JP4424698B2 - 電界効果トランジスタ・パッケージ - Google Patents

電界効果トランジスタ・パッケージ Download PDF

Info

Publication number
JP4424698B2
JP4424698B2 JP02679799A JP2679799A JP4424698B2 JP 4424698 B2 JP4424698 B2 JP 4424698B2 JP 02679799 A JP02679799 A JP 02679799A JP 2679799 A JP2679799 A JP 2679799A JP 4424698 B2 JP4424698 B2 JP 4424698B2
Authority
JP
Japan
Prior art keywords
fet
gate
fets
field effect
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP02679799A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11274370A5 (enExample
JPH11274370A (ja
Inventor
チャールズ・スティーブン・コーマン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of JPH11274370A publication Critical patent/JPH11274370A/ja
Publication of JPH11274370A5 publication Critical patent/JPH11274370A5/ja
Application granted granted Critical
Publication of JP4424698B2 publication Critical patent/JP4424698B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/072—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
JP02679799A 1998-02-17 1999-02-04 電界効果トランジスタ・パッケージ Expired - Fee Related JP4424698B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/024485 1998-02-17
US09/024,485 US5959357A (en) 1998-02-17 1998-02-17 Fet array for operation at different power levels

Publications (3)

Publication Number Publication Date
JPH11274370A JPH11274370A (ja) 1999-10-08
JPH11274370A5 JPH11274370A5 (enExample) 2008-07-17
JP4424698B2 true JP4424698B2 (ja) 2010-03-03

Family

ID=21820831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02679799A Expired - Fee Related JP4424698B2 (ja) 1998-02-17 1999-02-04 電界効果トランジスタ・パッケージ

Country Status (3)

Country Link
US (1) US5959357A (enExample)
EP (1) EP0938138A3 (enExample)
JP (1) JP4424698B2 (enExample)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100230428B1 (ko) * 1997-06-24 1999-11-15 윤종용 다층 도전성 패드를 구비하는 반도체장치 및 그 제조방법
US6057779A (en) * 1997-08-14 2000-05-02 Micron Technology, Inc. Method of controlling access to a movable container and to a compartment of a vehicle, and a secure cargo transportation system
US6356535B1 (en) * 1998-02-04 2002-03-12 Micron Technology, Inc. Communication systems and methods of communicating
EP1129480A1 (en) * 1998-10-05 2001-09-05 Kulicke & Soffa Investments, Inc Semiconductor copper bond pad surface protection
US6936531B2 (en) 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US10973397B2 (en) 1999-03-01 2021-04-13 West View Research, Llc Computerized information collection and processing apparatus
US8636648B2 (en) 1999-03-01 2014-01-28 West View Research, Llc Endoscopic smart probe
JP4094174B2 (ja) * 1999-06-04 2008-06-04 株式会社ルネサステクノロジ 半導体装置の製造方法
US8065155B1 (en) 1999-06-10 2011-11-22 Gazdzinski Robert F Adaptive advertising apparatus and methods
US7710273B2 (en) * 1999-09-02 2010-05-04 Round Rock Research, Llc Remote communication devices, radio frequency identification devices, wireless communication systems, wireless communication methods, radio frequency identification device communication methods, and methods of forming a remote communication device
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6713859B1 (en) * 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7498196B2 (en) 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
US7932603B2 (en) 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
JP3616605B2 (ja) * 2002-04-03 2005-02-02 沖電気工業株式会社 半導体装置
US7230273B2 (en) * 2002-06-13 2007-06-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device with a plurality of semiconductor elements each including a wide band-gap semiconductor
US7119437B2 (en) * 2002-12-26 2006-10-10 Yamaha Hatsudoki Kabushiki Kaisha Electronic substrate, power module and motor driver
US7427024B1 (en) 2003-12-17 2008-09-23 Gazdzinski Mark J Chattel management apparatus and methods
DE102004019447A1 (de) * 2004-04-19 2005-11-10 Siemens Ag Vorrichtung, insbesondere intelligentes Leistungsmodul, mit planarer Verbindungstechnik
US7560808B2 (en) * 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
US20090015407A1 (en) * 2007-07-13 2009-01-15 Micron Technology, Inc. Rifid tags and methods of designing rfid tags
US7777630B2 (en) * 2007-07-26 2010-08-17 Round Rock Research, Llc Methods and systems of RFID tags using RFID circuits and antennas having unmatched frequency ranges
US8179232B2 (en) * 2008-05-05 2012-05-15 Round Rock Research, Llc RFID interrogator with adjustable signal characteristics
US7852221B2 (en) * 2008-05-08 2010-12-14 Round Rock Research, Llc RFID devices using RFID circuits and antennas having unmatched frequency ranges
US8712334B2 (en) 2008-05-20 2014-04-29 Micron Technology, Inc. RFID device using single antenna for multiple resonant frequency ranges
US8053898B2 (en) * 2009-10-05 2011-11-08 Samsung Electronics Co., Ltd. Connection for off-chip electrostatic discharge protection
US8847293B2 (en) * 2012-03-02 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US9337163B2 (en) * 2012-11-13 2016-05-10 General Electric Company Low profile surface mount package with isolated tab
US9006584B2 (en) * 2013-08-06 2015-04-14 Texas Instruments Incorporated High voltage polymer dielectric capacitor isolation device
US9899484B1 (en) * 2016-12-30 2018-02-20 Texas Instruments Incorporated Transistor with source field plates under gate runner layers
JP2025030915A (ja) * 2023-08-24 2025-03-07 新光電気工業株式会社 半導体装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4182023A (en) * 1977-10-21 1980-01-08 Ncr Corporation Process for minimum overlap silicon gate devices
US4198250A (en) * 1979-02-05 1980-04-15 Intel Corporation Shadow masking process for forming source and drain regions for field-effect transistors and like regions
US4343078A (en) * 1979-03-05 1982-08-10 Nippon Electric Co., Ltd. IGFET Forming method
CA1198226A (en) * 1982-06-01 1985-12-17 Eliezer Kinsbron Method for manufacturing a semiconductor device
US4471524A (en) * 1982-06-01 1984-09-18 At&T Bell Laboratories Method for manufacturing an insulated gate field effect transistor device
JPH06101652B2 (ja) * 1987-02-12 1994-12-12 三菱電機株式会社 バイアス回路
US4783695A (en) * 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US5384691A (en) * 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
US5696403A (en) * 1993-10-25 1997-12-09 Lsi Logic Corporation System having input-output drive reduction
US5455442A (en) * 1993-11-17 1995-10-03 Harris Corporation COMFET switch and method
US5498556A (en) * 1995-01-10 1996-03-12 United Microelectronics Corp. Metal-oxide-semiconductor field-effect transistor and its method of fabrication

Also Published As

Publication number Publication date
JPH11274370A (ja) 1999-10-08
EP0938138A3 (en) 2003-08-20
US5959357A (en) 1999-09-28
EP0938138A2 (en) 1999-08-25

Similar Documents

Publication Publication Date Title
JP4424698B2 (ja) 電界効果トランジスタ・パッケージ
JP4192396B2 (ja) 半導体スイッチングモジュ−ル及びそれを用いた半導体装置
US10665398B1 (en) Direct current solid-state switch
US20250379124A1 (en) Power circuit module
CN210349834U (zh) 双面散热的功率器件模组
EP2899756A1 (en) Semiconductor device
US10573585B2 (en) Power converter having a conductive clip
US7019362B2 (en) Power MOSFET with reduced dgate resistance
US5366932A (en) Semi-conductor chip packaging method and semi-conductor chip having interdigitated gate runners with gate bonding pads
US20040095729A1 (en) Non-isolated heatsink(s) for power modules
CN113748509B (zh) 半导体装置
EP3703123B1 (en) Semiconductor component and semiconductor package
US11133303B2 (en) Semiconductor device and semiconductor arrangement comprising semiconductor devices
KR20220004442A (ko) 파워모듈
CN112951819A (zh) 半导体器件模块及组装方法
JP3525823B2 (ja) 相補型ｉｇｂｔの実装構造
JP7736907B2 (ja) ターンオン／ターンオフ挙動のバランスのための非対称な集積集中ゲート抵抗器及び／又はパワー処理の向上のための複数の離間した集中ゲート抵抗器を有する半導体デバイス
US20240243097A1 (en) Power module package structure
EP3660896A1 (en) Semiconductor arrangement
CN101019217A (zh) 具有公共引线框架上的倒装芯片设备的半导体设备模块
KR102816898B1 (ko) 파워모듈
JP2003007969A (ja) 半導体モジュール及び電力変換装置
KR101754923B1 (ko) 고 전자이동도 트랜지스터 기반 전력 모듈
CN117730407A (zh) 具有用于平衡接通/关断行为的不对称集成集总栅极电阻器和/或用于改善功率处置的多个间隔开的集总栅极电阻器的半导体器件
CN119522483A (zh) 半导体器件

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060201

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080602

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090113

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090223

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20090401

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090401

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090915

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091008

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091117

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091207

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121218

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees