JP4363227B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a power element and a drive circuit for driving the power element are integrated.

  Conventionally, in a semiconductor integrated circuit device in which a core and a peripheral function circuit are mounted on the same substrate, a block in which pads are arranged around the core is provided, and a block between the block and the block having the peripheral function circuit is provided between the blocks. A technique is disclosed in which a dicing region is provided that can cut a chip without impairing the function of each block by crossing only the connection wiring (see Patent Document 1).

According to the technique of this patent document 1, when manufacturing a product of a different specification from a semiconductor chip having a basic structure, a semiconductor integrated circuit device divided into blocks is formed in advance using a set of masks, and the semiconductor is manufactured by a wafer process. By cutting the dicing area provided on the chip and deleting unnecessary peripheral function circuits, it is possible to develop different types of products only in the cutting process.
Japanese Patent Laying-Open No. 2003-273229 (pages 2 to 4 in FIG. 1)

  In recent years, a semiconductor device (power monolithic IC) in which a power element (output transistor) and a drive circuit for the power element are integrated on a single semiconductor chip has been widely used. , Speakers, electric motors, various solenoids, etc.).

Conventionally, this semiconductor device generally has a single channel configuration (single function configuration) in which one power element is mounted on one semiconductor chip and one channel output can be obtained.
However, in recent years, there has been a demand for a semiconductor device having a multi-channel configuration (multi-functional configuration) in which two or more power elements are mounted on one semiconductor chip to obtain a multi-channel output.

  FIG. 4A is a main part schematic plan view showing an arrangement example of a conventional single-channel configuration semiconductor chip 51 formed on a semiconductor wafer (semiconductor substrate) WF. FIG. 4B is a schematic plan view showing one single-channel configuration semiconductor chip 51 cut out from the semiconductor wafer WF by dicing.

On the plane of the disk-shaped semiconductor wafer WF, a plurality of identical single-channel configuration semiconductor chips 51 are arranged in a grid pattern in the vertical and horizontal directions. A dicing line (dicing area) DL for cutting out each semiconductor chip 51 from the semiconductor wafer WF by dicing is set between the semiconductor chips 51.
In other words, the plane of the semiconductor wafer WF is divided into grids by dicing lines DL arranged in a grid pattern in the vertical and horizontal directions orthogonal to each other, and each of the rectangular grids of the divided semiconductor wafer WF has a single channel configuration. The semiconductor chip 51 is formed.

On the single-channel semiconductor chip 51, one power element PE, a drive circuit DC for driving the power element PE, and a plurality of electrode pads (bonding pads) PD are integrated.
The single channel semiconductor chip 51 constitutes one power monolithic IC (Integrated Circuit).

The power element PE is various active elements (for example, bipolar transistors, JFETs, MOSFETs, thyristors, etc.) that perform power amplification.
Each electrode pad PD is connected to the power element PE or the drive circuit DC by a wiring layer (not shown) made of a conductive film formed on the single channel configuration semiconductor chip 51, and the single channel configuration semiconductor chip 51 is mounted. A lead frame (not shown) is wire-bonded with a bonding wire (not shown). The electrode pads PD are provided for various purposes (for example, for power supply, ground, input signal, output signal, etc.).

FIG. 5A is a main part schematic plan view showing an arrangement example of a conventional two-channel configuration semiconductor chip 61 formed on a semiconductor wafer WF. FIG. 5B is a schematic plan view showing one two-channel configuration semiconductor chip 61 cut out from the semiconductor wafer WF by dicing.
On the two-channel semiconductor chip 61, two power elements PE, one drive circuit DC for driving the power elements PE, and a plurality of electrode pads PD are integrated.

FIG. 6A is a main part schematic plan view showing an arrangement example of a conventional 4-channel configuration semiconductor chip 71 formed on a semiconductor wafer WF. FIG. 6B is a schematic plan view showing one 4-channel configuration semiconductor chip 71 cut out from the semiconductor wafer WF by dicing.
On the four-channel configuration semiconductor chip 61, four power elements PE, one drive circuit DC for driving the power elements PE, and a plurality of electrode pads PD are integrated.

In order to manufacture these semiconductor chips 51, 61, 71, first, a drawing pattern corresponding to the circuit constituent members (power element PE, drive circuit DC, wiring layer, electrode pad PD) of each semiconductor chip 51, 61, 71. A photomask on which is formed is prepared.
Next, using a photolithography technique, the drawing pattern of the photomask is transferred to the photoresist film applied onto the semiconductor wafer WF, and the unnecessary photoresist film is removed.

  Then, using the photoresist film to which the drawing pattern of the photomask is transferred as a protective film, various semiconductor device manufacturing methods such as an etching method, a CVD (Chemical Vapor Deposition) method, a PVD (Physical Vapor Deposition) method, etc. are used. Circuit components of the semiconductor chips 51, 61, 71 are formed by injecting impurities or forming an insulating film, a wiring layer, or the like.

It should be noted that the photomask drawing pattern transfer process by photolithography is repeated several times to create a target circuit component, and the photomask is replaced each time the transfer process is performed.
At present, the mainstream photomask is an enlarged mask drawn four or five times larger than the drawing pattern, and this enlarged mask is called a reticle.

As described above, each of the conventional semiconductor chips 51, 61, 71 is formed on a separate semiconductor wafer WF. In addition, a photomask used for manufacturing each semiconductor chip 51, 61, 71 is also prepared separately for each semiconductor chip 51, 61, 71. That is, each semiconductor chip 51, 61, 71 is designed and developed completely separately and manufactured.
Therefore, in order to manufacture each of the conventional semiconductor chips 51, 61, 71, there is a problem that it takes a lot of time and cost for the design and development including the production of the photomask.

Further, even when the shipment number (production number) of each semiconductor chip 51, 61, 71 is smaller than the number that can be created from one semiconductor wafer WF, one semiconductor wafer for each semiconductor chip 51, 61, 71. Since the WF is used, there is a problem that the manufacturing cost increases as the semiconductor wafer WF is wasted. That is, the manufacturing cost increases especially for the semiconductor chips 51, 61, 71 with a small number of shipments.
For example, if the number of single-channel semiconductor chips 51 shipped is 1500 and 2000 semiconductor chips 51 can be created from one semiconductor wafer WF, 500 extra semiconductor chips 51 are required. Only one semiconductor wafer WF is wasted.

By the way, the technique disclosed in Patent Document 1 cannot be used to solve the above problems.
That is, Patent Document 1 has no description of a multi-channel semiconductor device (a semiconductor device in which a plurality of power elements of two or more are mounted on one semiconductor chip to obtain a multi-channel output), There is no suggestion of application to a multi-channel semiconductor device.

In Patent Document 1, a core composed of minimum components for operating as a semiconductor integrated circuit device and a peripheral function circuit that assists the function of the core or adds a function that is not included in the core are provided on the same substrate. It is only described that it is installed.
And since the technique of patent document 1 cut | disconnects a core and a peripheral function circuit, even if it applies the said core to the power element PE and applies the said peripheral function circuit to the drive circuit DC, said each problem It cannot be solved.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a plurality of power elements in a semiconductor device in which a power element and a drive circuit for driving the power element are integrated. Is to provide a multi-channel semiconductor device that can obtain an output of a plurality of channels at a low cost.

( Claim 1 : Corresponding to the 4-channel semiconductor chip 41 shown in FIG. 2C)
The invention described in claim 1
A basic cell in which one power element and a driving circuit for driving the power element are integrated;
A semiconductor wafer in which a plurality of basic cells are arranged in the vertical and horizontal directions;
A dicing line provided between the basic cells in the semiconductor wafer;
A semiconductor device comprising:
The power element and the driving circuit are arranged side by side in the first direction on the basic cell,
In each of the basic cells arranged in the first direction on the semiconductor wafer, a second basic cell adjacent to an arbitrary first basic cell is in relation to the first basic cell with respect to the second basic cell. It is placed in a state rotated 180 ° around the center
Comprising one semiconductor chip consisting of the four basic cells separated from the semiconductor wafer along the dicing line;
When the two basic cells adjacent to each other in the first direction on the semiconductor wafer and the drive circuits on the basic cells are adjacent to each other as a set, the four basic cells are the two basic cells. A technical feature is that two basic cells are provided.

( Claim 2 : Corresponds to the two-channel semiconductor chip 31 shown in FIG. 3B)
The invention according to claim 2 is the semiconductor device according to claim 1 ,
In each basic cell, a plurality of electrode pads connected to the power element or the driving circuit are integrated,
The technical feature is that the arrangement location and number of the electrode pads differ depending on the basic cells arranged on the semiconductor wafer.

(Claim 1)
In the first aspect of the present invention, each basic cell cut out from a semiconductor wafer by dicing can be regarded as one functional block. Therefore, by setting the number of basic cells cut out from the semiconductor wafer to a desired number of channels, it is possible to freely select and manufacture each semiconductor chip having a single channel configuration, a two channel configuration, and a four channel configuration. In other words, an arbitrary number of channel-configured semiconductor chips (single-channel configured semiconductor chip, 2-channel configured semiconductor chip, 4-channel configured semiconductor chip) can be mixed from a single semiconductor wafer by simply setting dicing lines to be separated. Can be manufactured.

In addition, in order to manufacture a semiconductor wafer in which each basic cell is arranged, it is only necessary to prepare a photomask corresponding to the arrangement of each basic cell, and it is necessary to prepare a separate photomask for each channel configuration semiconductor chip. Absent. That is, each channel constituent semiconductor chip is designed and developed at the same time, and its manufacturing process is the same up to the dicing process, and it is determined which of the channel constituent semiconductor chips to manufacture in the dicing process.
Therefore, according to the first aspect of the present invention, compared to the prior art, the time and cost required for the design and development including the production of the photomask can be greatly reduced.

According to the first aspect of the present invention, since any number of channel-configured semiconductor chips can be mixed and manufactured from a single semiconductor wafer, the semiconductor wafer can be used regardless of the shipment number (production number) of each channel-configured semiconductor chip. Manufacturing costs can be reduced since waste is not wasted.
In other words, when there is a remaining basic cell after a desired number of 2-channel or 4-channel semiconductor chips are formed from a single semiconductor wafer, the remaining basic cells may be converted into single-channel semiconductor chips. Therefore, the semiconductor wafer is not wasted.

According to the first aspect of the invention, a four-channel semiconductor chip can be obtained.
In the four-channel configuration semiconductor chip, four power elements are arranged apart from the four corners of the semiconductor chip, and two drive circuits are arranged two by two in the vertical and horizontal directions between the power elements. . Therefore, the heat dissipation of each power element is promoted, and the temperature rise of the semiconductor chip due to the heat generated by each power element can be suppressed. In addition, when electrode pads are arranged in the vicinity of each power element, it is possible to prevent the bonding wires from becoming complicated when wire bonding is performed on the electrode pads, and wire bonding is facilitated.

( Claim 2 )
According to the second aspect of the present invention, it is possible to make the arrangement location and number of each electrode pad different for each basic cell, so that the electrode pad can be shared in one semiconductor chip according to the use of the electrode pad. .
For example, only one set of power supply electrode pads and ground electrode pads may be provided on one semiconductor chip, and the electrode pads may be shared by the basic cells constituting the semiconductor chip.

This is because each electrode pad is composed of the uppermost wiring layer formed on the basic cell, so that each electrode pad can be replaced by simply replacing the photomask on which a drawing pattern corresponding to each electrode pad is formed. This is because the arrangement location and number of the can be easily changed.
Since in comparison to change the arrangement position of the power device and the drive circuit, is easy to change the arrangement position and the number of the electrode pads, there is almost no increase in manufacturing cost due to the change, according to claim 1 The above-mentioned effect of the invention is not inhibited.

  Hereinafter, an embodiment embodying the present invention will be described with reference to the drawings. In the present embodiment, the same constituent members as those in the prior art are denoted by the same reference numerals.

  FIG. 1 is a main part schematic plan view showing an arrangement example of the basic cells 11 of the present embodiment formed on a semiconductor wafer (semiconductor substrate) WF. In the drawings and the following description, symbols “a” to “h” are appended to the end of the symbol “11” to distinguish the basic cells 11.

On the plane of the disk-shaped semiconductor wafer WF, a plurality of the same basic cells 11 (11a to 11h) are arranged in a grid pattern in the vertical and horizontal directions. A temporary dicing line (dicing area) DLt for cutting out a desired basic cell 11 from the semiconductor wafer WF by dicing is set between the basic cells 11.
That is, the plane of the semiconductor wafer WF is divided into grids by dicing lines DLt arranged in a grid pattern in the vertical and horizontal directions orthogonal to each other, and each of the rectangular grids of the divided semiconductor wafer WF is a basic cell 11. It becomes.

  On the basic cell 11, one power element PE, a drive circuit DC for driving the power element PE, and a plurality of electrode pads (bonding pads) PD are integrated. The basic cell 11 constitutes one power monolithic IC.

On the basic cell 11, the power element PE and the drive circuit DC are arranged side by side in the longitudinal direction of the basic cell 11 (lateral direction shown in FIG. 1).
Then, in each basic cell 11 arranged in the horizontal direction (first direction) shown in FIG. 1 on the semiconductor wafer WF, a basic cell (second basic cell) adjacent to an arbitrary basic cell (first basic cell) 11. ) 11 is arranged with respect to the arbitrary basic cell (first basic cell) 11 in a state of being rotated 180 ° with the center of the adjacent basic cell (second basic cell) 11 as the rotation axis.

  That is, in each of the basic cells 11e to 11h arranged in the horizontal direction (first direction) shown in FIG. 1, the second basic cells 11a and 11c adjacent to the first basic cell 11b are in relation to the first basic cell 11b. The second basic cells 11a and 11c are arranged in a state of being rotated by 180 ° about the center of rotation. The second basic cells 11b and 11d adjacent to the first basic cell 11c are arranged in a state of being rotated 180 ° with respect to the first basic cell 11c with the center of the second basic cells 11b and 11d as the rotation axis. Yes.

  Similarly, in each of the basic cells 11a to 11d arranged in the horizontal direction (first direction) shown in FIG. 1, the second basic cells 11e and 11g adjacent to the first basic cell 11f are different from the first basic cell 11f. The second basic cells 11e and 11g are arranged in a state rotated by 180 ° with the center as the rotation axis. The second basic cells 11f and 11h adjacent to the first basic cell 11g are arranged in a state rotated by 180 ° with respect to the first basic cell 11g with the center of the second basic cells 11f and 11h as the rotation axis. Yes.

Therefore, in order to create a photomask used for manufacturing the semiconductor wafer WF of this embodiment, first, it corresponds to the circuit constituent members (power element PE, drive circuit DC, wiring layer, electrode pad PD) of the basic cell 11a. Create a drawing pattern.
Then, the drawing pattern of the basic cell 11a is rotated by 180 ° to create the drawing pattern of the basic cell 11b, and a set of drawing patterns of the basic cells 11a and 11b is taken as one set. If the drawing patterns for one horizontal row are arranged in the horizontal direction and the drawing patterns for the horizontal row are arranged in the vertical direction, a photomask for the entire semiconductor wafer WF can be created.

  Using the photomask created in this way, as in the prior art, a photolithography technique is used to form a photoresist film to which the drawing pattern of the photomask has been transferred, and the photoresist film is used as a protective film for various semiconductors. If an apparatus manufacturing method (such as an etching method, a CVD method, or a PVD method) is used, each basic cell 11 (11a to 11h) can be created.

  FIG. 2 is a schematic plan view showing the respective semiconductor chips 21, 31, 41 created by cutting out a desired basic cell 11 from the semiconductor wafer WF by dicing.

FIG. 2A shows an example in which one basic cell 11a is cut out from the semiconductor wafer WF, and one single-channel configuration semiconductor chip 21 is configured by the basic cell 11a.
In order to manufacture the single-channel semiconductor chip 21, the basic cell 11a may be separated from the semiconductor wafer WF by cutting the semiconductor wafer WF along the dicing line DLt surrounding the outer periphery of the basic cell 11a.

FIG. 2B shows an example in which two basic cells 11a and 11b adjacent in the horizontal direction in the figure are cut out from the semiconductor wafer WF, and a single two-channel semiconductor chip 31 is configured by these basic cells 11a and 11b. The
That is, on the two-channel configuration semiconductor chip 31, two power elements PE, two drive circuits DC for driving the power elements PE, and a plurality of electrode pads PD are integrated. .

The two basic cells 11a and 11b are adjacent to each other in the horizontal direction (first direction) shown in FIG. 1 on the semiconductor wafer WF, and the drive circuits DC on the basic cells 11a and 11b are adjacent to each other.
In order to manufacture the two-channel semiconductor chip 31, the semiconductor wafer WF is cut along the dicing line DLt surrounding the outer periphery of each basic cell 11a, 11b, and the dicing line DLt between each basic cell 11a, 11b is The basic cells 11a and 11b may be separated from the semiconductor wafer WF by leaving them as they are.

FIG. 2C shows an example in which four basic cells 11a, 11b, 11e, and 11f adjacent in the horizontal direction and the vertical direction are cut out from the semiconductor wafer WF, and these basic cells 11a, 11b, 11e, and 11f are cut out. One 4-channel semiconductor chip 41 is formed.
That is, on the four-channel configuration semiconductor chip 41, four power elements PE, four drive circuits DC for driving the power elements PE, and a plurality of electrode pads PD are integrated. .
The 4-channel semiconductor chip 41 is used, for example, to drive and control an electric motor or the like by an H bridge circuit formed by four power elements PE.

Similar to the two basic cells 11a and 11b, the two basic cells 11e and 11f are adjacent to each other in the horizontal direction (first direction) shown in FIG. 1 on the semiconductor wafer WF and on each basic cell 11e and 11f. The drive circuits DC are adjacent to each other.
Here, a set of two basic cells 11 adjacent to each other in the lateral direction (first direction) shown in FIG. 1 on the semiconductor wafer WF and adjacent to the drive circuits DC on each basic cell 11 is taken as one set. Then, the four basic cells 11a, 11b, 11e, and 11f have two sets of basics including one set including the two basic cells 11a and 11b and one set including the two basic cells 11e and 11f. It consists of cells 11. That is, the four basic cells 11a, 11b, 11e, and 11f include two sets of two basic cells (11a, 11b and 11e, 11f).

  In order to manufacture the four-channel semiconductor chip 41, the semiconductor wafer WF is cut along the dicing line DLt surrounding the outer periphery of each basic cell 11a, 11b, 11e, 11f, and each basic cell 11a, 11b, 11e. , 11f, the basic cells 11a, 11b, 11e, 11f may be separated from the semiconductor wafer WF by leaving the dicing line DLt remaining.

[Operations and effects of the embodiment]
According to the embodiment described above in detail, the following actions and effects can be obtained.

[1] Each basic cell 11 cut out from the semiconductor wafer WF by dicing is the same as the conventional single-channel semiconductor chip 51 shown in FIG. 4 and can be regarded as one functional block.
Therefore, by making the number of basic cells 11 cut out from the semiconductor wafer WF the desired number of channels, the semiconductor chips 21, 31, 41 shown in FIGS. 2 (A) to 2 (C) can be freely selected and manufactured. it can. That is, an arbitrary number of semiconductor chips 21, 31, 41 can be mixed and manufactured from one semiconductor wafer WF by simply setting the dicing line DLt to be separated.

In order to manufacture the semiconductor wafer WF in which the basic cells 11 are arranged, it is only necessary to prepare a photomask corresponding to the arrangement of the basic cells 11 shown in FIG. There is no need to prepare a separate photomask.
That is, the semiconductor chips 21, 31, 41 are designed and developed at the same time, and the manufacturing process is the same up to the dicing process, and it is determined which of the semiconductor chips 21, 31, 41 is manufactured in the dicing process. Is done.

  Therefore, according to the present embodiment, the time and cost required for the design and development including the production of the photomask are greatly increased as compared with the conventional technique for manufacturing the semiconductor chips 51, 61 and 71 shown in FIGS. Can be reduced.

[2] Since any number of semiconductor chips 21, 31, 41 can be manufactured from a single semiconductor wafer WF, the semiconductors can be manufactured regardless of the shipment number (production number) of the semiconductor chips 21, 31, 41. Since the wafer WF is not wasted, the manufacturing cost can be suppressed.
That is, if there is a surplus basic cell 11 after a desired number of semiconductor chips 31 and 41 are formed from one semiconductor wafer WF, the surplus basic cell 11 can be used as a single-channel configuration semiconductor chip 21. Because it is good, the semiconductor wafer WF is not wasted.

[3] In the two-channel configuration semiconductor chip 31, two power elements PE are arranged apart from each other in the longitudinal direction (first direction) of the semiconductor chip 31, and two power elements PE are provided between the power elements PE. Drive circuits DC are arranged in the longitudinal direction.
Further, in the four-channel configuration semiconductor chip 41, four power elements PE are arranged apart from the four corners of the semiconductor chip 41, and four drive circuits DC are arranged in the vertical and horizontal directions between the power elements PE. They are arranged one by one.

Therefore, the heat dissipation of each power element PE is promoted, and the temperature rise of each semiconductor chip 31, 41 due to the heat generated by each power element PE can be suppressed.
Further, when wire bonding is performed on the electrode pads PD in the vicinity of each power element PE, it is possible to prevent the bonding wires (not shown) from being complicated, and wire bonding is facilitated.

[Another embodiment]
In the embodiment described above, the center of the basic cell 11 is used as the rotation axis for all circuit components (power element PE, drive circuit DC, wiring layer, electrode pad PD) of the basic cell 11 adjacent in the horizontal direction shown in FIG. One adjacent basic cell 11 is arranged in a state rotated by 180 °.
However, the arrangement location and the number of electrode pads PD may differ depending on the basic cells 11 arranged on the semiconductor wafer WF.

This is because each electrode pad PD is constituted by the uppermost wiring layer formed on the basic cell 11, so that only by replacing the photomask on which the drawing pattern corresponding to each electrode pad PD is formed, This is because the location and number of electrode pads PD can be easily changed.
And, compared to changing the placement location of the power element PE and drive circuit DC, it is easy to change the placement location and number of each electrode pad PD, there is almost no increase in manufacturing cost due to the change, The effect of the above embodiment is not hindered.

FIG. 3A is a schematic plan view showing the same two-channel configuration semiconductor chip 31 as shown in FIG.
Each basic cell 11a, 11b is provided with a power supply electrode pad PDa and a ground electrode pad PDb.
The electrode pads PDa and PDb of the basic cell 11a are connected only to the power element PE and the drive circuit DC on the basic cell 11a by a wiring layer (not shown) made of a conductive film formed on the basic cell 11a. .
Each electrode pad PDa, PDb of the basic cell 11b is connected only to the power element PE and the drive circuit DC on the basic cell 11b by a wiring layer (not shown) made of a conductive film formed on the basic cell 11b. .

FIG. 3B is a schematic plan view showing a two-channel configuration semiconductor chip 31 of another embodiment.
The basic cell 11a is provided with a power supply electrode pad PDa and a ground electrode pad PDb, whereas the basic cell 11b is not provided with each electrode pad PDa, PDb.
Each electrode pad PDa, PDb is connected to each power element PE on each basic cell 11a, 11b and each drive circuit DC by a wiring layer (not shown) made of a conductive film formed on each basic cell 11a, 11b. Has been.

  That is, in the semiconductor chip 31 shown in FIG. 3A, two sets of independent electrode pads PDa and PDb are provided for each basic cell 11a and 11b. On the other hand, in the semiconductor chip 31 shown in FIG. 3B, only one set of electrode pads PDa and PDb shared by the basic cells 11a and 11b is provided.

FIG. 3B shows an example of the two-channel configuration semiconductor chip 31. Also in the four-channel configuration semiconductor chip 41, each basic cell 11a, 11b, 11e, 11f has one electrode pad PDa, PDb shared by one. Only a set may be provided.
Further, not only the power supply and ground electrode pads PD but also electrode pads PD for other purposes (for example, for input signals and output signals) may be shared by the plurality of basic cells 11.

The principal part schematic plan view which shows the example of arrangement | positioning of the basic cell 11 formed on the semiconductor wafer WF in one Embodiment which actualized this invention. FIG. 3 is a schematic plan view showing each semiconductor chip (single-channel configuration semiconductor chip 21, 1, 2-channel configuration semiconductor chip 31, 4-channel configuration semiconductor chip 41) cut out from the semiconductor wafer WF by dicing. The schematic plan view for demonstrating the two-channel structure semiconductor chip 31 in another embodiment which actualized this invention. FIG. 4A is a schematic plan view of an essential part showing an arrangement example of a conventional single channel configuration semiconductor chip 51 formed on a semiconductor wafer WF. FIG. 4B is a schematic plan view showing one single-channel configuration semiconductor chip 51 cut out from the semiconductor wafer WF by dicing. FIG. 5A is a main part schematic plan view showing an arrangement example of a conventional two-channel configuration semiconductor chip 61 formed on a semiconductor wafer WF. FIG. 5B is a schematic plan view showing one two-channel configuration semiconductor chip 61 cut out from the semiconductor wafer WF by dicing. FIG. 6A is a schematic plan view of a main part showing an arrangement example of a conventional 4-channel configuration semiconductor chip 71 formed on a semiconductor wafer WF. FIG. 6B is a schematic plan view showing one 4-channel configuration semiconductor chip 71 cut out from the semiconductor wafer WF by dicing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 (11a-11h) ... Basic cell 21 ... Single channel structure semiconductor chip 31 ... 2 channel structure semiconductor chip 41 ... 4 channel structure semiconductor chip
WF ... Semiconductor wafer
DLt ... Dicing line
PE ... Power element
DC ... Drive circuit
PD, PDa, PDb ... electrode pads

Claims (2)

A basic cell in which one power element and a driving circuit for driving the power element are integrated;
A semiconductor wafer in which a plurality of basic cells are arranged in the vertical and horizontal directions;
A semiconductor device comprising a dicing line provided between the basic cells in the semiconductor wafer,
The power element and the driving circuit are arranged side by side in the first direction on the basic cell,
In each of the basic cells arranged in the first direction on the semiconductor wafer, a second basic cell adjacent to an arbitrary first basic cell is in relation to the first basic cell with respect to the second basic cell. are arranged centered in a state of being rotated 180 ° as a rotation axis,
Comprising one semiconductor chip consisting of the four basic cells separated from the semiconductor wafer along the dicing line;
When two basic cells are adjacent to each other in the first direction on the semiconductor wafer and the drive circuits on the basic cells are adjacent to each other,
The four basic cells include two sets of the two basic cells . The semiconductor device according to claim 1 ,
In each basic cell, a plurality of electrode pads connected to the power element or the driving circuit are integrated,
The semiconductor device according to claim 1, wherein the arrangement location and the number of the electrode pads differ depending on the basic cells arranged on the semiconductor wafer.

Images