JP2008270429A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize influence to a chip area when biasing a substrate for performance correction. <P>SOLUTION: A semiconductor integrated circuit device has a functional block. The functional block has a plurality of rows in which a plurality of primitive cells 31 for carrying out predetermined operations are provided respectively and a plurality of substrate contact cells 32 provided in the rows for respectively supplying substrate potential to the plurality of primitive cells 31. The plurality of substrate contact cells 32 are respectively provided to meet predetermined distance standard for the adjacent primitive cell 31 to which the substrate potential is supplied and linearly provided along the direction orthogonal to the rows. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device that improves chip performance and reduces the rate of increase in chip area.

  In recent years, with the miniaturization of devices, there has been a problem that variations in the performance of integrated circuits increase. Considering that the demand for device miniaturization will continue in the future, the scale of integrated circuits will increase and the system will become complicated. For this reason, it is very difficult to design an integrated circuit that allows such variations.

  On the other hand, a technique for improving chip performance by threshold correction using a substrate bias is known. In this chip performance improvement technology, the performance of the completed chip is measured, and when it is off the target, the threshold value of the transistor is adjusted using the substrate bias to bring the chip performance closer to the target. Several reports have been reported on large-scale system LSIs.

  However, when such a chip performance improvement technique is used, a wiring for supplying a substrate potential is replaced with a VDD metal instead of a substrate contact for fixing a substrate (well) provided in a primitive cell to a power source. Since it is provided separately from the wiring and the VSS metal wiring, the chip performance can be improved, but the area at the cell level is increased and the chip area is greatly increased.

That is, in the conventional semiconductor integrated circuit device, improvement in chip performance and reduction in the increase rate of the chip area are in a trade-off relationship, and it has not been possible to achieve both at the same time.
JP 2003-133416 A

  An object of the present invention is to minimize the influence on the chip area when applying a substrate bias for performing performance correction.

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device having a functional block, wherein the functional block includes a plurality of rows in which a plurality of primitive cells for performing a predetermined operation are respectively arranged, and the rows. A plurality of substrate contact cells provided to supply a substrate potential to each of the plurality of primitive cells, each of the plurality of substrate contact cells being constant with respect to neighboring primitive cells to which the substrate potential is supplied; A semiconductor integrated circuit device is provided, which is provided so as to satisfy the distance standard of and arranged linearly with respect to a direction orthogonal to the row.

  According to the present invention, when a substrate bias for performing performance correction is applied, the influence on the chip area can be minimized, and at the same time, improvement of the chip performance and reduction of the increase rate of the chip area can be simultaneously performed. Can be achieved.

  Embodiments of the present invention will be described below with reference to the drawings. The following examples are one embodiment of the present invention and do not limit the scope of the present invention.

  First, Embodiment 1 of the present invention will be described with reference to the drawings. In the first embodiment of the present invention, an example will be described in which the substrate contact cells 32 are provided so as to satisfy a certain distance standard with respect to neighboring primitive cells 31 and are arranged linearly in a direction perpendicular to the row. .

  FIG. 1 is a schematic diagram showing a layout of functional blocks of a semiconductor integrated circuit according to a first embodiment of the present invention.

  The semiconductor integrated circuit according to the first embodiment of the present invention includes an N well 1 that is a substrate of a PMOS transistor and a P well 2 that is a substrate of an NMOS transistor.

  The VDD metal wiring 11 is provided in the N well 1. The VSS metal wiring 12 is provided in the P well 2. The power supply trunk lines 13 and 14 are provided so as to straddle the N well 1 and the P well 2. Rows A to G are provided in a region sandwiched between the VDD metal wiring 11 and the VSS metal wiring 12. Rows A to G are provided with a primitive cell 31, a substrate contact cell 32, and a substrate bias application circuit 33, which will be described later.

  The substrate wiring VBP21 and the substrate wiring VBN22, and the substrate wiring VBP23 and the substrate wiring VBN24 are connected to a substrate contact cell 32 described later.

  Each row is connected to a primitive cell 31, a substrate contact cell 32, and a substrate bias application circuit 33 of the semiconductor integrated circuit device.

  The primitive cell 31 is a cell that performs a predetermined operation. In each row, the primitive cell 31 has a constant distance from a substrate contact cell 32 described later (within a fixed distance between the primitive cell 31 and the substrate contact cell 32 closest to the primitive cell 31). It is provided so as to satisfy.

  The substrate contact cell 32 is a cell that supplies a substrate potential to the primitive cell 31 via the N well 1 and the P well 2. The substrate contact cells 32 are arranged in a straight line with respect to the direction orthogonal to each row. That is, in the functional block, the substrate contact cells 32 are arranged in a lattice pattern. In the first embodiment of the present invention, the number of substrate contact cells 32 is 20 (4 columns in the row direction and 5 columns in the direction orthogonal to each row), but is not limited thereto.

  In particular, when a standard cell is used, the primitive cell 31 and the substrate contact cell are provided because the standard cell is provided so as to share a well in adjacent rows (for example, share a P well 2 in rows A and B). Rows provided with 32 (for example, rows A, C, E, and H) and rows not provided (B, D, F, and G) are alternately arranged. That is, in the functional block, the substrate contact cells 32 are arranged in a lattice pattern.

  The substrate bias application circuit 33 is a circuit for applying a substrate bias for performing performance correction to the N well 1 and the P well 2. The substrate bias applying circuit 33 is provided in the row A at the ends of the N well 1 and the P well 2.

  The substrate contact cell 32, the substrate wiring VBP21 and the substrate wiring VBN22, and the substrate bias applying circuit 33, the substrate wiring VBP23 and the substrate wiring VBN24 are linearly connected using an upper wiring layer (not shown).

  In circuit design, the connection between the substrate contact cell 32 and the substrate wiring VBP21 and the substrate wiring VBN22, and the connection between the substrate bias application circuit 33 and the substrate wiring VBP23 and the substrate wiring VBN24 are the arrangement and wiring of the primitive cells 31 constituting the logic circuit. Is given priority over.

  FIG. 1 shows the arrangement of the substrate contact cells 31 between the power supply trunk line 13 and the power supply trunk line 14 and the layout of the wiring. At the functional block level, the power supply trunk line 13 and the power supply trunk line 14 are repeated over the entire functional block. It is. In each functional block, substrate wiring is performed in consideration of the appropriate number and interval of rows of substrate contacts 31 between the power supply trunk line 13 and the power supply trunk line 14.

  FIG. 2 is a schematic diagram showing a layout of the substrate contact cell 32 according to the first embodiment of the present invention.

  The substrate contact cell 32 according to the first embodiment of the present invention includes an N + diffusion 321, a P + diffusion 322, a substrate contact 323, and a via 324 in the cell frame 320. In the substrate contact cell 32 according to the first embodiment of the present invention, the VDD metal wiring 11 and the VSS metal wiring 12 for supplying the substrate potential are separately provided.

  The VDD metal wiring 11 gives a substrate potential to the N + diffusion 321. The VSS metal wiring 12 applies a substrate potential to the P + diffusion 322. The substrate contact 323 is provided on the N + diffusion 321 and the P + diffusion 322 and connects the N well 1 and the P well 2 with the VDD metal wiring 11 and the VSS metal wiring 12.

  FIG. 3 is a schematic diagram showing a distance reference between the primitive cell 31 and the substrate contact cell 32 according to the first embodiment of the present invention.

  As described above, the substrate contact cells 32 according to the first embodiment of the present invention are arranged in a lattice pattern in the functional block. Each substrate contact cell 32 is provided at a predetermined interval (a) with respect to the row direction. The primitive cell 31 is provided so as to be included in a region (cover region) in which the distance from the neighboring substrate contact cell 32 is not more than a certain distance reference value (b) from the substrate contact 323 of the substrate contact cell 32. . That is, when the primitive cell 31 is included in the cover region in the same well centered on the substrate contact 323 of the substrate contact cell 32, the distance criterion is satisfied.

  For example, as shown in FIG. 3, the cover region B of the substrate contact A provided in the P well 2 is a circle having a radius b drawn in the P well 2 with the substrate contact A as the center. As shown in FIG. 3, since the primitive cells C1 and C2 are included in the cover region B of the substrate contact A, the distance reference with respect to the substrate contact A is satisfied.

  In other words, the distance (a) between the substrate contact cells 32 may be not more than twice the distance reference value (b) of the substrate contact 323. The intervals (a) between the substrate contact cells 32 need not be equal.

  Normally, the substrate contacts 323 for the metal wirings 11 and 12 to the N well 1 and the P well 2 need to be provided within a certain distance from the transistor region in order to prevent latch-up and ensure transistor performance.

  According to the first embodiment of the present invention, the substrate contact cell 32 is provided so as to satisfy a certain distance standard with respect to the neighboring primitive cell 32, and is arranged linearly in the direction perpendicular to the row. In the layout to apply the substrate bias for performance correction, the influence on the chip area can be minimized, and at the same time, improvement of the chip performance and reduction of the increase rate of the chip area can be realized at the same time. Can do.

  Further, according to the first embodiment of the present invention, since the substrate bias applying circuit 33 is arranged at the row A at the end of the functional block, it is possible to apply the substrate bias while minimizing the layout change of the primitive cells 31. it can.

  Further, according to the first embodiment of the present invention, since the substrate contact cells 32 are arranged in a grid pattern in the functional block, an increase in area due to the provision of the substrate contact cells 32 for applying a substrate bias can be reduced. .

  Next, a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment of the present invention, the example in which the substrate contact cells 32 are arranged in a grid pattern in the functional block has been described. In the second embodiment of the present invention, the substrate contact cells 32 are arranged in a staggered pattern in the functional block. An example will be described. In addition, the description about the content similar to Example 1 of this invention is abbreviate | omitted.

  FIG. 4 is a schematic diagram showing a functional block layout of the semiconductor integrated circuit according to the second embodiment of the present invention.

  The row A substrate contact cell 32 disposed at one end of the functional block is provided so as to satisfy a certain distance standard with respect to the N well 1 which is the well at the outermost portion of the functional block.

  The row B substrate contact cells 32 arranged adjacent to the row A are provided so that columns connected to the substrate wiring VBP21 and the substrate wiring VBN22 and columns not connected are alternately arranged.

  The row C substrate contact cells 32 disposed adjacent to the row B are provided so as to be connected to the substrate wiring VBP21 and the substrate wiring VBN22 in a column to which the row B substrate contact cells 32 are not connected.

  Rows D and F are configured in the same manner as row B, and rows E and G are configured in the same manner as row C. That is, in the rows B to G, the substrate contact cells 32 are arranged in a staggered manner.

  According to the second embodiment of the present invention, in addition to the same effects as those of the first embodiment, the substrate contact cells 32 are arranged in a staggered manner in the functional block. Therefore, the interval between the substrate contact cells 32 is set to the first embodiment of the present invention. As a result, it is possible to secure a space for arranging the large primitive cells 31 in each row.

Comparative example

  Next, a comparative example of the present invention will be described with reference to the drawings. In the comparative example of the present invention, an example of a technique for improving chip performance by threshold correction using a substrate bias will be described.

  FIG. 5 is a schematic diagram showing a layout of a semiconductor integrated circuit according to a comparative example of the present invention.

  In the comparative example of the present invention, the N well 1, the P well 2, the PMOS transistor 3, the NMOS transistor 4, the N + diffusion 5, the P + diffusion 6, the VDD metal wiring 11, the VSS metal wiring 12, and the substrate wiring VBP21 are provided in the cell frame 320. A substrate wiring VBN22 and a substrate contact 323 are provided.

  The substrate wiring VBP 21 and the substrate wiring VBN 22 for supplying the substrate potential are provided separately from the VDD metal wiring 11 and the VSS metal wiring 12. The substrate wiring VBP 21 gives a substrate potential to the N well 1 which is the substrate of the PMOS transistor 3 through the N + diffusion 5 and the substrate contact 21. The substrate wiring VBN 22 gives a substrate potential to the P well 2 which is the substrate of the NMOS transistor 4 through the P + diffusion 6 and the substrate contact 22.

  In the semiconductor integrated circuit of the comparative example of the present invention, the substrate wiring VBP21 and the substrate wiring VBN22 for supplying the substrate potential are provided separately from the VDD metal wiring 11 and the VSS metal wiring 12, so that the threshold voltage of the transistor is set. It can be adjusted by the substrate bias, and the chip performance can be improved. However, the semiconductor integrated circuit according to the comparative example of the present invention has a chip area of about 15 to 15 by separating the substrate wiring VBP21 and the substrate wiring VBN22 for supplying the substrate potential from the VDD metal wiring 11 and the VSS metal wiring 12. Increase by 20%.

  On the other hand, in the semiconductor integrated circuit according to the first embodiment of the present invention, as described above, the substrate contact cell 32 is provided so as to satisfy a certain distance criterion with respect to the neighboring primitive cell 32 and is orthogonal to the row. Since it is arranged linearly with respect to the direction (lattice in the functional block), the increase rate of the chip area can be reduced to about 1-2%.

  In the semiconductor integrated circuit according to the second embodiment of the present invention, as described above, the substrate contact cells 32 are provided so as to satisfy a certain distance standard with respect to the neighboring primitive cells 32, and are arranged in a staggered manner in the functional blocks. Therefore, the increase rate of the chip area can be reduced to about 0.5 to 1%.

It is the schematic which shows the layout of the functional block of the semiconductor integrated circuit of Example 1 of this invention. It is the schematic which shows the layout of the substrate contact cell 32 of Example 1 of this invention. It is the schematic which shows the distance reference | standard between the primitive cell 31 and the substrate contact cell 32 of Example 1 of this invention. It is the schematic which shows the layout of the functional block of the semiconductor integrated circuit of Example 2 of this invention. It is the schematic which shows the layout of the semiconductor integrated circuit of the comparative example of this invention.

Explanation of symbols

1 N well 2 P well 11 VDD metal wiring 12 VSS metal wiring 13, 14 Power supply trunk lines 21, 23 Substrate wiring VBP
22, 24 Substrate wiring VBN
31 Primitive cell 32 Substrate contact cell 33 Substrate bias application circuit

Claims (5)

A semiconductor integrated circuit device having a functional block,
The functional block includes a plurality of rows each provided with a plurality of primitive cells performing a predetermined operation, and a plurality of substrate contact cells provided in the row and supplying a substrate potential to each of the plurality of primitive cells. Have
The plurality of substrate contact cells are provided so as to satisfy a certain distance standard with respect to neighboring primitive cells to which the substrate potential is supplied, and are arranged linearly in a direction perpendicular to the row. A semiconductor integrated circuit device.   The semiconductor integrated circuit device according to claim 1, wherein the plurality of rows are arranged so as to straddle an N well and a P well, respectively.   The semiconductor integrated circuit device according to claim 2, wherein the plurality of substrate contact cells are arranged in a lattice pattern in each of the functional blocks.   The semiconductor integrated circuit device according to claim 2, wherein each of the plurality of substrate contact cells is arranged in a staggered manner in the functional block.   The semiconductor substrate according to claim 4, wherein a substrate contact cell of a row provided at one end of the functional block among the plurality of rows is provided so as to satisfy a certain distance criterion with respect to a well at an outermost portion of the functional block. Integrated circuit device.

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