JP2008258424A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of suppressing variation in transistor characteristics caused by the well proximity effect. <P>SOLUTION: Standard cell lines 11, 12, 13, ... in each of which standard cells 10 are laterally disposed, are longitudinally disposed side by side. The standard cell lines 11, 12, 13, ... are flipped on every other line, the standard cell lines 11, 12 share a P region, and the standard cell lines 12, 13 share N wells. Distances D1, D2, D3 from PMOS transistors 21, 22, 23 positioned at the ends of the standard cell lines 11, 12, 13 to the end of the N wells are spread so as to be equal to or wider than a width W1 of the N wells shared by the standard cell lines 12, 13. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit layout design technique, and more particularly, to a semiconductor integrated circuit device designed by arranging standard cells.

Conventionally, a layout of a semiconductor integrated circuit has been designed by arranging circuit parts called standard cells. For example, standard cells are arranged in the horizontal direction to form a standard cell column, and a plurality of standard cell columns are arranged in the vertical direction to form a circuit block. Each standard cell has a PMOS transistor and an NMOS transistor. In the case of the N well structure, the PMOS transistor is formed on the N well and the NMOS transistor is formed on the P substrate. In the case of the twin well structure, the PMOS transistor is formed on the N well and the NMOS transistor is formed on the P well.
JP 2003-133416 A

  With the progress of miniaturization, a phenomenon called a well proximity effect is likely to occur. The well proximity effect means that when impurities are implanted into the well, the impurities reflected and scattered by the resist are implanted into the channel region of the transistor, the channel impurity concentration exceeds the set value, and the threshold value of the transistor rises. It is a phenomenon.

  The amount of impurity implantation due to reflection and scattering varies depending on the distance between the transistor and the well, and tends to increase as the distance decreases. Here, the distance between the transistor and the well corresponds to the distance from the transistor to the end of the well. The miniaturization narrows the layout rule of the distance between the transistor and the well, so that the well proximity effect is likely to occur as a side effect.

  Normally, in the logic design stage of an electronic circuit, if the cells are the same, the characteristics are treated as the same. However, when the distance between the transistor and the well differs on the layout, the transistor characteristics on the product differ due to the influence of the well proximity effect. Therefore, a mismatch in circuit operation timing and the like occurs between the design and the product, which causes a product failure. Then, the competitiveness is lowered due to a decrease in yield, a decrease in circuit performance due to the addition of a design margin for guaranteeing a characteristic difference, and an increase in block area.

  On the other hand, in order to match the characteristics of the same cell, the distance between the transistor and the well should be kept constant, or the influence of the well proximity effect can be ignored so that the reflected and scattered impurities do not reach. It is necessary to keep.

  An example of the location where the characteristic variation due to the well proximity effect occurs is the end of the standard cell row. That is, in the vicinity of the center of the cell column, since the cells are arranged adjacent to each other, the distance between the transistor and the well becomes very large, whereas at the end of the cell column, the well included in one cell There are only width intervals. For this reason, a difference occurs in characteristics.

  Also, characteristics are likely to be different even in the uppermost row or the lowermost standard cell row. In a semiconductor integrated circuit designed using standard cells, the standard cell columns are usually flipped every other column, and the two standard cell columns arranged vertically share a well region. That is, the width of the well region is widened at a place other than the top row or the bottom row. For this reason, the well width is narrower in other places than in the uppermost row or the lowermost standard cell row. For this reason, a difference occurs in characteristics.

  Such a problem is a problem that has become apparent due to the progress of miniaturization. Conventionally, no measures have been taken in layout design, focusing on the distance between the transistor and the well in consideration of the influence of the well proximity effect. It wasn't.

  In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to a well proximity effect.

  The present invention provides a semiconductor integrated circuit device comprising a circuit block in which standard cell columns in which standard cells are arranged in the horizontal direction are arranged in a plurality of columns in the vertical direction, and each standard cell column extends in the horizontal direction. In addition, each of the standard cells includes a PMOS transistor formed in the N well and an NMOS transistor formed in the P region. In each of the standard cell columns, the positional relationship between the N well and the P region in the vertical direction is replaced every other column, and the standard cell columns of the first column and the second column share the P region, The second and third standard cell columns share an N well, and at least one of the standard cell columns has a small number. Also, the distance from the PMOS transistor located at either end to the end of the N well in the lateral direction closer to the PMOS transistor is shared by the second and third standard cell columns. It is equal to or larger than the shared N well width which is the width in the vertical direction of the well.

  According to the present invention, in at least one standard cell column, the distance from the PMOS transistor located at at least one end to the end of the N well in the lateral direction closer to the PMOS transistor is the second column and The width is equal to or larger than the shared N well width which is the width in the vertical direction of the N well shared by the standard cell row of the third row. For this reason, since the well proximity effect at the end of the standard cell column can be suppressed, the occurrence of a characteristic difference from the transistors at other locations other than the end of the standard cell column can be suppressed.

  Further, the present invention provides a semiconductor integrated circuit device comprising a standard cell block in which standard cell columns in which standard cells are arranged in the horizontal direction are arranged in a plurality of columns and arranged in the vertical direction. Each standard cell has a PMOS transistor formed in the N well and an NMOS transistor formed in the P region. The N well and the P region extend in the direction and are adjacent to each other in the vertical direction. In each of the standard cell columns, the positional relationship between the N well and the P region in the second direction is replaced every other column, and the standard cell columns of the first column and the second column are replaced with the P region. In addition, the standard cell columns of the second column and the third column share the N well. In addition, the common N well in which the vertical width of the N well in the standard cell column of the first column is the vertical width of the N well shared by the standard cell columns of the second column and the third column. Each standard cell is arranged such that the width of the N well in the vertical direction is not less than the shared N well width. Alternatively, a dummy cell column in which dummy cells having N wells are arranged in the horizontal direction is arranged on the outer side of the standard cell column of the first column so as to share the N well with the standard cell column of the first column. The vertical width of the N well shared by the standard cell column of the first column and the dummy cell column is the vertical direction of the N well shared by the standard cell column of the second column and the third column. The width is equal to or greater than the shared N well width.

  According to the present invention, the common N well in which the vertical width of the N well in the first standard cell column is the vertical width of the N well shared by the second and third standard cell columns. It is more than the width. For this reason, the well proximity effect of the standard cell column of the first column can be suppressed to be equivalent to the well proximity effect of the standard cell column of the second column and the third column. It is possible to suppress the occurrence of a characteristic difference from the transistors in the second and third standard cell columns.

  As described above, according to the present invention, variations in transistor characteristics due to the well proximity effect can be suppressed.

  Embodiments of the present invention will be described below with reference to the drawings.

  In the present specification, for convenience, the direction in which the standard cells are arranged in the standard cell row is referred to as a horizontal direction, and the direction in which the standard cell rows are arranged is referred to as a vertical direction.

(First embodiment)
FIG. 1 is a diagram showing a part of the layout of the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 1, reference numerals 11, 12, and 13 denote standard cell rows in which standard cells 10 (shown by rectangles) are arranged in the horizontal direction. The standard cell rows 11, 12, 13,... Are arranged in the vertical direction to form a circuit block. The standard cell row 11 is the top row. Each standard cell row 11, 12, and 13 includes an N well and a P region that extend in the horizontal direction and are arranged adjacent to each other in the vertical direction. Each standard cell 10 has a PMOS transistor formed in the N well and an NMOS transistor formed in the P region. However, the illustration is omitted except for the PMOS transistors 21, 22, and 23.

  The semiconductor integrated circuit device of FIG. 1 has an N well structure in which a PMOS transistor is formed on an N well and an NMOS transistor is formed on a P substrate, or a PMOS transistor is formed on the N well, and the NMOS transistor is a P well. It is a twin well structure formed on top. The P region in FIG. 1 is a P substrate in the case of an N well structure, and is a P well in the case of a twin well structure.

  In each of the standard cell rows 11, 12, and 13, the positional relationship between the N well and the P region in the vertical direction is replaced every other row. That is, the standard cell row 12 is flipped. When viewed from above, the standard cell columns 11 and 12 in the first column and the second column share the P region, and the standard cell columns 12 and 13 in the second column and the third column share the N well. ing.

  In FIG. 1, the PMOS transistors 21, 22, and 23 are located at the left end in the N wells of the standard cell columns 11, 12, and 13. D1 is a distance from the PMOS transistor 21 to the end closer to the N-well PMOS transistor 21 in the lateral direction, and D2 is an end closer to the N-well PMOS transistor 22 in the lateral direction from the PMOS transistor 22. , D3 is the distance from the PMOS transistor 23 to the end of the N-well closer to the PMOS transistor 23 in the lateral direction. W1 is a vertical width (shared N well width) of the N well shared by the second and third standard cell rows 12 and 13.

  For comparison with FIG. 1, FIG. 26 shows a layout of a conventional semiconductor integrated circuit device.

  Here, in the semiconductor integrated circuit device of FIG. 1, the distances D1, D2, D3 from the PMOS transistors 21, 22, 23 to the end of the N-well are expanded as compared with the conventional layout shown in FIG. The distances D1, D2, and D3 are equal to or larger than the width W1 in the vertical direction of the N well shared by the standard cell columns 12 and 13 of the second column and the third column.

  This can suppress the well proximity effect at the ends of the standard cell rows 11, 12, and 13. For the PMOS transistors 21, 22, and 23, the amount of impurities reflected and scattered by the resist and injected into the channel region of the transistors. Can be reduced sufficiently. Therefore, the difference between the characteristics of the PMOS transistors 21, 22, and 23 located at the end in the standard cell rows 11, 12, and 13 can be eliminated. As a result, the difference between the design stage and the actual circuit operation can be eliminated.

  In FIG. 1, the distance to the end of the N well is increased for the PMOS transistor located at the left end of each standard cell column, but the distance to the end of the N well is increased for the PMOS transistor located at the right end. Alternatively, the distance to the end of the N well may be increased for the PMOS transistors located at both the left and right ends.

  Further, in FIG. 1, the distance from the PMOS transistor located at the end to the end of the N well is increased in each standard cell column. However, if the distance is expanded in at least one standard cell column, the present invention will be described. include.

FIG. 2 is a diagram showing an example of a standard cell layout pattern for realizing the layout of FIG. The standard cell shown in FIG. 2 has a wider width in the horizontal direction than the conventional standard cell shown in FIG. In FIG. 2, A1 and A2 are distances from the PMOS transistor to the end of the N well in the horizontal direction. And
A1, A2 ≧ W1
A layout is formed so that

  By configuring each standard cell column using standard cells having a wide layout as shown in FIG. 2, a layout in which the distance from the PMOS transistor located at the end to the end of the N well is increased as shown in FIG. It can be easily realized. Note that adjacent standard cells are formed by overlapping N well regions in a range where transistors are not formed.

  Further, as shown in FIG. 3, the layout as shown in FIG. 1 is also realized by arranging dummy cells 31, 32, 33 having N wells outside the standard cells having PMOS transistors 21, 22, 23. can do. The lateral width of the N well in each dummy cell 31, 32, 33 is set sufficiently wide so that the distances D1, D2, D3 are equal to or greater than the width W1.

  In FIG. 3, one dummy cell is arranged in each standard cell row, but a plurality of dummy cells may be connected and arranged. That is, the distances D1, D2, and D3 need only be equal to or greater than the width W1, and the number of dummy cells to be arranged is not limited.

  4 to 8 show other configuration examples of the dummy cell. The dummy cell in FIG. 4 is a standard cell that does not share input / output with other standard cells, and 34 is a PMOS transistor. By using a dummy cell as shown in FIG. 4, this dummy cell can be utilized as a spare circuit when there is a circuit failure or when circuit improvement is required. Therefore, the development efficiency can be improved.

  The dummy cell in FIG. 5 includes an inter-power source capacitive element 35. By using the dummy cell as shown in FIG. 5, the capacity between the power supplies can be expanded, so that the power supply noise resistance of the circuit operation can be improved.

  The dummy cell in FIG. 6 includes a diode element 36. By using a dummy cell as shown in FIG. 6, it is possible to take measures against gate oxide film destruction due to charge accumulation in a fine process step, so-called antenna effect.

  The dummy cell in FIG. 7 includes a dummy gate 37 that is not connected to other elements. By using the dummy cell as shown in FIG. 7, it is possible to improve the processing uniformity of the transistor gate wiring located at the extreme end of the standard cell row and to improve the flatness in the gate wiring process step.

  The dummy cell in FIG. 8 includes a dummy wiring 38 that is not connected to other elements. By using a dummy cell as shown in FIG. 8, the area ratio of the wiring pattern can be adjusted, and the planarization in the wiring process can be improved.

(Second Embodiment)
FIG. 9 is a diagram showing a part of the layout of the semiconductor integrated circuit device according to the second embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 9 has substantially the same configuration as that in FIG. 1, and common constituent elements are denoted by the same reference numerals. W2 is the width in the vertical direction of the N well in the standard cell row 11 of the first row.

  Here, in the semiconductor integrated circuit device of FIG. 9, the width W2 in the vertical direction of the N well in the standard cell row 11 of the first row is expanded as compared with the conventional layout shown in FIG. The width W2 is equal to or greater than the width (shared N well width) W1 in the vertical direction of the N well shared by the standard cell rows 12 and 13 of the second row and the third row. As a result, the distance D4 from the PMOS transistor (for example, PMOS transistor 21) in the first standard cell column 11 to the far end of the N well in the vertical direction is set to the standard cell column 12 in the second column and the third column. , 13, the distances D5 and D6 from the PMOS transistor (for example, PMOS transistors 22 and 23) to the far end of the N well in the vertical direction are equal to or greater than.

  With such a configuration, the well proximity effect of the standard cell row 11 in the first row can be suppressed to be equal to the well proximity effect of the standard cell rows 12 and 13 in the second row and the third row.

  That is, when the distance D4 is equal to the distances D5 and D6, the amount of impurities reflected and scattered by the resist and injected into the channel region of the transistor is the same as the PMOS transistor and the second column in the standard cell column 11 in the first column. In addition, the PMOS transistors in the standard cell rows 12 and 13 in the third row are almost the same. For this reason, there is no difference in characteristics, and as a result, there is no difference between the design stage and the actual circuit operation.

  When the distance D4 is larger than the distances D5 and D6, the amount of impurities reflected and scattered by the resist and injected into the channel region of the transistor is the second in the PMOS transistor of the standard cell column 11 in the first column. This is less than the PMOS transistors in the standard cell columns 12 and 13 in the column and the third column. For this reason, a difference occurs in that the threshold value of the PMOS transistor in the standard cell row 11 of the first row is lowered. However, in this case, an effect that a high-speed circuit can be realized can be obtained by frequently using the cells arranged in the first column for a circuit that requires high-speed circuit operation.

  Here, the width of the N well in the uppermost standard cell column is expanded. Similarly, when the width of the N well in the lowermost standard cell column is expanded, the same as in the present embodiment. An effect is obtained.

FIG. 10 is a diagram showing an example of a standard cell layout pattern for realizing the layout of FIG. In the standard cell of FIG. 10, the vertical width of the N well is expanded as compared with the conventional standard cell as shown in FIG. In FIG. 10, B2 is the vertical width of the N well. And
B2 = W1
The layout is formed so that That is, the vertical width B2 of the N well is set equal to the shared N well width W1 in FIG.

  By configuring each standard cell column using standard cells having a layout in which the N wells are vertically expanded as shown in FIG. 10, the vertical width of the N well in the uppermost standard cell column as shown in FIG. It is possible to easily realize a layout with a widening. When the N well is shared by the two upper and lower standard cell columns, the N well regions in the range where the transistors are not formed are overlapped with each other.

  The layout as shown in FIG. 9 can also be realized by arranging dummy cell columns as shown in FIG. In FIG. 11, a dummy cell column 41 in which dummy cells 40 having N wells are arranged in the horizontal direction shares an N well with the standard cell column 11 of the first column further above, that is, outside, the standard cell column 11 of the first column. To be arranged.

  Further, in place of the dummy cell 40 of FIG. 11, a dummy cell having the configuration as shown in FIGS. 4 to 8 may be used. In this case, the same effect as described above can be obtained.

  In FIG. 11, the dummy cell 40 having both the N well and the P region is used. Instead, a dummy cell having only the N well without having the P region may be used. In this case, an increase in layout area due to the addition of dummy cell columns can be suppressed.

  12 to 15 show other configuration examples of dummy cells having only N wells. The dummy cell in FIG. 12 includes an inter-power source capacitive element 42. By using dummy cells as shown in FIG. 12, the capacity between power supplies can be expanded, so that the power supply noise resistance of the circuit operation can be improved.

  The dummy cell in FIG. 13 includes a diode element 43. By using a dummy cell as shown in FIG. 13, it is possible to take measures against gate oxide film destruction due to charge accumulation in a fine process step, that is, a so-called antenna effect.

  The dummy cell in FIG. 14 includes a dummy gate 44 that is not connected to other elements. By using the dummy cell as shown in FIG. 14, it is possible to improve the processing uniformity of the transistor gate wiring located at the extreme end of the standard cell row and to improve the flatness in the gate wiring process step.

  The dummy cell of FIG. 15 includes a dummy wiring 45 that is not connected to other elements. By using a dummy cell as shown in FIG. 15, the area ratio of the wiring pattern can be adjusted, and the planarization in the wiring process can be improved.

(Third embodiment)
The third embodiment of the present invention is a combination of the first and second embodiments described above. FIG. 16 is a diagram showing a part of the layout of the semiconductor integrated circuit device according to the third embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 16 has substantially the same configuration as that in FIGS. 1 and 9, and common constituent elements are denoted by the same reference numerals.

  In the semiconductor integrated circuit device of FIG. 16, as in the semiconductor integrated circuit device of FIG. 1, the distances D1, D2, and D3 from the PMOS transistors 21, 22, and 23 to the end of the N well are increased. The width of the N well shared by the standard cell rows 12 and 13 in the third row is equal to or larger than the width W1 in the vertical direction. Similarly to the semiconductor integrated circuit device of FIG. 9, the width W2 in the vertical direction of the N well in the first standard cell column 11 is increased, and the standard cell columns 12, 13 in the second column and the third column are expanded. The width W1 in the vertical direction of the N well shared by the above is greater than or equal to W1.

  According to the present embodiment, the operational effects obtained by the first embodiment and the operational effects obtained by the second embodiment are both obtained.

  Also, the layout as shown in FIG. 16 can be realized by arranging dummy cells as shown in FIG. In FIG. 17, dummy cells 51, 52, and 53 having N wells are arranged outside the standard cell having PMOS transistors 21, 22, and 23. Further, a dummy cell column 55 in which dummy cells 54 having N wells are arranged in the horizontal direction is arranged above the standard cell column 11 of the first column so as to share the N well.

(Fourth embodiment)
FIG. 18 is an image diagram of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. The semiconductor integrated circuit device of FIG. 18 includes first and second circuit blocks 101 and 102 (blocks P and P) in which a plurality of standard cell columns in which standard cells 100 are arranged in the horizontal direction are arranged in the vertical direction. Block Q). However, the height of the standard cell in the vertical direction is higher in the second circuit block 102 than in the first circuit block 101.

  FIGS. 19A and 19B are diagrams showing detailed layouts of the first and second circuit blocks 101 and 102 in FIG. 18, respectively. As shown in FIGS. 19A and 19B, both the first and second circuit blocks 101 and 102 have substantially the same configuration as the semiconductor integrated circuit device of FIG.

  In FIG. 19A, reference numerals 61, 62, and 63 denote standard cell rows in which standard cells (shown by rectangles) are arranged in the horizontal direction, and reference numerals 71, 72, and 73 denote N wells in the respective standard cell rows 61, 62, and 63. The PMOS transistor is arranged at the left end. E1 is the distance from the PMOS transistor 71 to the near end of the N well in the lateral direction, E2 is the distance from the PMOS transistor 72 to the near end of the N well in the lateral direction, and E3 is the PMOS transistor 73 to the near end of the N well in the lateral direction. X1 is the vertical width of the N well shared by the second and third standard cell columns 62 and 63, and X2 is the vertical width of the N well in the standard cell column 61 of the first column. .

  In FIG. 19B, 64, 65 and 66 are standard cell rows in which standard cells (shown by rectangles) are arranged in the horizontal direction, and 74, 75 and 76 are N wells of the respective standard cell rows 64, 65 and 66. PMOS transistor disposed at the left end in FIG. E4 is the distance from the PMOS transistor 74 to the near end of the N well in the lateral direction, E5 is the distance from the PMOS transistor 75 to the near end of the N well in the lateral direction, and E6 is the PMOS transistor. The distance from 76 to the near end of the N-well in the lateral direction. X3 is the vertical width of the N well shared by the second and third standard cell columns 65 and 66, and X4 is the vertical width of the N well in the standard cell column 64 of the first column. .

  Here, as shown in FIG. 19A, in the first circuit block 101, the width X2 in the vertical direction of the N well in the standard cell column 61 of the first column is the standard cell of the second column and the third column. The width of the N well shared by the columns 62 and 63 is not less than the width X1 in the vertical direction. Further, as shown in FIG. 19B, in the second circuit block 102, the width X4 in the vertical direction of the N well in the standard cell column 64 of the first column is equal to the standard cell columns of the second column and the third column. The width of the N well shared by 65 and 66 is not less than the width X3 in the vertical direction.

  With such a configuration, the same effects as those of the second embodiment can be obtained in the first and second circuit blocks 101 and 102. That is, in the first circuit block 101, the characteristics and differences of the PMOS transistors in the standard cell column 61 of the first column are different from those of the PMOS transistors in the standard cell columns 62 and 63 of the second column and the third column. Does not occur. Further, in the second circuit block 102, the characteristics and differences of the PMOS transistors in the standard cell column 64 of the first column are different from those of the PMOS transistors in the standard cell columns 65 and 66 of the second column and the third column. Does not occur.

  Further, as shown in FIG. 19A, in the first circuit block 101, distances E1, E1, and E3 from the PMOS transistors 71, 72, and 73 to the end of the N well are increased. The distances E1, E2, and E3 are equal to or larger than the width X1 in the vertical direction of the N well shared by the standard cell columns 62 and 63 of the second column and the third column. As a result, the same effects as those of the first embodiment can be obtained.

  Further, as shown in FIG. 19B, in the second circuit block 102, distances E4, E5, E6 from the PMOS transistors 74, 75, 76 to the end of the N well are expanded. However, in this case, the distances E4, E5, and E6 are equal to or greater than the width X1 in the vertical direction of the N well shared by the second and third standard cell columns 62 and 63 in the first circuit block 101. Just do it. As a result, the same effects as those of the first embodiment can be obtained.

  That is, in a semiconductor integrated circuit device having a plurality of circuit blocks having different cell heights, the width of the N-wells that expands in the horizontal direction with reference to the width of the shared N-well in the circuit block with the lower cell height. Should be set.

  In FIG. 19, the distance to the end of the N well is increased for the PMOS transistor located at the left end of each standard cell column, but the distance to the end of the N well is extended for the PMOS transistor located at the right end. Alternatively, the distance to the end of the N well may be increased for the PMOS transistors located at both the left and right ends.

  In FIG. 19, the distance from the PMOS transistor located at the end to the end of the N well is increased in each standard cell column. However, if the distance is increased in at least one standard cell column, the present invention can be applied. included.

(Fifth embodiment)
FIG. 20 is a diagram showing a part of the layout of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. In FIG. 20, reference numerals 81, 82, 83 denote standard cell rows in which standard cells 80 (shown by rectangles) are arranged in the horizontal direction. The standard cell rows 81, 82, 83,... Are arranged in the vertical direction to form a circuit block. The standard cell row 81 is the bottom row. Each standard cell row 81, 82, 83 includes an N well and a P well that extend in the horizontal direction and are adjacent to each other in the vertical direction. Each standard cell 80 includes a PMOS transistor formed in the N well and an NMOS transistor formed in the P well. However, the illustration is omitted except for the NMOS transistors 85, 86, and 87.

  The semiconductor integrated circuit device of FIG. 20 has a twin well structure in which a PMOS transistor is formed on an N well and an NMOS transistor is formed on a P well.

  In each standard cell column 81, 82, 83, the positional relationship between the N well and the P well in the vertical direction is replaced every other column. That is, the standard cell row 82 is flipped. When viewed from the bottom, the standard cell columns 81 and 82 in the first column and the second column share the N well, and the standard cell columns 82 and 83 in the second column and the third column share the P well. ing.

  Reference numeral 84 denotes an N-well pattern. W3 is the width in the vertical direction of the P well shared by the standard cell columns 82 and 83 in the second column and the third column, and W4 is the width in the vertical direction of the P well in the standard cell column 81 in the first column. .

  In FIG. 20, the vertical width W4 of the P well in the standard cell column 81 of the first column is equal to or larger than the vertical width W3 of the P well shared by the standard cell columns 82 and 83 of the second column and the third column. An N-well pattern 84 is arranged so that As a result, in the first standard cell column 81, the distance D7 from the NMOS transistor (for example, NMOS transistor 85) to the far end of the P well in the vertical direction is the second and third standard cell columns 82. 83, the distances D8 and D9 from the NMOS transistors (for example, NMOS transistors 86 and 87) to the far end of the P-well in the vertical direction are equal to or greater than. Therefore, the NMOS transistors in the standard cell column 81 of the first column do not differ or deteriorate in characteristics as compared with the PMOS transistors in the standard cell columns 82 and 83 of the second column and the third column.

  Further, the layout as shown in FIG. 20 can be realized by arranging dummy cell columns as shown in FIG. In FIG. 21, the dummy cell column 91 in which the dummy cells 90 are arranged in the horizontal direction shares a P well with the standard cell column 81 of the first column, further below or outside the standard cell column 81 of the first column. Has been placed. Here, the dummy cell 90 may be constituted by the P well and the minimum necessary N well pattern for setting the boundary between the N well and the P well. Thereby, the increase in the layout area by dummy cell arrangement | positioning can be suppressed.

  22 to 25 show other configuration examples of dummy cells. The dummy cell in FIG. 22 includes an inter-power source capacitive element 92. By using a dummy cell as shown in FIG. 22, the capacity between the power supplies can be expanded, so that the power supply noise resistance of the circuit operation can be improved.

  The dummy cell in FIG. 23 includes a diode element 93. By using a dummy cell as shown in FIG. 23, it is possible to take measures against gate oxide film destruction due to charge accumulation in a fine process step, so-called antenna effect.

  The dummy cell of FIG. 24 includes a dummy gate 94 that is not connected to other elements. By using a dummy cell as shown in FIG. 24, it is possible to improve the processing uniformity of the transistor gate wiring located at the extreme end of the standard cell row and to improve the flatness in the gate wiring process step.

  The dummy cell in FIG. 25 includes a dummy wiring 95 that is not connected to other elements. By using a dummy cell as shown in FIG. 25, the area ratio of the wiring pattern can be adjusted, and the planarization in the wiring process can be improved.

  Here, the width of the P well in the lowermost standard cell column is expanded. Similarly, when the width of the P well in the uppermost standard cell column is expanded, the same as in the present embodiment. An effect is obtained.

  In the present invention, variations in transistor characteristics due to the well proximity effect can be suppressed. Therefore, for example, the present invention is useful as a technique for improving yield, improving circuit performance, and reducing block area in a semiconductor integrated circuit device.

1 is a diagram showing a part of a layout of a semiconductor integrated circuit device according to a first embodiment of the present invention. It is a figure which shows an example of the standard cell for implement | achieving the layout of FIG. It is a figure which shows the example which implement | achieved the layout of FIG. 1 by arrangement | positioning of a dummy cell. It is another example of a structure of a dummy cell. It is another example of a structure of a dummy cell. It is another example of a structure of a dummy cell. It is another example of a structure of a dummy cell. It is another example of a structure of a dummy cell. It is a figure which shows a part of layout of the semiconductor integrated circuit device based on the 2nd Embodiment of this invention. It is a figure which shows an example of the standard cell for implement | achieving the layout of FIG. FIG. 10 is a diagram illustrating an example in which the layout of FIG. 9 is realized by arrangement of dummy cells. It is another example of a structure of the dummy cell which has only N well. It is another example of a structure of the dummy cell which has only N well. It is another example of a structure of the dummy cell which has only N well. It is another example of a structure of the dummy cell which has only N well. It is a figure which shows a part of layout of the semiconductor integrated circuit device based on the 3rd Embodiment of this invention. It is a figure which shows the example which implement | achieved the layout of FIG. 16 by arrangement | positioning of a dummy cell. It is an image figure of the semiconductor integrated circuit device which concerns on the 4th Embodiment of this invention. (A), (b) is a figure which shows the detailed layout of the circuit block in FIG. It is a figure which shows a part of layout of the semiconductor integrated circuit device based on the 5th Embodiment of this invention. It is a figure which shows the example which implement | achieved the layout of FIG. 20 by arrangement | positioning of a dummy cell. It is another example of a structure of a dummy cell. It is another example of a structure of a dummy cell. It is another example of a structure of a dummy cell. It is another example of a structure of a dummy cell. It is an example of the layout of the conventional semiconductor integrated circuit device. It is an example of the layout of the conventional standard cell.

Explanation of symbols

10 Standard cells 11, 12, 13 Standard cell columns 21, 22, 23 PMOS transistors 31, 32, 33 Dummy cell 35 Inter-power capacitive element 36 Diode element 37 Dummy gate 38 Dummy wiring 40 Dummy cell 41 Dummy cell string 42 Inter-power capacitive element 43 Diode Element 44 Dummy gate 45 Dummy wiring 51, 52, 53 Dummy cell 54 Dummy cell 55 Dummy cell column 61, 62, 63, 64, 65, 66 Standard cell column 71, 72, 73, 74, 75, 76 PMOS transistor 80 Standard cell 81, 82, 83 Standard cell row 84 N well pattern 85, 86, 87 NMOS transistor 90 Dummy cell 91 Dummy cell row 92 Inter-power source capacitance element 93 Diode element 94 Dummy gate 95 Dummy wiring 01 first circuit block 102 and the second circuit block

Claims (15)

A standard cell row in which standard cells are arranged in the horizontal direction includes a plurality of rows and circuit blocks arranged in the vertical direction.
Each standard cell row includes an N well and a P region extending in the horizontal direction and arranged adjacent to each other in the vertical direction,
Each standard cell includes a PMOS transistor formed in an N well and an NMOS transistor formed in a P region.
In each of the standard cell columns, the positional relationship between the N well and the P region in the vertical direction is exchanged every other column, and the standard cell columns of the first column and the second column share the P region, and 2 and 3 standard cell columns share N well,
In at least one of the standard cell columns,
The distance from the PMOS transistor located at at least one end to the end of the N well in the lateral direction closer to the PMOS transistor is shared by the second and third standard cell columns. A semiconductor integrated circuit device having a width equal to or larger than a common N-well width which is a width in a vertical direction of a well. In claim 1,
In the at least one standard cell row, a semiconductor in which the distance from the PMOS transistor in the lateral direction to the end of the N well is not less than the shared N well width is arranged as the standard cell. Integrated circuit device. In claim 1,
2. A semiconductor integrated circuit device according to claim 1, wherein a dummy cell having an N well is arranged outside the standard cell having the PMOS transistor in the at least one standard cell column. In claim 3,
The semiconductor integrated circuit device, wherein the dummy cell is a standard cell that does not share input / output with other standard cells. In claim 3,
The dummy cell includes a power source capacitance element, a diode element, a dummy gate not connected to another element, or a dummy wiring not connected to another element. In claim 1,
The semiconductor integrated circuit device according to claim 1, wherein a width in the vertical direction of the N well in the standard cell row of the first row is equal to or greater than the shared N well width. In claim 1,
A semiconductor integrated circuit device, wherein the P region is a P well. A standard cell column in which standard cells are arranged in a horizontal direction includes a plurality of columns and first and second circuit blocks arranged in a vertical direction,
Each standard cell row includes an N well and a P region extending in the horizontal direction and arranged adjacent to each other in the vertical direction,
Each standard cell includes a PMOS transistor formed in an N well and an NMOS transistor formed in a P region.
In each of the first and second circuit blocks, each of the standard cell columns has the positional relationship between the N well and the P region in the vertical direction replaced every other column. The cell columns share the P region, and the second and third standard cell columns share the N well,
The vertical height of the standard cell in the second circuit block is higher than the vertical height of the standard cell in the first circuit block,
In at least one of the standard cell columns in the second circuit block,
The distance from the PMOS transistor located at at least one end to the end of the N well in the lateral direction closer to the PMOS transistor is the standard of the second column and the third column in the first circuit block. A semiconductor integrated circuit device having a width equal to or greater than a width in a vertical direction of an N well shared by cell columns. A standard cell row in which standard cells are arranged in the horizontal direction includes a plurality of rows and circuit blocks arranged in the vertical direction.
Each standard cell row includes an N well and a P region extending in the horizontal direction and arranged adjacent to each other in the vertical direction,
Each standard cell includes a PMOS transistor formed in an N well and an NMOS transistor formed in a P region.
In each of the standard cell columns, the positional relationship between the N well and the P region in the vertical direction is exchanged every other column, and the standard cell columns of the first column and the second column share the P region, and 2 and 3 standard cell columns share N well,
The vertical width of the N well in the first standard cell column is equal to or greater than the shared N well width which is the vertical width of the N well shared by the second and third standard cell columns. Yes,
A semiconductor integrated circuit device, wherein each of the standard cells is arranged such that the width of the N well in the vertical direction is equal to or larger than the shared N well width. A standard cell row in which standard cells are arranged in the horizontal direction includes a plurality of rows and circuit blocks arranged in the vertical direction.
Each standard cell row includes an N well and a P region extending in the horizontal direction and arranged adjacent to each other in the vertical direction,
Each standard cell includes a PMOS transistor formed in an N well and an NMOS transistor formed in a P region.
In each of the standard cell columns, the positional relationship between the N well and the P region in the vertical direction is exchanged every other column, and the standard cell columns of the first column and the second column share the P region, and 2 and 3 standard cell columns share N well,
A dummy cell column in which dummy cells having N wells are arranged in the horizontal direction is arranged on the outer side of the standard cell column of the first column so as to share the N well with the standard cell column of the first column. ,
The vertical width of the N well shared by the standard cell column of the first column and the dummy cell column is the vertical width of the N well shared by the standard cell column of the second column and the third column. A semiconductor integrated circuit device having a width equal to or greater than a certain common N-well width. In claim 10,
The semiconductor integrated circuit device, wherein the dummy cell is a standard cell that does not share input / output with other standard cells. In claim 10,
The dummy cell includes a power source capacitance element, a diode element, a dummy gate not connected to another element, or a dummy wiring not connected to another element. In claim 10,
The semiconductor integrated circuit device, wherein the dummy cell does not have a P region. A standard cell row in which standard cells are arranged in the horizontal direction includes a plurality of rows and circuit blocks arranged in the vertical direction.
Each standard cell row includes an N well and a P well extending in the horizontal direction and arranged adjacent to each other in the vertical direction,
Each standard cell has a PMOS transistor formed in an N well and an NMOS transistor formed in a P well,
In each of the standard cell columns, the positional relationship between the N well and the P well in the vertical direction is exchanged every other column, and the standard cell columns of the first column and the second column share the N well, and 2 and 3 standard cell columns share a P-well,
The width in the vertical direction of the P well in the standard cell row of the first row is equal to or larger than the width in the vertical direction of the P well shared by the standard cell rows of the second row and the third row. Integrated circuit device. In claim 14,
A dummy cell column in which dummy cells are arranged in a horizontal direction is arranged on the outer side of the standard cell column of the first column so as to share a P well with the standard cell column of the first column. A semiconductor integrated circuit device.

Images