JP4334296B2 - 混成集積回路装置の製造方法 - Google Patents
混成集積回路装置の製造方法 Download PDFInfo
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- JP4334296B2 JP4334296B2 JP2003285160A JP2003285160A JP4334296B2 JP 4334296 B2 JP4334296 B2 JP 4334296B2 JP 2003285160 A JP2003285160 A JP 2003285160A JP 2003285160 A JP2003285160 A JP 2003285160A JP 4334296 B2 JP4334296 B2 JP 4334296B2
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- circuit board
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000000034 method Methods 0.000 title description 13
- 229920005989 resin Polymers 0.000 claims description 72
- 239000011347 resin Substances 0.000 claims description 72
- 238000007789 sealing Methods 0.000 claims description 67
- 239000004519 grease Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229920001187 thermosetting polymer Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000314 lubricant Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1を参照して、本発明に斯かる混成集積回路装置10の構成を説明する。図1(A)は混成集積回路装置10の斜視図であり、図1(B)は図1(A)のX−X’断面での断面図である。
図3および図4を参照して、混成集積回路装置10の製造方法を説明する。混成集積回路装置10の製造方法は、回路基板16の表面に導電パターン18および導電パターン18に固着された回路素子14から成る電気回路を構成する工程と、上金型22および下金型23から構成されるキャビティ内部に回路基板16を収納して、封止樹脂12をゲートから前記キャビティに封入することにより封止を行う工程とを有し、上金型22には、回路基板16の上方を移動する封止樹脂12の移動速度を規制する突起部22が設けられるものとなっている。この製造方法を以下にて説明する。
11 リード
12 封止樹脂
13 溝
14 回路素子
15 金属細線
16 回路基板
17 絶縁層
18 導電パターン
Claims (3)
- お互いが対向する長辺およびお互いが対向する短辺から成る矩形の表面と、前記表面と対向する裏面、および前記表面および前記裏面の周囲に位置する4側面から成る6面体から成り、前記表面の長辺に沿って配置されるリードパッド群の実装領域と、前記リードパッド群の実装領域に沿って隣接して設けられる未実装領域と、前記未実装領域に沿って隣接して配置される回路素子の実装領域とを有する回路基板を用意し、
前記実装領域に前記回路素子を実装すると共に、前記リードパッド群にリードを接続し、
上金型および下金型から構成されるキャビティ内部に前記回路基板を収納し、前記回路基板の前記側面の中点付近に位置するゲートから、前記リードパッド群の延在方向と直交する方向で、前記回路基板側面に向かって、樹脂を注入し、樹脂封止部を形成する混成集積回路装置の製造方法に於いて、
前記上金型には、前記未実装領域に相当する所の前記回路基板に向かって凸状の突起部が設けられることを特徴とする混成集積回路装置の製造方法。 - 前記回路基板側面に向かって注入された樹脂は、前記回路基板の前記表面と前記裏面に向かって分岐されながら注入される請求項1に記載の混成集積回路装置の製造方法。
- 前記リードパッド群に接続されたリードは、前記上金型と前記下金型で狭持される請求項1または請求項2に記載の混成集積回路装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2003285160A JP4334296B2 (ja) | 2003-08-01 | 2003-08-01 | 混成集積回路装置の製造方法 |
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JP2003285160A JP4334296B2 (ja) | 2003-08-01 | 2003-08-01 | 混成集積回路装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008291304A Division JP5108725B2 (ja) | 2008-11-13 | 2008-11-13 | 回路装置および回路装置モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005057004A JP2005057004A (ja) | 2005-03-03 |
JP4334296B2 true JP4334296B2 (ja) | 2009-09-30 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003285160A Expired - Fee Related JP4334296B2 (ja) | 2003-08-01 | 2003-08-01 | 混成集積回路装置の製造方法 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5098301B2 (ja) * | 2006-11-10 | 2012-12-12 | 三菱電機株式会社 | 電力用半導体装置 |
JP5108725B2 (ja) * | 2008-11-13 | 2012-12-26 | オンセミコンダクター・トレーディング・リミテッド | 回路装置および回路装置モジュール |
JP2014154732A (ja) * | 2013-02-08 | 2014-08-25 | Toshiba Corp | 電子機器および半導体電子部品 |
JP6358296B2 (ja) * | 2016-08-05 | 2018-07-18 | トヨタ自動車株式会社 | 半導体モジュールの製造方法 |
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2003
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