JP4311775B2 - Cartridge with semiconductor memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a cartridge containing a recording medium such as a silver halide photographic film or a magnetic recording tape, and more particularly to a cartridge with a semiconductor memory provided with a semiconductor memory in addition to a storage medium.
[0002]
[Prior art]
Conventionally, as this type of cartridge with a semiconductor memory, there is a cartridge in which a semiconductor memory module is attached to a video tape cartridge conforming to the digital video recorder (DVCR) standard.
[0003]
This cartridge with a semiconductor memory module can not only record normal images on a built-in magnetic tape but also store images and character information in the semiconductor memory module.
[0004]
[Problems to be solved by the invention]
By the way, a file management method used in a computer system is generally known as a method for storing and managing electronic information in a semiconductor memory.
In this management method, file data such as image information is stored in the semiconductor memory, and at the same time, management data having specific information such as a specific flag indicating that the file data is stored in the semiconductor memory and a creation date is stored. Let For this reason, even if the file data is not accessed in the memory, the management data can be searched for the unique information related to the file data only by the memory access.
[0005]
Further, when the stored file data is no longer needed, it is assumed that the file data has been erased by rewriting a specific flag in the management data to erase data. That is, the file data is not actually erased, but the file data is regarded as erased only by setting the specific flag to “erase”.
[0006]
However, in this file management method, the file data set to “erase” is actually left in the semiconductor memory, so there is a possibility that it will be read by some method.
[0007]
Therefore, when the conventional file management method is applied to a cartridge with a semiconductor memory module, the same possibility as described above is latent. For this reason, in a cartridge with a semiconductor memory module, a new technology that can reliably prevent leakage of information stored in the semiconductor memory module has been desired.
[0008]
[Means for Solving the Problems]
The present invention has been made to overcome the above-described problems of the prior art, and is a cartridge with a semiconductor memory in which a semiconductor memory is attached to a cartridge containing a recording medium. A file data storage area for storing one or more file data, and a management data storage area for storing one or more management data having unique information of each of the one or more file data, In the predetermined bits in each management data, storage information indicating that each file data is stored in the file data storage area and deletion information indicating that deletion of each file data is designated are exclusive. written, further, a flag detecting circuit constituted by a sense amplifier that is directly connected to the memory cell storing the predetermined bit, the file data When stored in the file data storage area, it examined based on the detection signal from the flag detecting circuit one is what is stored in the storage information or erase information on said predetermined bits, stored in the predetermined bit storage When it is detected that the information has been rewritten to the erasure information, a data erasing unit is provided for erasing the file data designated for erasure.
[0009]
According to such a configuration, when the data erasing means stores the file data in the file data storage area, the detection signal from the flag detection circuit indicates whether stored information or erasure information is stored in the predetermined bit. Find out based on . As a result, when it is detected that the stored information stored in the predetermined bit is rewritten to the erasure information, the file data corresponding to the rewritten management data is erased. Therefore, unlike the case where the erasure of the corresponding file data is apparently performed based on the erasure information in the management data, the file data is actually erased by the data erasure means.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a cartridge with a semiconductor memory according to the present invention will be described below with reference to the drawings. A cartridge with a semiconductor memory in which a semiconductor memory is attached to a new standard film cartridge called an APS (advanced photo system) (hereinafter referred to as an APS film cartridge with a semiconductor memory) will be described.
[0011]
FIG. 1 is a perspective view showing an external structure of an APS film cartridge with a semiconductor memory, and FIG. 2 is a block diagram showing a circuit configuration of the semiconductor memory.
[0012]
1, this APS film cartridge 1 with a semiconductor memory has a spool 3 equipped with a roll-shaped silver salt photographic film 2 rotatably housed in a bottomed cylindrical cartridge body 4 with good light shielding properties. ing. At the side end of the cartridge body 4, an opening 5 for taking in and out the silver halide photographic film 2 and a swingable light-shielding lid 6 for opening and closing the opening 5 are provided.
[0013]
The respective end portions of the spool 3 and the light shielding cover 6 are exposed from the end surface of the cartridge main body 4, and notched key grooves 3a and 6a are formed at the respective end portions. When the APS film cartridge 1 with semiconductor memory is mounted in the camera system, the film transport mechanism in the camera system engages with the key grooves 3a and 6a, and the rotation of the spool 3 and the light shielding lid 6 are driven by the film transport mechanism. Opening and closing is performed.
[0014]
When the shielding lid 6 is opened by the above film transport mechanism and the spool 3 is further rotated in a predetermined direction, the silver halide photographic film 2 is sent one frame at a time through the opening 5 and photography can be performed. When the spool 3 is rotated in the direction opposite to the above, the silver salt photographic film 2 is wound up in the cartridge body 4, and the silver halide photographic film 2 is closed when the opening 5 is closed by the light shielding lid 6 after the winding is completed. Can be prevented from being exposed to external light.
[0015]
As described above, the APS film cartridge 1 with a semiconductor memory includes the cartridge body 4 having good light shielding properties, the spool 3 for feeding and winding the silver halide photographic film 2, and the light shielding lid 6 for opening and closing the opening 5. Therefore, the silver halide photographic film 2 in which the unphotographed frames remain can be taken up in the cartridge body 4 and attached to the camera system again at a later date to shoot using the unphotographed frames. It has the characteristics.
[0016]
A modular chip-shaped semiconductor memory 7 is fixed to the end surface of the cartridge body 4. At one end of the semiconductor memory 7, at least connection terminals such as a power input terminal, a clock signal input terminal, and a data input / output terminal are exposed. Electrical connection is made between the circuit shown in FIG. 2 and an electronic device such as a camera system via these connection terminals.
[0017]
The semiconductor memory 7 of the present embodiment is composed of a serial semiconductor memory that performs input / output of data for each bit. And a non-volatile semiconductor memory such as a flash memory, and a solid element manufacturing process such as a FRAM (Ferro Electric Random Access Memory).
[0018]
In FIG. 2, a semiconductor memory 7 includes a memory matrix unit 8 for storing data, a data transfer circuit 9 for accessing the memory matrix unit 8 (data writing and data reading), an address counter 10 and a control circuit. 11 and a data erasing circuit 12 are provided. The data erasing circuit 12 includes a determination circuit 13, an erasing address designating circuit 14, a clear data generating circuit 15, and a plurality of flag detecting circuits 16a to 16n.
[0019]
In the memory matrix portion 8, a large number of memory cells are arranged in units of 8 bits (byte units). A memory bus DB composed of eight data lines is connected to each array of the same bits of these memory cells, and an address bus AB is connected to each array in byte units.
[0020]
The memory matrix unit 8 further includes a file data storage area for storing a plurality of file data (# 0) to (#n) such as image data and audio data, and file data (# 0) to (#n). ) Is assigned a management data storage area for storing management data related to the unique information. More specifically, as shown in the memory map of FIG. 3A, addresses $ 00 to $ 0n designated by the address bus AB are management data storage areas, and addresses $ 1000 to $ 1n00 are file data storage areas. Assigned.
[0021]
In the present embodiment, each file data (# 0) to (#n) is configured in units of a plurality of bytes having a fixed length, and each management data is configured in units of 1 byte. Further, as shown in FIG. 3B, each piece of management data is encoded in a predetermined format, and a plurality of management items are commonly assigned in bit units. Specifically, as shown in (1) to (8) below, a management item is assigned for each bit, and a bit flag of “1” or “0” is set (written) to each.
[0022]
{Circle around (1)} Bit 0... Indicates whether processing is in JPEG or TIFF image format.
{Circle around (2)} Bit 1 indicates whether or not a date is attached to the file data.
{Circle around (3)} Bit 2... Indicates whether the image is obtained by panoramic shooting with a wide angle of view.
{Circle around (4)} Bit 3... Indicates whether or not the picture was taken using a strobe.
(5) Bit 4 ... Unused bit.
(6) Bit 5: Unused bit.
(7) Bit 6: Unused bit.
(8) Bit 7: Storage information indicating that the file data has been recorded and erase information indicating that the deletion of the file data has been instructed are written.
[0023]
In FIG. 2 again, the data transfer circuit 9 is composed of an 8-bit bidirectional shift register, and a 1-bit bidirectional serial data bus SB connected to the data input / output terminal is connected to the memory bus DB. Has been. Then, it operates according to the clock signal CK externally input from the clock signal input terminal and the control signal Csp from the control circuit 11.
[0024]
That is, when the data transfer circuit 9 receives an instruction to write data by the control signal Csp, the data transfer circuit 9 inputs the write data Din transferred by the bit string for each bit from the bidirectional serial data bus SB, and then the data in units of 8 bits. Are converted into parallel and serial data and transferred to the memory bus DB in parallel. As a result, the data Din input as a bit string is converted into 8-bit data and stored at the address specified by the address counter 10.
[0025]
On the other hand, when receiving an instruction to read data by the control signal Csp, the data transfer circuit 9 inputs the data in units of bytes transferred from the memory matrix unit 8 via the memory bus DB in parallel, and then outputs the data for each bit. The data Dout is parallel-serial converted and sent to the bidirectional serial data bus SB. That is, data read from the address specified by the address counter 10 is converted into a bit string and output to the bidirectional serial data bus SB.
[0026]
The address decoder 10 includes a shift counter connected to the address bus AB, and counts the address clock signal CKad according to the memory access control signal Cas supplied from the control circuit 11. Then, by outputting the count value to the address bus AB, the memory matrix unit 8 is addressed in units of bytes.
[0027]
The address clock signal CKad is supplied from the control circuit 11 during normal data writing and data reading (hereinafter referred to as “normal memory access mode”), and in the “data erasing mode” described later, the erasing address. Supplied from the designation circuit 14.
[0028]
The control circuit 11 is composed of a decoder circuit, ROM-structured firmware, and the like, and by determining the address data ADR and command data COM in the input data Din externally input via the bidirectional serial bus SB, The control signals Csp and Cas and the address clock signal CKad are generated. Further, the timing adjustment signal Ccn is transmitted / received between the control circuit 11 and the determination circuit 13 so that the processes in the “normal memory access mode” and the “data erase mode” do not compete.
[0029]
Each of the flag detection circuits 16a to 16n is composed of a sense amplifier or the like, and is connected to the 7th bit memory cell of each address $ 00 to $ 0n of the management data storage area as shown in FIG. . The flag detection circuits 16a to 16n do not detect the data accessed by the memory by the address line, but read the data nondestructively by the above-described sense amplifier directly connected to the memory cell of the 7th bit and read it. The detected signals Fa to Fn are sent to the determination circuit 13.
[0030]
The determination circuit 13 is configured by a decoder circuit, ROM-structured firmware, or the like, and determines whether or not the “data erasure mode” should be set based on the detection signals Fa to Fn from the flag detection circuits 16a to 16n. . That is, when any one of the detection signals Fa to Fn changes from logic “1” to “0”, the flag of the seventh bit of the management data corresponding to the detection signal is rewritten from “1” to “0”. It is determined that
Based on the determination result, “data erasure mode” is set to erase the management data in which the 7th bit flag is rewritten from “1” to “0” and the file data managed by the management data. Is done.
[0031]
The erase address designating circuit 14 operates in accordance with the instruction of the control signal Cad supplied from the determination circuit 13 in the “data erase mode”, and the address of the management data in which the flag of the seventh bit is rewritten to “0”. The address clock signal CKad for designating the address of the file data managed by the management data is generated. The address clock signal CKad is synchronized with the clock signal CK.
[0032]
The clear data generation circuit 15 performs management data in which the flag of the seventh bit is rewritten to “0” in accordance with the instruction of the control signal Ccd supplied from the determination circuit 13 in the “data erasing mode”, and the management data The bit string data Dcd for erasing the file data managed by the above is generated and sent to the data transfer circuit 9 via the bidirectional serial bus SB.
[0033]
When the determination circuit 13 requests the “data erasing mode” from the control circuit 11 by the timing adjustment signal Ccn, the control circuit 11 supplies the control signal Csp and the memory access control signal Cas to the data transfer circuit 9 and the address counter 10. To instruct data writing. As a result, the erase address designating circuit 14 sets a memory address based on the address clock signal CKad, and the data transfer circuit 9 transfers the bit string data Dcd to the memory matrix unit 8 via the memory bus DB. The file data and the management data at the memory address specified in 13 are overwritten with data Dcd and deleted.
[0034]
In the present embodiment, the data Dcd is all composed of “0” or “1”. However, the present invention is not limited to the data Dcd, and may be meaningless data.
[0035]
Next, an operation example of the semiconductor memory having such a configuration will be described with reference to FIGS. FIG. 4 is an explanatory diagram showing an operation when writing file data and management data in the “normal memory access mode”, and FIG. 5 erases the file data and management data in the “data deletion mode”. It is explanatory drawing which shows the operation | movement at the time.
[0036]
When the APS film cartridge with semiconductor memory 1 is shipped, no data is written in the file data management area and the management data storage area. In other words, as shown in FIG. 4A, the state is the same as when meaningless data (NULL) is written.
[0037]
When the user takes a picture using the APS film cartridge 1 with a semiconductor memory and then requests the developer to develop the silver salt film 2, the developed silver salt film 2 according to the user's request. The image of each frame can be digitized and stored in a file data storage area. Although detailed description is omitted, data can be written into the file data storage area also by a dedicated electronic device that digitizes the developed image of each frame and writes it in the semiconductor memory 7. .
[0038]
First, as shown in FIG. 4B, after the first file data, that is, the first image data (# 0) is stored at the memory address $ 1000, the image data (#) is stored at the memory address $ 00. Management data having unique information 0) is stored in the format shown in FIG. The writing process of the image data (# 0) and the management data is performed in the “normal memory access mode”.
[0039]
Next, as shown in FIG. 4C, after the second image data (# 1) is stored at the memory address $ 1100, the unique information of the image data (# 1) is stored at the memory address $ 01. Is stored in the same format as described above. The writing process of the image data (# 1) and the management data is also performed in the “normal memory access mode”.
[0040]
The same writing process is performed until all the image data is written.
[0041]
Next, by using the above-described dedicated electronic device or by requesting a developing laboratory, it is possible to delete an image file that has become unnecessary. FIG. 5 shows an erasing operation of the first image data (# 0) as an example. First, as shown in FIG. 5A, the bit flag “0” is written to the seventh bit of the management data stored at the address $ 00 of the management data storage area. The bit flag “0” is also written in the “normal memory access mode”. As a result, the image data (# 0) is apparently erased.
[0042]
Thus, when the bit flag of the seventh bit becomes “0”, the flag detection circuit 16a and the determination circuit 13 in the semiconductor memory 7 automatically detect this, and the “data erasing mode” is set. Then, as shown in FIG. 5B, the image data (# 0) is completely erased by being overwritten with meaningless data NULL.
[0043]
Next, as shown in FIG. 5C, the management data is completely erased by overwriting all the bits of the management data at the address $ 00 with the meaningless data NULL.
[0044]
Also, when deleting a plurality of image data, the same “data erasing mode” process is performed. That is, when the bit flag of the seventh bit of the management data related to the plurality of image data is rewritten to “0”, the flag detection circuits 16a to 16n and the determination circuit 13 automatically set these bit flags “ A change from “1” to “0” is detected, and the corresponding image data and management data are completely erased by the processing of “data erase mode”.
[0045]
As described above, according to this embodiment, when apparent file data is set to be erased by setting (writing) the bit flag “0” to the seventh bit of the management data, the semiconductor memory 7 itself Since this is automatically detected and the corresponding file data is overwritten and erased with meaningless data, information leakage as in the prior art can be reliably prevented.
[0046]
In this embodiment, the serial semiconductor memory 7 that accesses data in units of 8 bits has been described. However, the present invention is not limited to this. The memory cells of the memory matrix unit 8 may be a serial semiconductor memory that performs memory access in word units (16-bit units) or other multi-bit units.
[0047]
In this embodiment, an item related to erasure of file data is assigned to the seventh bit of management data, but the present invention is not limited to this, and other bits of management data or other bits An item related to erasure of file data may be assigned to a plurality of bits.
[0048]
In the present embodiment, the serial semiconductor memory 7 has been described. However, the present invention is not limited to this, and a semiconductor memory that inputs and outputs write data and read data in parallel may be applied.
[0049]
Further, the APS film cartridge 1 with semiconductor memory has been described. However, this is merely an embodiment, and the present invention includes other cartridges. As an example, the present invention can also be applied to a DVCR video tape cartridge used in a digital video recorder (DVCR) for digitally photographing a subject. Further, the storage medium stored in the cartridge is not limited to a silver salt photographic film or a magnetic recording medium, but may be other recording media.
[0050]
【The invention's effect】
As described above, according to the present invention, when the file data is stored in the file data storage area, the flag detection circuit detects whether stored information or erase information is stored in a predetermined bit. Since the semiconductor memory has data erasing means for erasing the file data designated for erasure when it is detected that the stored information stored in the predetermined bit is rewritten to the erasure information , the management data is provided. Unlike the prior art in which erasure of the file data corresponding to the erasure information is apparently performed, the file data is surely erased. Therefore, it is possible to provide a new technique that can reliably prevent leakage of information stored in the semiconductor memory.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an external structure of an APS film cartridge with a semiconductor memory according to the present embodiment.
FIG. 2 is a block diagram showing a circuit configuration of a semiconductor memory according to the present embodiment.
FIG. 3 is an explanatory diagram showing a memory map of a semiconductor memory, a configuration of management data, and a partial configuration of a data erasing circuit;
FIG. 4 is an explanatory diagram for explaining a data write operation to a file data storage area and a management data storage area of a semiconductor memory.
FIG. 5 is an explanatory diagram for explaining an erasing operation between image data in a file data storage area and management data in a management data storage area;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... APS film cartridge with semiconductor memory 7 ... Semiconductor memory 8 ... Memory matrix part 9 ... Data transfer circuit 10 ... Address counter 11 ... Control circuit 12 ... Data erasure circuit 13 ... Determination circuit 14 ... Erase address designation circuit 15 ... Clear data generation Circuits 16a to 16n: Flag detection circuit

Claims (4)

A cartridge with a semiconductor memory in which a semiconductor memory is attached to a cartridge containing a recording medium,
The semiconductor memory includes a file data storage area for storing one or more file data, and a management data storage area for storing one or more management data having unique information of each of the one or more file data Have
The predetermined bit in each management data is exclusive of storage information indicating that each file data has been stored in the file data storage area and deletion information indicating that the deletion of each file data is designated. Written,
A flag detection circuit including a sense amplifier directly connected to the memory cell storing the predetermined bit;
When the file data is stored in the file data storage area, whether the stored information or the erasure information is stored in the predetermined bit based on a detection signal from the flag detection circuit , wherein when the storage information stored in a predetermined bit is detected to be rewritten on the erased information, cartridge with a semiconductor memory which is characterized in that a data erasing means for erasing the file data specified in erased. The cartridge with semiconductor memory according to claim 1, wherein the semiconductor memory is a serial semiconductor memory. 3. The cartridge with a semiconductor memory according to claim 1, wherein the cartridge with a semiconductor memory is a cartridge compliant with the APS standard. 3. The cartridge with semiconductor memory according to claim 1, wherein the cartridge with semiconductor memory is a video tape cartridge for a digital video recorder.

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