JP4298009B2 - Ｓｏｉ基板の作製方法及び半導体装置の作製方法 - Google Patents

Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Download PDF

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Publication number
JP4298009B2
JP4298009B2 JP20599898A JP20599898A JP4298009B2 JP 4298009 B2 JP4298009 B2 JP 4298009B2 JP 20599898 A JP20599898 A JP 20599898A JP 20599898 A JP20599898 A JP 20599898A JP 4298009 B2 JP4298009 B2 JP 4298009B2
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layer
single crystal
substrate
silicon
silicon layer
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JP20599898A
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Japanese (ja)
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JP2000040812A5 (fr
JP2000040812A (ja
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舜平 山崎
健司 福永
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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JP20599898A 1998-07-22 1998-07-22 Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Expired - Fee Related JP4298009B2 (ja)

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JP20599898A JP4298009B2 (ja) 1998-07-22 1998-07-22 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20599898A JP4298009B2 (ja) 1998-07-22 1998-07-22 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

Publications (3)

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JP2000040812A JP2000040812A (ja) 2000-02-08
JP2000040812A5 JP2000040812A5 (fr) 2005-10-20
JP4298009B2 true JP4298009B2 (ja) 2009-07-15

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JP20599898A Expired - Fee Related JP4298009B2 (ja) 1998-07-22 1998-07-22 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2827423B1 (fr) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
TW564471B (en) 2001-07-16 2003-12-01 Semiconductor Energy Lab Semiconductor device and peeling off method and method of manufacturing semiconductor device
US7351300B2 (en) 2001-08-22 2008-04-01 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
KR100944886B1 (ko) * 2001-10-30 2010-03-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 제조 방법
JP5271541B2 (ja) * 2006-01-16 2013-08-21 パナソニック株式会社 半導体小片の製造方法ならびに電界効果トランジスタおよびその製造方法
FR2914493B1 (fr) * 2007-03-28 2009-08-07 Soitec Silicon On Insulator Substrat demontable.

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JP2000040812A (ja) 2000-02-08

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