JP4290554B2 - 改良された制御回路を備える出力ドライバ - Google Patents
改良された制御回路を備える出力ドライバ Download PDFInfo
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- JP4290554B2 JP4290554B2 JP2003548404A JP2003548404A JP4290554B2 JP 4290554 B2 JP4290554 B2 JP 4290554B2 JP 2003548404 A JP2003548404 A JP 2003548404A JP 2003548404 A JP2003548404 A JP 2003548404A JP 4290554 B2 JP4290554 B2 JP 4290554B2
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- transistor
- supply terminal
- current
- output
- supply
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- 230000000087 stabilizing effect Effects 0.000 claims description 5
- 230000004044 response Effects 0.000 claims description 3
- 230000006641 stabilisation Effects 0.000 claims 2
- 238000011105 stabilization Methods 0.000 claims 2
- 239000003990 capacitor Substances 0.000 description 8
- 238000009499 grossing Methods 0.000 description 7
- 102100031456 Centriolin Human genes 0.000 description 5
- 101000941711 Homo sapiens Centriolin Proteins 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
Claims (5)
- 制御信号を生成するための出力ドライバを備え、この出力ドライバは、第1の供給端子と、第2の供給端子と、入力信号を受信するための信号入力端子と、前記制御信号を供給するための信号出力端子と、制御電極を有すると共に前記第1の供給端子と前記信号出力端子との間に連結される主電流パスを有する出力トランジスタと、前記入力信号に応答して制御信号を前記出力トランジスタの前記制御電極に供給する制御回路とを含み、且つ前記制御回路は、出力が前記出力トランジスタの前記制御電極に連結されると共に第1の供給接続点が前記第1の供給端子に連結されるバッファを備える、電子回路であって、前記出力ドライバは、前記バッファの第2の供給接続点と前記第2の供給端子との間に連結された主電流パスを有すると共に、基準電位を受取るための制御電極を有する電流受信トランジスタを更に含み、
前記バッファの前記第2の供給接続点に生じた電流ピークは、前記バッファの供給電圧に認容し難いピークを生じさせないように、前記電流受信トランジスタを介して、前記第2の供給端子に向かって放電されることを特徴とする、電子回路。 - 前記出力ドライバは、前記第1の供給端子の電位に対して前記基準電位を安定化するための電圧安定化手段を更に含むことを特徴とする、請求項1に記載の電子回路。
- 前記電圧安定化手段は、前記第1の供給端子と前記電流受信トランジスタの前記制御電極との間に連結されるツェナーダイオードと、前記ツェナーダイオードを通って流れる電流を生成するための電流生成手段と、を備えることを特徴とする、請求項1に記載の電子回路。
- 前記出力ドライバは、入力が前記電流受信トランジスタの前記主電流パスと前記第2の供給端子との間に連結されると共に出力が前記電流受信トランジスタの前記制御電極に連結されるフィードバック手段を更に含むことを特徴とする、請求項1から3のいずれか一項に記載の電子回路。
- 前記出力ドライバは、前記ツェナーダイオードと直列に連結される抵抗器を更に含むことを特徴とする、請求項3または4に記載の電子回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01204584 | 2001-11-27 | ||
PCT/IB2002/005048 WO2003047105A1 (en) | 2001-11-27 | 2002-11-25 | Output driver comprising an improved control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005510934A JP2005510934A (ja) | 2005-04-21 |
JP4290554B2 true JP4290554B2 (ja) | 2009-07-08 |
Family
ID=8181320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003548404A Expired - Fee Related JP4290554B2 (ja) | 2001-11-27 | 2002-11-25 | 改良された制御回路を備える出力ドライバ |
Country Status (6)
Country | Link |
---|---|
US (1) | US6956403B2 (ja) |
EP (1) | EP1451932B1 (ja) |
JP (1) | JP4290554B2 (ja) |
KR (1) | KR20040062646A (ja) |
AU (1) | AU2002353265A1 (ja) |
WO (1) | WO2003047105A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6781422B1 (en) * | 2003-09-17 | 2004-08-24 | System General Corp. | Capacitive high-side switch driver for a power converter |
US7088151B1 (en) * | 2004-04-21 | 2006-08-08 | Intersil Americas Inc. | High voltage gate driver using a low voltage multi-level current pulse translator |
US7812639B2 (en) * | 2007-12-31 | 2010-10-12 | Sandisk Corporation | Extending drive capability in integrated circuits utilizing programmable-voltage output circuits |
JP2012228139A (ja) * | 2011-04-22 | 2012-11-15 | Toshiba Corp | レベルシフト回路、制御回路及びdc−dcコンバータ |
KR101287659B1 (ko) * | 2011-09-30 | 2013-07-24 | 삼성전기주식회사 | 출력 구동 장치 |
FR2988931B1 (fr) * | 2012-03-30 | 2015-10-16 | Schneider Toshiba Inverter | Dispositif de commande employe dans un systeme d'alimentation electrique a decoupage |
TWI611185B (zh) * | 2015-12-19 | 2018-01-11 | National Taipei University Of Technology | 檢測裝置 |
US9973180B2 (en) | 2015-12-30 | 2018-05-15 | Industrial Technology Research Institute | Output stage circuit |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5021684A (en) * | 1989-11-09 | 1991-06-04 | Intel Corporation | Process, supply, temperature compensating CMOS output buffer |
US5218239A (en) * | 1991-10-03 | 1993-06-08 | National Semiconductor Corporation | Selectable edge rate cmos output buffer circuit |
US5568081A (en) * | 1995-06-07 | 1996-10-22 | Cypress Semiconductor, Corporation | Variable slew control for output buffers |
US5917758A (en) * | 1996-11-04 | 1999-06-29 | Micron Technology, Inc. | Adjustable output driver circuit |
JPH1117517A (ja) * | 1997-06-23 | 1999-01-22 | Seiko Epson Corp | Cmos−ic出力回路 |
JP3036482B2 (ja) * | 1997-09-17 | 2000-04-24 | 日本電気株式会社 | 出力バッファ回路 |
JPH11225062A (ja) * | 1998-02-05 | 1999-08-17 | Hitachi Ltd | 出力回路 |
US6087853A (en) * | 1998-06-22 | 2000-07-11 | Lucent Technologies, Inc. | Controlled output impedance buffer using CMOS technology |
US6535020B1 (en) * | 2001-12-18 | 2003-03-18 | Sun Microsystems, Inc. | Output buffer with compensated slew rate and delay control |
US6759872B2 (en) * | 2002-03-14 | 2004-07-06 | Koninklijke Philips Electronics N.V. | I/O circuit with mixed supply voltage capability |
-
2002
- 2002-11-25 AU AU2002353265A patent/AU2002353265A1/en not_active Abandoned
- 2002-11-25 US US10/496,481 patent/US6956403B2/en not_active Expired - Lifetime
- 2002-11-25 KR KR10-2004-7007940A patent/KR20040062646A/ko not_active Application Discontinuation
- 2002-11-25 WO PCT/IB2002/005048 patent/WO2003047105A1/en active IP Right Grant
- 2002-11-25 EP EP02788286A patent/EP1451932B1/en not_active Expired - Lifetime
- 2002-11-25 JP JP2003548404A patent/JP4290554B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005510934A (ja) | 2005-04-21 |
US20050040866A1 (en) | 2005-02-24 |
EP1451932A1 (en) | 2004-09-01 |
AU2002353265A1 (en) | 2003-06-10 |
WO2003047105A1 (en) | 2003-06-05 |
KR20040062646A (ko) | 2004-07-07 |
EP1451932B1 (en) | 2006-08-23 |
US6956403B2 (en) | 2005-10-18 |
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