JP4260415B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a capacitor.
[0002]
[Prior art]
In a semiconductor integrated circuit device, various circuits are formed by appropriately combining semiconductor elements such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a capacitor (capacitance).
[0003]
It is necessary to optimize the structure and manufacturing process of these semiconductor elements by using portions (semiconductor regions, conductive films, etc.) that are common to other elements as much as possible.
[0004]
[Problems to be solved by the invention]
The present inventors are engaged in research and development of a semiconductor integrated circuit device, particularly a nonvolatile memory (EEPROM: Electrically Erasable Programmable Read Only Memory, flash memory) that can be electrically written and erased.
[0005]
Since driving of this nonvolatile memory requires a high potential (a potential having a large absolute value), a high voltage MISFET and a booster circuit (step-down circuit) are built in addition to the memory element. The booster circuit is used as a positive power supply generation circuit that generates a high-potential positive voltage, and the step-down circuit is used as a negative power supply generation circuit that generates a high-potential negative voltage.
[0006]
As will be described later, a capacitor is incorporated in this step-up circuit (step-down circuit). The capacitor is composed of a capacitive insulating film and electrodes sandwiching it.
[0007]
The inventors of the present invention use the semiconductor substrate as the first electrode, the silicon oxide film formed thereon as a capacitive insulating film, and the conductive film such as a polycrystalline silicon film formed thereon as the second electrode. The capacitor was examined.
[0008]
As will be described in detail later, the silicon oxide film is formed in the same process as the gate insulating film of the high voltage MISFET, for example, and the polycrystalline silicon film is the same as the floating gate (FG) of the nonvolatile memory. Formed in the process. A capacitor having such a configuration is called a MOS (Metal Oxide Semiconductor) capacitor.
[0009]
However, in a write / erase cycle test (E / W cycle test) of a nonvolatile memory device having such a capacitor, a defect that prevents writing / erasing occurred.
[0010]
Thus, as a result of intensive studies on the cause of this failure, the present inventors have found that this is due to the capacitance insulating film breakdown (gate breakdown) of the capacitor, particularly the gate breakdown of the negative power supply generation circuit.
[0011]
Further, as a result of further investigation, it has been found that such destruction occurs at the end of the element formation region (active). FIG. 42 schematically shows the state (photograph) of gate destruction confirmed by the present inventors. A broken line portion is a boundary between the element formation region AC and the element isolation region 6, and gate breakdown (black circle portion) occurs at the upper part of the boundary.
[0012]
An object of the present invention is to improve the breakdown voltage of a capacitor insulating film of a capacitor.
[0013]
Another object of the present invention is to improve the characteristics of a semiconductor integrated circuit device (particularly, a nonvolatile memory) by improving the breakdown voltage of a capacitor insulating film of a capacitor. Another object is to improve the yield of the semiconductor integrated circuit device.
[0014]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0015]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0016]
(1) A semiconductor integrated circuit device according to the present invention includes (a) a semiconductor substrate having an element formation region partitioned by an element isolation region, and (b) a capacitor formed on the element formation region, wherein (b1 ) A first insulating film formed on the semiconductor substrate; (b2) a first conductive film formed on the first insulating film and formed in the element formation region; and (b3) the first insulating film. A capacitor having a second conductive film formed on the conductive film and extending from the element formation region to the element isolation region; and (c) located in a lower layer of the second conductive film, A second insulating film formed on a boundary between the element isolation region and the element formation region; and (d) an electrode lead portion located on the second conductive film on the element isolation region. .
[0017]
(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, (a) a step of forming an element formation region partitioned by an element isolation region, and (b) forming a first insulating film on the element formation region. And (c) forming a first conductive film on the first insulating film and not extending on a boundary between the element formation region and the element isolation region, and (d) the first Forming a second insulating film on an insulating film on a boundary between the element formation region and the element isolation region; and (e) on the first conductive film and the second insulating film. Forming a second conductive film extending from the element formation region to the element isolation region; (f) forming a third insulating film on the second conductive film; and (g) By selectively removing the third insulating film on the second conductive film located on the element isolation region. A step of forming a connection hole Te and has a.
[0018]
(3) The first insulating film constituting the capacitor can be formed in the same process (same layer) as the gate insulating film of the MISFET formed in another element formation region.
[0019]
Further, the first and second conductive films constituting the capacitor can be formed in the same process (same layer) as the floating gate of the nonvolatile memory formed in another element formation region.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0021]
A method for manufacturing a nonvolatile memory according to an embodiment of the present invention will be described in the order of steps with reference to FIGS. 1 to 34 are cross-sectional views or plan views of main parts of a substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, in which a memory cell is formed (MA). , A peripheral circuit area (LA) or a capacitor area (CA).
[0022]
First, as shown in FIGS. 1 to 3, a mask film (not shown) made of a silicon nitride film or the like is formed on an element formation region of a semiconductor substrate 1 made of, for example, p-type single crystal silicon. As a mask, the semiconductor substrate 1 is etched to form the element isolation trench 4. 1 is a cross-sectional view of a main part of a region MA where a memory cell is formed, FIG. 2 is a cross-sectional view of a main part of a peripheral circuit region LA, and FIG. 3 is a cross-sectional view of a main part of a capacitor region CA. 1 corresponds to the AA cross section (cross section perpendicular to the word line of the memory cell) in FIG. 31 and FIG. 32 (plan view), which will be described later, and the right figure shows B- This corresponds to a B sectional view (a horizontal section with respect to the word line of the memory cell).
[0023]
Next, a thin silicon oxide film (not shown) is formed on the inner wall of the groove by thermal oxidation. This silicon oxide film is formed in order to recover the dry etching damage generated on the inner wall of the groove.
[0024]
Next, a silicon oxide film 6 is deposited on the semiconductor substrate 1 including the inside of the element isolation trench 4 by a CVD (Chemical Vapor deposition) method, and the upper portion of the trench is oxidized by a chemical mechanical polishing (CMP) method. The silicon film 6 is polished and its surface is flattened. Next, the silicon nitride film is removed. Note that the surface of the silicon oxide film 6 gradually recedes through the subsequent cleaning process of the semiconductor substrate 1 and the surface oxidation and oxide film removal processes.
[0025]
Thus, the element isolation region 6 is formed by embedding the silicon oxide film 6 in the element isolation trench 4. That is, the element formation region (active) is surrounded by the element isolation region 6 and is separated from other element formation regions. In other words, the element formation region is partitioned by the element isolation region 6. For example, as shown in FIGS. 29 and 30, the element formation region AC is partitioned.
[0026]
Next, after p-type impurities (boron) and n-type impurities (for example, phosphorus) are ion-implanted into the semiconductor substrate 1, heat treatment is performed to diffuse the impurities, thereby forming the p-type well 8 in the memory cell region MA. Then, the p-type well 8 and the n-type well 7 are formed in the semiconductor substrate 1 in the peripheral circuit region LA and the capacitor region CA.
[0027]
A high breakdown voltage n-channel MISFET is formed in the p-type well 8 of the peripheral circuit region LA, and a high breakdown voltage p-channel MISFET is formed in the n-type well 7. In the figure, these formation regions are denoted as QN and QP, respectively. In the capacitor region CA, the p-type well 8 is formed with a capacitor constituting a negative power supply generation circuit, and the n-type well 7 is formed with a capacitor constituting a positive power supply generation circuit. In the figure, these formation regions are indicated as CNV and CPV, respectively. A channel is formed in the n-type well 7 and the p-type well 8 as necessary.
[0028]
Next, as shown in FIGS. 4 to 6, a thermal oxide film having a thickness of about 25 nm is formed by thermal oxidation. This thermal oxide film constitutes a gate oxide film 9b of a high breakdown voltage MISFET and a capacitor insulating film 9c of a capacitor (MOS capacitor) formed in the peripheral circuit region LA.
[0029]
Next, the region of the high breakdown voltage MISFET and the capacitor (MOS capacitor) is covered with a resist film (not shown), the thermal oxide film in the memory cell region is selectively removed, and then subjected to thermal oxidation to thereby form the memory cell region. A thermal oxide film having a thickness of about 9 nm is formed on the surface of the film. This thermal oxide film forms the gate oxide film 9a of the nonvolatile memory cell.
[0030]
Next, as shown in FIGS. 7 to 9, a polycrystalline silicon film 10 having a film thickness of about 100 nm is deposited on the top of the semiconductor substrate (9a, 9b, 9c) by the CVD method. Subsequently, a silicon nitride film 11 having a thickness of about 170 nm is deposited thereon by a CVD method. Next, the silicon nitride film 11 is dry-etched using a resist film (not shown) as a mask, thereby leaving the silicon nitride film 11 in a region where a gate electrode is to be formed.
[0031]
Next, the polycrystalline silicon film 10 is dry etched using the silicon nitride film 11 as a mask.
[0032]
As a result, a polycrystalline silicon pattern 10a is formed in the memory cell region MA. This polycrystalline silicon pattern 10a becomes the lower layer (FG1) of the floating gate FG of the nonvolatile memory cell. The polycrystalline silicon pattern 10a extends in the Y direction as shown in FIG. FIG. 31 is a plan view of the principal part of the substrate in the memory cell region MA after the formation of the polycrystalline silicon pattern 20a.
[0033]
In the capacitor area CA, a polycrystalline silicon pattern 10b is formed. The polycrystalline silicon pattern 10b becomes a capacitor electrode (CE). The counter electrode of the capacitor electrode CE is a semiconductor substrate (n-type well 7 or p-type well 8).
[0034]
Here, it is important that the width of the polycrystalline silicon pattern 10b in the X direction is smaller than the width of the element formation region AC in the X direction, as shown in FIGS. That is, the patterning is performed so that the polycrystalline silicon pattern 10b is not applied on the boundary (on the dotted line) between the element formation region and the element isolation region extending in the Y direction. FIGS. 33 and 34 are plan views of main parts of the substrate of the CNV and CPV parts after the formation of the silicon oxide film 19 formed between the polycrystalline silicon patterns 10b.
[0035]
Next, as shown in FIG. 7, an n-type impurity (arsenic) is implanted into the p-type well 8 on both sides of the polycrystalline silicon pattern 10a in the memory cell region MA, and then heat treatment is performed to diffuse the impurity. The n-type semiconductor region 17 (source, drain) is formed. Note that a source and drain having an LDD (Lightly doped Drain) structure may be formed by forming a sidewall film on the sidewall of the polycrystalline silicon pattern 10a and implanting n-type impurities before and after the formation.
[0036]
At this time, if the capacitor region CA is not covered with a resist film or the like, the n-type semiconductor region 17 is also formed on both sides of the polycrystalline silicon pattern 10b in the capacitor region CA (FIG. 9).
[0037]
Here, the n-type semiconductor region 17 formed in the n-type well 7 of the capacitor region CA is not a problem, but by forming the n-type semiconductor region 17 in the p-type well 8 of the capacitor region CA, There is a risk that the withstand voltage of the capacitive insulating film 9c between the n-type semiconductor region 17 and the end portion of the polycrystalline silicon pattern 10b is lowered.
[0038]
However, as a result of studies by the present inventors, the breakdown voltage of the capacitive insulating film 9c can be ensured by a GiDL (Gate-Induced-Drain-Leakcurent) phenomenon, as will be described in detail later.
[0039]
Next, as shown in FIGS. 10 to 12, after a silicon oxide film 19 is deposited on the upper portion of the semiconductor substrate 1 by the CVD method, the silicon oxide film 19 is polished by the CMP method until the surface of the silicon nitride film 11 is exposed. Alternatively, etch back to flatten the surface.
[0040]
As a result, a silicon oxide film 19 is formed between the polycrystalline silicon patterns 10a in the memory cell region MA.
[0041]
In the capacitor region CA, a silicon oxide film 19 is formed between the polycrystalline silicon patterns 10b. The silicon oxide film 19 in the capacitor region CA is located at the boundary between the element formation region and the element isolation region extending in the Y direction (see also FIGS. 33 and 34).
[0042]
Next, as shown in FIGS. 13 to 15, the silicon nitride film 11 is removed by hot phosphoric acid or the like, and the surfaces of the polycrystalline silicon film 10 and the polycrystalline silicon patterns 10a and 10b are exposed.
[0043]
Next, a polycrystalline silicon film 20 doped with phosphorus is deposited on the polycrystalline silicon film 10 and the polycrystalline silicon patterns 10a and 10b by the CVD method, and then a resist film (not shown) is used as a mask. The polycrystalline silicon film 20 is dry-etched to form the polycrystalline silicon pattern 20a on the polycrystalline silicon pattern 10a in the memory cell region MA. This polycrystalline silicon pattern 20a becomes the upper layer (FG2) of the floating gate FG of the nonvolatile memory cell. The polycrystalline silicon pattern 20a extends in the Y direction as shown in FIG. That is, the floating gates FG (FG1, FG2) are configured by further patterning the polycrystalline silicon patterns 10a and 20a.
[0044]
The polycrystalline silicon film 20 is also formed on the polycrystalline silicon pattern 10b in the capacitor area CA, and the polycrystalline silicon pattern 10b and the polycrystalline silicon film 20 become a capacitor electrode (CE).
[0045]
Further, the polycrystalline silicon film 20 is also formed on the polycrystalline silicon film 10 in the peripheral circuit region LA, and the polycrystalline silicon films 10 and 20 become the gate electrode G of the MISFET.
[0046]
Next, as shown in FIGS. 16 to 18, an ONO film (interlayer insulating film) 21 is formed on the semiconductor substrate 1. The ONO film 21 is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The ONO film 21 is formed, for example, by sequentially depositing a silicon oxide film having a thickness of about 4 nm, a silicon nitride film having a thickness of about 6 nm, and a silicon oxide film having a thickness of about 4 nm by a CVD method. The ONO film 21 serves to separate the floating gate (FG) and the control gate (CG) constituting the memory cell.
[0047]
Next, the ONO film 21 on the polycrystalline silicon film 20 in the capacitor area CA is selectively removed to form an opening OA (FIG. 18). The opening OA is formed on the polycrystalline silicon film 20 and on the element isolation region 6. The polycrystalline silicon film 20 and a later-described polycrystalline silicon film 22 are connected through the opening OA. Although not shown, at this time, the gate electrode G of the peripheral MISFET is also opened for element isolation and is connected to the polycrystalline silicon 22 described later.
[0048]
Next, a polycrystalline silicon film 22 doped with phosphorus is deposited on the semiconductor substrate 1 by a CVD method. Subsequently, a refractory metal silicide film such as tungsten silicide (WSi) is formed on the upper portion. ₂ ) A film 23 is deposited, and a silicon oxide film 24 is further deposited thereon by a CVD method. This polycrystalline silicon film 22 and WSi ₂ The stacked film of the film 23 becomes a control gate (CG) of the memory cell formed in the memory cell region MA.
[0049]
Next, as shown in FIGS. 19 to 21, using the resist film (not shown) as a mask, the silicon oxide film 24 in the memory cell region MA, WSi ₂ The film 23, the polycrystalline silicon film 22, the ONO film 21, and the polycrystalline silicon patterns 10a and 20a are dry-etched.
[0050]
In memory cell region MA, polycrystalline silicon film 22 and WSi ₂ The laminated film of the film 23 becomes the control gate CG of the memory cell, and this control gate CG extends in the X direction as shown in FIG. Note that the control gate CG formed in the memory cell region MA functions as the word line WL. FIG. 32 is a plan view of the principal part of the substrate of the memory cell region MA after the formation of the control gate CG.
[0051]
Further, the polycrystalline silicon patterns 10a and 20a are divided for each cell by this etching, and become polycrystalline silicon patterns FG1 and FG2, respectively. These patterns constitute the floating gate FG (FIG. 19).
[0052]
In the peripheral circuit region LA, these films (24, 23, 22, 21, 20, 10) remain in the region where the gate electrode G is formed, and the gate electrode made of the polycrystalline silicon films 10 and 20 is formed. G is formed (FIG. 20).
[0053]
In the capacitor area CA, these films (24, 23, 22, 21, 20, 10b) are divided for each capacitor (FIG. 21).
[0054]
Here, as shown in FIGS. 21, 29, and 30, the polycrystalline silicon film 20 is patterned so as to extend over the element isolation region 6. Further, the width in the Y direction of the polycrystalline silicon film 20 and the polycrystalline silicon pattern 10b is patterned smaller than the width in the Y direction of the element formation region AC. Therefore, the polycrystalline silicon pattern 10b is formed inside the element formation region AC.
[0055]
Next, as shown in FIG. 20, n-type impurities are implanted by injecting n-type impurities into the p-type well 8 (semiconductor substrate 1) on both sides of the gate electrode G in the peripheral circuit region LA. ^- A type semiconductor region 25n is formed. In addition, p-type impurities are implanted into the n-type well 7 (semiconductor substrate 1) on both sides of the gate electrode G in the peripheral circuit region LA. ^- A type semiconductor region 25p is formed.
[0056]
At this time, although not shown in the cross section shown in FIG. 21, the n-type wells 7 on both sides in the Y direction of the polycrystalline silicon film 22 in the capacitor region CA are also n. ^- P type well region 25n is formed, and p type well 8 on both sides in the Y direction of polycrystalline silicon film 22 in capacitor region CA is also p-type. ^- A type semiconductor region 25p is formed (see FIGS. 27, 28, 29, and 30).
[0057]
Next, the polycrystalline silicon patterns FG1, FG2, the polycrystalline silicon film 22 and the WSi in the memory cell region MA are formed by light oxidation. ₂ A light oxide film 26 is formed on the sidewall of the film 23. Note that the gate electrode G in the peripheral circuit region LA, etc. (polycrystalline silicon films 10 and 20, polycrystalline silicon film 22 and WSi ₂ A light oxide film 26 is also formed on the side wall of the film 23).
[0058]
Next, as shown in FIGS. 22 to 24, a silicon oxide film 28 is deposited on the semiconductor substrate 1 by a CVD method, and then anisotropically etched to form sidewalls such as the gate electrode G in the peripheral circuit region LA. Sidewall films 28s are formed. At this time, the sidewall film 28s is also formed on the sidewall of the memory cell region MA such as the control gate CG and the sidewall of the capacitor region CA such as the polycrystalline silicon film 20.
[0059]
Next, n-type impurities are implanted into the p-type well 8 (semiconductor substrate 1) on both sides of the gate electrode G in the peripheral circuit region LA, thereby forming n. ⁺ A type semiconductor region 27n (source, drain) is formed. In addition, p-type impurities are implanted into the n-type well 7 (semiconductor substrate 1) on both sides of the gate electrode G in the peripheral circuit region LA. ⁺ A type semiconductor region 27p (source, drain) is formed.
[0060]
At this time, although not shown in the cross section shown in FIG. 24, the n-type wells 7 on both sides in the Y direction of the polycrystalline silicon film 22 in the capacitor region CA are also n-type. ⁺ P-type semiconductor region 27n is formed, and p-type well 8 on both sides in the Y direction of polycrystalline silicon film 22 in capacitor region CA is also p-type. ⁺ A type semiconductor region 27p is formed (see FIGS. 27, 28, 29, and 30). This n ⁺ Type semiconductor regions 27n and p ⁺ The type semiconductor region 27p serves as a power supply region for supplying power to the n-type well 7 and the p-type well 8, respectively.
[0061]
Through the above process, the control gate CG (polycrystalline silicon film 22, WSi is formed in the memory cell region MA. ₂ An AND-type nonvolatile memory cell having a film 23), an ONO film 21 and a floating gate FG (polycrystalline silicon patterns FG1, FG2) is formed, and a high breakdown voltage n-channel MISFET QN and p-channel MISFET QP are formed in the peripheral circuit area LA. It is formed. In the capacitor region CA, the semiconductor substrate (n-type well 7 and p-type well 8) is used as the lower electrode of the capacitor, and the polycrystalline silicon pattern 10b and the polycrystalline silicon film 20 are used as the upper electrode CE of the capacitor. Capacitors CPV and CNV having the capacitive insulating film 9c are formed.
[0062]
Next, an interlayer insulating film made of a silicon oxide film or the like is formed on the silicon oxide film 24 and the sidewall film 28s, and a wiring made of a conductive film is formed on the interlayer insulating film.
[0063]
These forming steps will be described with reference to FIGS. 25 to 30 which are cross-sectional views or plan views of main parts of the substrate in the capacitor area CA. Needless to say, plugs and wirings to be described later are formed in the memory cell region MA and the peripheral circuit region LA as needed.
[0064]
25 and 27 are principal part cross-sectional views of the capacitor CPV part on the n-type well 7 in the capacitor area CA, and FIG. 29 is a principal part plan view. FIG. 26 and FIG. 28 are principal part sectional views of the capacitor CNV part on the p-type well 8 in the capacitor region CA, and FIG. 30 is a principal part plan view. 25 and 27 correspond to the CC cross-section and the DD cross-section of FIG. 29, respectively. 26 and 28 correspond to the CC cross-section and DD cross-section of FIG. 30, respectively.
[0065]
As shown in FIGS. 25 to 30, a silicon oxide film 30 is formed on the upper portion of the semiconductor substrate 1 (silicon oxide film 24 and the like) by a CVD method, and the upper portion is planarized by using a CMP method or the like, if necessary. To do.
[0066]
Then WSi ₂ The contact hole C1 is formed by selectively removing the silicon oxide films 24 and 30 above the film 23. At this time, n ⁺ Type semiconductor regions 27n and p ⁺ The contact hole C2 is formed by selectively removing the silicon oxide film 30 above the type semiconductor region 27p.
[0067]
Here, the contact hole C 1 is formed on the polycrystalline silicon film 20 located on the element isolation region 6. As a result, it is possible to reduce the influence of damage caused when the contact hole C1 is formed (when the silicon oxide film 30 or the like is etched) on the capacitor insulating film 9c.
[0068]
Next, after depositing a conductive film such as tungsten (W) on the silicon oxide film 30 including the inside of the contact holes C1 and C2 by sputtering, the conductive film outside the contact holes C1 and C2 is removed by CMP or the like. Thus, a plug (electrode lead part) P1 is formed.
[0069]
Next, a conductive film such as W is deposited by sputtering on the silicon oxide film 30 including the plug P1, and the first layer wiring M1 is formed by etching into a desired shape.
[0070]
Thereafter, multilayer wiring can be formed on the upper portion of the first layer wiring M1 by repeating the process of forming an interlayer insulating film made of a silicon oxide film or the like, a plug, and wiring. Is omitted.
[0071]
Thus, in the present embodiment, the capacitor electrode CE is composed of two layers, that is, the polycrystalline silicon film 10b and the polycrystalline silicon film 20, so that the lower layer 10b is formed inside the element forming region, that is, the element forming region. It can be formed so as not to be on the boundary with the element isolation region. In other words, the polycrystalline silicon film 10b can be offset from the element formation region.
[0072]
In addition, the silicon oxide film 19 can be formed on the boundary between the element formation region and the element isolation region. Therefore, it is possible to prevent the capacitance insulating film from being broken due to electric field concentration at the end of the element isolation region (silicon oxide film 6).
[0073]
That is, for example, as shown in FIG. 40, similarly to the polycrystalline silicon film 20, the polycrystalline silicon pattern 10b extends to the boundary between the element formation region and the element isolation region, and the polycrystalline silicon patterns 10b and 20b. When a potential is applied to the capacitor, the electric field concentrates on the capacitor insulating film 9c on the boundary between the element formation region and the element isolation region, and the capacitor insulating film is destroyed.
[0074]
Although the boundary between the element formation region and the element isolation region is not clearly shown in the drawing, the surface of the silicon oxide film 6 is likely to retreat from the surface of the semiconductor substrate 1 so that a so-called recess phenomenon easily occurs. A step is likely to occur on the boundary between the region and the element isolation region.
[0075]
Therefore, in such a portion, the film thickness and film quality of the capacitive insulating film are likely to change, are easily affected by electric field concentration, and the insulating film is likely to be broken.
[0076]
In order to avoid this influence, there is a means of actively rounding the step shape, but it is not perfect.
[0077]
In addition, in order to secure the capacitance of the capacitor, it is necessary to increase the capacitor area. As a result, the boundary region is expanded, and the probability of destruction of the capacitive insulating film is increased.
[0078]
In addition, since driving of the nonvolatile memory requires a high potential (a potential with a large absolute value of the potential), a plurality of booster circuits (step-down circuits) are prepared, and step-up (step-down) is performed. Therefore, a capacitor is required for each of these circuits, and if any of the used capacitors is destroyed, the memory operation cannot be performed.
[0079]
35 to 37 show an example of the step-down circuit and its driving state. As shown in the figure, such a circuit has seven MISFETs (T1 to T7) and two capacitors Ca1 and Ca2. The capacitance of the capacitor Ca1 is 8 pF, and the capacitance of Ca2 is 10 pF.
[0080]
For example, as shown in FIG. 35, the driving method is as follows: 1) P1IN (first electrodes of capacitors Ca1 and Ca2) is set to 7.2 V of VWDP via MISFETs T1 and T2. At this time, if there is an n-type semiconductor region in the p-type well, the p-type well is charged up to 7.2V. 2) Next, the second electrodes of the capacitors Ca1 and Ca2 are set to −6.4 V through the pair of MISFETs T6 and T7.
[0081]
Next, as shown in FIG. 36, the pair of MISFET T1 and MISFET T6 and T7 is turned off, and the potential of P1IN is extracted through MISFET T3. As a result, the potential of P1IN can be lowered to -13.6V in an ideal state.
[0082]
Next, as shown in FIG. 37, when the MISFET T3 is turned off and the potential of the p-type well is lowered to −6.4 V by the MISFET T5, the second electrodes of the capacitors Ca1 and Ca2 can be set to −20 V, and P1OUT and A potential of −20 V is supplied from P2OUT.
[0083]
The MISFET T4 plays a role of controlling the isolation voltage. CLK1, DFSCVCP, DFSCVCOVE, 003T, and ON1T are control signals.
[0084]
Although a configuration example of the booster circuit is omitted, it can be similarly configured using a plurality of MISFETs and capacitors.
[0085]
As described above, in this embodiment, it is possible to prevent the capacitance insulating film from being broken due to the electric field concentration at the end of the element isolation region (silicon oxide film 6). For example, the characteristics of the capacitors constituting the booster circuit or the step-down circuit The characteristics of the semiconductor integrated circuit device can be improved. In addition, the yield can be improved.
[0086]
In particular, a nonvolatile memory requires a high-potential signal for driving, and a capacitor used in a booster circuit or a step-down circuit has a large capacity or is used in multiple stages. Therefore, the configuration of this embodiment is preferable. is there.
[0087]
In addition, in order to evaluate a capacitive insulating film due to electric field concentration and extract defective products, it is necessary to perform a probe test, a stress acceleration test, and the like in addition to the above-described E / W cycle test. Many of these tests require time, leading to an increase in test cost and TAT (turn around time).
[0088]
However, according to the present embodiment, the capacitance insulating film can be prevented from being destroyed and the characteristics of the capacitor can be improved, so that the test time of the stress acceleration test can be reduced. TAT can be shortened.
[0089]
In the present embodiment, since the capacitor electrode CE is constituted by two layers of the polycrystalline silicon pattern 10b and the polycrystalline silicon film 20, the polycrystalline silicon film 20 can be extended to the element isolation region. As a result, the plug P1 and the like can be formed using the polycrystalline silicon film 20 on the element isolation region, and deterioration of the characteristics of the capacitive insulating film 9c can be prevented.
[0090]
For example, as shown in FIG. 41, it is possible to make the polycrystalline silicon film 20 have the same shape as the polycrystalline silicon pattern 10b. In this case, however, the plug P1 must be formed above the element formation region. . In such a case, the influence of etching damage when forming the contact hole C1 in the capacitive insulating film 9c is unavoidable, and the characteristics of the capacitive insulating film 9c are deteriorated.
[0091]
In the nonvolatile memory according to the present embodiment, since the floating gate FG is composed of two layers (FG1 and FG2), 10a and 20 constituting the capacitor electrode CE are the same as the film constituting the floating gate FG. By comprising a layer film, it is easy to optimize the manufacturing process.
[0092]
In the present embodiment, the gate oxide film 9b of the high breakdown voltage MISFET and the capacitor insulating film 9c of the capacitor can be formed of the same layer, and the manufacturing process can be easily optimized.
[0093]
In particular, the gate oxide film 9b of the high breakdown voltage MISFET is thicker than the gate oxide film 9a and ONO film 21 of the nonvolatile memory, and by using a film of the same layer as the capacitor insulating film 9c, the breakdown voltage of the capacitor insulating film can be reduced. Improvements can be made.
[0094]
However, even with a high withstand voltage MISFET, its film thickness is reduced in order to bring out the maximum capability of the MISFET. Further, the film thickness tends to be reduced as the element is miniaturized. Therefore, it is necessary to further improve the breakdown voltage of the gate insulating film using the present invention.
[0095]
Of course, the capacitor insulating film may be formed using a film in the same layer as the gate oxide film 9a of the nonvolatile memory or the gate insulating film of the low breakdown voltage MISFET.
[0096]
Further, in the present embodiment, when forming the n-type semiconductor region 17 (source, drain) of the nonvolatile memory, the capacitor region CA is not covered with a resist film or the like, but in the p-type well 8 of the capacitor region CA. Even if the n-type semiconductor region 17 is formed, the breakdown voltage of the capacitive insulating film 9c can be secured by the GiDL phenomenon.
[0097]
For example, when a negative voltage is applied to the capacitor electrode CE shown in FIG. 24 and a positive voltage is applied to the semiconductor substrate (p-type well 8), positive charges are accumulated in the n-type semiconductor region 17. Therefore, the potential difference between the n-type semiconductor region 17 and the capacitor electrode CE (negative potential) increases, and there is a concern about the destruction of the capacitive insulating film 9c.
[0098]
However, when a high potential is applied to the capacitor electrode CE, a GiDL phenomenon occurs, and the positive charge accumulated in the n-type semiconductor region 17 is discharged to the semiconductor substrate, so that the end of the capacitive insulating film 9c A high voltage is not applied to the portion (near the n-type semiconductor region 17).
[0099]
The evaluation result of GiDL is shown, referring to FIG. 38 and FIG. FIG. 38 schematically shows the structure of the capacitor shown in FIG. As shown in FIG. 38, the capacitor has a structure similar to that of the MISFET, which is called a MOS capacitor.
[0100]
Here, when the source is in an open state, the gate potential is Vg is a negative potential, and the well potential is 0 V, the drain potential Vd is changed from 0 V to 6 V, and positive charges are accumulated in the drain. Checked the status. In this case, it can be considered that the potential difference between the gate electrode and the drain becomes large, a gate leakage current flows between them, and the gate insulating film is destroyed.
[0101]
However, as shown in FIG. 39, the drain current Id (solid line) coincides with the substrate current Ibb (broken line) even when the gate potential Vg with respect to the gate insulating film thickness is 0 MV / cm and 8 MV / cm. It was found that no current was flowing into the gate electrode side. Therefore, for example, even when a high potential of −20 V is applied to the gate electrode, Id becomes a substrate current due to the 100% GiDL phenomenon and is discharged to the substrate side, and a high voltage is applied to the edge of the gate insulating film. Not. The scale on the left side of the vertical axis indicates the magnitude of the drain current Id (solid line), and the scale on the right side indicates the magnitude of the substrate current Ibb (dashed line). The horizontal axis represents the drain potential Vd.
[0102]
Thus, according to the present embodiment, it is possible to ensure the withstand voltage of the capacitive insulating film 9c.
[0103]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0104]
In particular, in this embodiment, the semiconductor integrated circuit device having a nonvolatile memory has been described as an example. However, the present invention can be widely applied to a capacitor, in particular, a semiconductor device having a high voltage generation circuit using the capacitor.
[0105]
In this embodiment, a capacitor for step-down (step-up) has been described as an example. However, in addition to this, a capacitor for smoothing power supply noise is used in the internal power supply circuit. Is also applicable to such a capacitor.
[0106]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.
[0107]
The capacitor includes a semiconductor substrate, an insulating film formed thereon, a first conductive film formed on the insulating film, and a second conductive film formed on the first conductive film. Since the first conductive film is formed so as not to be on the boundary between the element isolation region of the semiconductor substrate and the element formation region, the breakdown voltage of the insulating film serving as the capacitor insulating film can be improved.
[0108]
In addition, the characteristics of the semiconductor integrated circuit device can be improved. In addition, the yield of the semiconductor integrated circuit device can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a principal part of a substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 2 is a fragmentary cross-sectional view of a substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a principal part of the substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a principal part of the substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 5 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of the principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.
7 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
FIG. 8 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 9 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention;
FIG. 10 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 11 is a cross-sectional view of the essential part of the substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 12 is a fragmentary cross-sectional view of a substrate showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention;
13 is a fragmentary cross-sectional view of a substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
FIG. 14 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 15 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 16 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 17 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 18 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 19 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 20 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 21 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 22 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 23 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 24 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 25 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 26 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 27 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
FIG. 28 is a cross sectional view of the essential part of the substrate, for showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.
29 is a substantial part plan view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
30 is a substantial part plan view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
FIG. 31 is a substantial part plan view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;
32 is a substantial part plan view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
33 is a substantial part plan view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
34 is a substantial part plan view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
FIG. 35 is a circuit diagram showing an example of a step-down circuit used in a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 36 is a circuit diagram showing an example of a step-down circuit used in the semiconductor integrated circuit device according to the embodiment of the present invention.
FIG. 37 is a circuit diagram showing an example of a step-down circuit used in a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 38 is a diagram for explaining the effect of the embodiment of the present invention.
FIG. 39 is a diagram (graph) for explaining the effect of the embodiment of the present invention;
FIG. 40 is a fragmentary cross-sectional view of the substrate of the semiconductor integrated circuit device for illustrating the effect of the embodiment of the present invention;
41 is a fragmentary cross-sectional view of the substrate of the semiconductor integrated circuit device for illustrating the effect of the embodiment of the present invention; FIG.
42 is a substantial part plan view of a substrate of a semiconductor integrated circuit device for illustrating a problem of the present invention; FIG.
[Explanation of symbols]
1 Semiconductor substrate
4 Element isolation groove
6 Device isolation region (silicon oxide film)
7 n-type well
8 p-type well
9a Gate oxide film
9b Gate oxide film
9c capacitive insulating film
10 Polycrystalline silicon film
10a Polycrystalline silicon pattern
10b Polycrystalline silicon pattern
11 Silicon nitride film
17 n-type semiconductor region
19 Silicon oxide film
20 Polycrystalline silicon film
20a polycrystalline silicon pattern
21 ONO film
22 Polycrystalline silicon film
23 Tungsten silicide film (WSi ₂ film)
24 Silicon oxide film
25n n ^- Type semiconductor region
25pp ^- Type semiconductor region
26 Light oxide film
27n n ⁺ Type semiconductor region
27pp ⁺ Type semiconductor region
28 Silicon oxide film
28s sidewall film
30 Silicon oxide film
AC element formation region
C1 contact hole
C2 contact hole
CA capacitor area
CE capacitor (upper) electrode
CG control gate
CNV capacitor (formation region)
CPV capacitor (formation area)
Ca1 capacitor
Ca2 capacitor
CLK1, DFSCVCP, DFSCVCOVE, 003T, ON1T Control signal
FG floating gate
FG1 Floating gate lower layer
FG2 Floating gate upper layer
G Gate electrode
LA peripheral circuit area
M1 first layer wiring
MA memory cell area
OA opening
P1 plug
P1IN, P1OUT, P2OUT Node (terminal)
QN n-channel MISFET (formation region)
QP p-channel MISFET (formation region)
T1-T7 MISFET
Vg Gate potential
Vd Drain potential
WL Word line

Claims (5)

(A) a semiconductor substrate having an element formation region partitioned by an element isolation region;
(B) a capacitor formed on the element formation region,
(B1) a first insulating film formed on the semiconductor substrate;
(B2) a first conductive film formed on the first insulating film and formed in the element formation region;
(B3) a capacitor having a second conductive film formed on the first conductive film and extending from the element formation region to the element isolation region;
(C) a second insulating film located under the second conductive film and formed on a boundary between the element isolation region and the element formation region;
(D) an electrode lead portion located on the second conductive film on the element isolation region;
A semiconductor integrated circuit device comprising: The semiconductor device includes first and second element formation regions partitioned by an element isolation region on the semiconductor substrate, wherein a MISFET is formed in the first element formation region, and a capacitor is formed in the second element formation region A semiconductor integrated circuit device formed with
(A) The MISFET is
(A1) a first insulating film formed on the semiconductor substrate;
(A2) a first conductive film formed on the first insulating film;
(A3) a semiconductor region formed in the semiconductor substrate on both sides of the first conductive film;
Have
(B) The capacitor is
(B1) a second insulating film formed on the semiconductor substrate and in the same layer as the first insulating film;
(B2) a second conductive film formed on the second insulating film and in the second element formation region;
(B3) a capacitor having a third conductive film formed on the second conductive film and extending from the element formation region to the element isolation region;
(C) a third insulating film located under the third conductive film and formed on a boundary between the element isolation region and the element formation region;
A semiconductor integrated circuit device comprising: The semiconductor device includes first and second element formation regions partitioned by an element isolation region on a semiconductor substrate, a nonvolatile memory is formed in the first element formation region, and the second element formation region is A semiconductor integrated circuit device in which a capacitor is formed,
(A) the nonvolatile memory,
(A1) a first insulating film formed on the semiconductor substrate;
(A2) a first conductive film formed on the first insulating film;
(A3) a second conductive film formed on the first conductive film;
(A4) a third conductive film formed on the second conductive film via a second insulating film;
(A5) a non-volatile memory having a semiconductor region formed in the semiconductor substrate on both sides of the first conductive film;
(B) the capacitor,
(B1) a third insulating film formed on the semiconductor substrate;
(B2) a fourth conductive film on the third insulating film and formed in the second element formation region and in the same layer as the first conductive film;
(B3) A fifth conductive film formed on the fourth conductive film and in the same layer as the second conductive film, the fifth conductive film extending from the element formation region to the element isolation region. A capacitor having a conductive film;
(C) a fourth insulating film located under the fifth conductive film and formed on a boundary between the element isolation region and the element formation region;
A semiconductor integrated circuit device comprising: A first, second, and third element formation region partitioned by an element isolation region on a semiconductor substrate, and a non-volatile memory is formed in the first element formation region, and the second element formation A semiconductor integrated circuit device in which a MISFET is formed in the region and a capacitor is formed in the third element formation region;
(A) the nonvolatile memory,
(A1) a first insulating film formed on the semiconductor substrate;
(A2) a first conductive film formed on the first insulating film;
(A3) a second conductive film formed on the first conductive film;
(A4) a third conductive film formed on the second conductive film via a second insulating film;
(A5) a first semiconductor region formed in the semiconductor substrate on both sides of the first conductive film;
Have
(B) The MISFET is
(B1) a third insulating film formed on the semiconductor substrate and thicker than the first and second insulating films;
(B2) a fourth conductive film formed on the third insulating film;
(B3) a second semiconductor region formed in the semiconductor substrate on both sides of the third conductive film;
Have
(C) the capacitor is
(C1) a fourth insulating film formed on the semiconductor substrate and in the same layer as the third insulating film;
(C2) a fifth conductive film on the fourth insulating film and formed in the third element formation region and in the same layer as the first conductive film;
(C3) A sixth conductive film formed on the fifth conductive film and in the same layer as the second conductive film, the sixth conductive film extending from the element formation region to the element isolation region. A capacitor having a conductive film;
(D) a fifth insulating film located under the sixth conductive film and formed on a boundary between the element isolation region and the element formation region;
A semiconductor integrated circuit device comprising: (A) forming an element formation region partitioned by an element isolation region;
(B) forming a first insulating film on the element formation region;
(C) forming a first conductive film on the first insulating film and not extending on a boundary between the element formation region and the element isolation region;
(D) forming a second insulating film on the first insulating film and on the boundary between the element formation region and the element isolation region;
(E) forming a second conductive film on the first conductive film and the second insulating film and extending from the element formation region to the element isolation region;
(F) forming a third insulating film on the second conductive film;
(G) forming a connection hole by selectively removing the third insulating film above the second conductive film located on the element isolation region;
A method for manufacturing a semiconductor integrated circuit device, comprising:

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