JP4231861B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4231861B2 JP4231861B2 JP2005217627A JP2005217627A JP4231861B2 JP 4231861 B2 JP4231861 B2 JP 4231861B2 JP 2005217627 A JP2005217627 A JP 2005217627A JP 2005217627 A JP2005217627 A JP 2005217627A JP 4231861 B2 JP4231861 B2 JP 4231861B2
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- frame
- semiconductor element
- pad support
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
本発明では、ダイパッドサポートの熱膨張によるダイパッドの厚み方向への変位を抑制することのできる半導体装置を提供することを目的とする。
また、ダイパッドサポートの形状として、枠部を用いることで第1のダイパッドサポート部分と第2のダイパッドサポート部分とが一直線に配置されないようにしているため、ダイパッドサポートの熱膨張による伸びを吸収できるとともに、ワイヤボンディングする際に半導体素子を吸引するバキューム穴を十分に大きくとることが可能となる。
2 ダイパッド
3 ダイパッドサポート
4 インナーリード
5 ダムバー
6 めっき部
7 応力緩和部
8 凸部
9 切り欠き部
10 折り曲げ部
11 半導体素子
Claims (4)
- ダイパッドと、
前記ダイパッドを取り囲む略矩形形状の枠体と、
前記枠体のそれぞれのコーナー部において前記枠体を支持する第1のダイパッドサポートと、
前記枠体のそれぞれの辺部と前記ダイパッドとを接続する第2のダイパッドサポートと、
前記枠体の周囲に先端がそれぞれ配置された複数のインナーリードと、
前記ダイパッドと前記枠体との上に配置され、前記ダイパッドに固着された半導体チップと、
前記半導体チップと前記ダイパッドと前記枠体と前記第1のダイパッドサポートと前記第2のダイパッドサポートと前記インナーリードとを封止する封止樹脂と、を含み、
前記半導体チップの表面を覆う部分の前記封止樹脂の厚さと、前記半導体チップの裏面を覆う部分の前記封止樹脂の厚さとが等しいことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1のダイパッドサポートは隣り合う前記インナーリードに沿って延在する第1の部分を有することを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記第1のダイパッドサポートの前記第1の部分にダウンセット部が設けられていることを特徴とする半導体装置。
- 請求項1〜3のいずれか1つに記載の半導体装置において、前記半導体チップと前記インナーリードとをそれぞれ接続するボンディングワイヤを有することを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005217627A JP4231861B2 (ja) | 2005-07-27 | 2005-07-27 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005217627A JP4231861B2 (ja) | 2005-07-27 | 2005-07-27 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002363568A Division JP2003179195A (ja) | 2002-12-16 | 2002-12-16 | 半導体装置および半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005317999A JP2005317999A (ja) | 2005-11-10 |
JP4231861B2 true JP4231861B2 (ja) | 2009-03-04 |
Family
ID=35445025
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005217627A Expired - Lifetime JP4231861B2 (ja) | 2005-07-27 | 2005-07-27 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4231861B2 (ja) |
-
2005
- 2005-07-27 JP JP2005217627A patent/JP4231861B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2005317999A (ja) | 2005-11-10 |
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