JP4153015B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a gate electrode structure of a thin film transistor (hereinafter abbreviated as TFT) using a semiconductor thin film.

  In recent years, an active matrix liquid crystal display device (hereinafter abbreviated as AMLCD) in which a pixel matrix circuit and a drive circuit are configured by TFTs formed on a glass substrate or a quartz substrate has attracted attention.

  Such AMLCDs range from those for projectors of about 0.5 to 2 inches to those for notebook computers of about 10 to 20 inches, and are mainly used as display displays from small to medium size.

  When the AMLCD is made medium-sized, the area of the pixel matrix circuit serving as an image display portion increases, and the source lines and gate lines arranged in a matrix form have a large additional capacity.

  Therefore, it is considered promising to use aluminum or a material containing aluminum as a main component (hereinafter abbreviated as aluminum material) as the wiring.

  However, as a result of failure analysis of the TFT in which the inventors have caused a malfunction, it has been found that there is a possibility that a short circuit (short circuit) has occurred between the gate electrode / channel.

  This is presumably because the gate electrode and the channel are short-circuited for some reason despite being insulated by the gate insulating film, causing the TFT to malfunction. There are three possible causes for this.

(1) Aluminum atoms diffuse into the gate insulating film and reach the channel in contact with the gate insulating film.
(2) Projections such as hillocks and whiskers generated from the aluminum material penetrate the gate insulating film and reach the channel.
(3) Pinholes existed in the gate insulating film, and during the heat treatment, aluminum atoms flowed into the pinholes and reached the channel.

  The above factors can be considered, but at present the clear mechanism is unknown. However, it is almost certain that the short circuit between the gate electrode / channel is the cause, and there is a high possibility that one of the above three causes.

  It is an object of the present invention to provide a technique for realizing a TFT using an aluminum material as a gate electrode with a high yield.

  Therefore, it is an object to provide a technique for preventing a short circuit between a gate electrode and a channel (active layer). It is another object of the present invention to provide a novel method for forming an LDD region.

The configuration of the invention disclosed in this specification is as follows.
A semiconductor device including a semiconductor circuit composed of a plurality of TFTs formed on the same substrate.
The TFT has an active layer, a gate insulating film, and a gate electrode formed by laminating a tantalum layer and a material layer mainly composed of aluminum or aluminum,
The tantalum layer has a film thickness that can function as a blocking layer that prevents aluminum or a constituent element of a material layer containing aluminum as a main component from entering the gate insulating film.

  The gist of the present invention is to prevent the aluminum component from penetrating into the gate insulating film by using a tantalum / aluminum laminated film (tantalum as a lower layer) as a gate electrode that has been conventionally constituted only by an aluminum material. That is, the tantalum layer provided in the lower layer is used as a blocking layer for the aluminum component.

  Therefore, the film thickness of the tantalum layer must be thick enough to function as a barrier against the movement of the aluminum component. According to the knowledge of the present inventors, a tantalum layer having a thickness of 5 nm or more is necessary. Below this, a blocking effect cannot be expected.

  The upper limit is about 200 nm. Above this, the aluminum material must be thinned in order to suppress the total film thickness of the gate electrode (to reduce the level difference), and the low resistance characteristic of aluminum cannot be utilized.

  From the above, it can be said that the film thickness of the tantalum layer is preferably selected from the range of 5 to 200 nm (preferably 10 to 100 nm, more preferably 20 to 50 nm).

  The tantalum film is characterized in that it can be easily anodized with the same electrolytic solution as the aluminum film, and the form of the anodized layer (such as the direction of progress of the oxide layer formation process) is close to that of the aluminum film. It is a material suitable for use in the invention.

In addition, the configuration of other inventions is as follows:
A semiconductor device including a semiconductor circuit composed of a plurality of TFTs formed on the same substrate.
The TFT has an active layer, a gate insulating film, and a gate electrode formed by laminating a tantalum layer and a material layer mainly composed of aluminum or aluminum,
A tantalum oxide layer is formed in a region of the tantalum layer that does not overlap with the aluminum or the material layer containing aluminum as a main component.

In addition, the configuration of other inventions is as follows:
A semiconductor device including a semiconductor circuit composed of a plurality of TFTs formed on the same substrate.
The TFT has an active layer, a gate insulating film, and a gate electrode formed by laminating a tantalum layer and a material layer mainly composed of aluminum or aluminum,
An end portion of the tantalum layer protrudes outside the aluminum or a material layer mainly composed of aluminum, and a tantalum oxide layer is formed at the protruding end portion.

In addition, the configuration of other inventions is as follows:
A semiconductor device including a semiconductor circuit composed of a plurality of TFTs formed on the same substrate.
The TFT has an active layer, a gate insulating film, and a gate electrode formed by laminating a tantalum layer and a material layer mainly composed of aluminum or aluminum,
The end of the tantalum layer protrudes outside the aluminum or aluminum-based material layer,
The position of the source or drain junction included in the active layer is defined by the protruding end.

  One of the features of the present invention is that a tantalum oxide layer obtained by anodizing a part of the tantalum layer is used as a mask when forming an LDD region. That is, through doping is performed on the active layer through the tantalum oxide layer to form an LDD region under the tantalum oxide layer.

  Therefore, there is a feature of the structure that a tantalum oxide layer is formed in substantially the same shape on the LDD region provided in the active layer.

In addition, the configuration of other inventions is as follows:
A method for manufacturing a semiconductor device including a semiconductor circuit including a plurality of TFTs formed on the same substrate.
A first step of forming an active layer and a gate insulating film;
A second step of forming a gate electrode formed by sequentially laminating a tantalum layer and aluminum or a material layer mainly composed of aluminum;
A third step of selectively anodizing only the aluminum or a material layer mainly composed of aluminum to form a porous alumina layer;
A nonporous alumina layer is formed on the surface of the aluminum or a material layer mainly composed of aluminum by anodic oxidation again, and at the same time, all or a part of the tantalum layer located under the porous alumina layer is tantalum. A fourth step of transforming into an oxide layer;
It is characterized by having.

In addition, the configuration of other inventions is as follows:
A method for manufacturing a semiconductor device including a semiconductor circuit including a plurality of TFTs formed on the same substrate.
A first step of forming an active layer and a gate insulating film;
A second step of forming a gate electrode formed by sequentially laminating a tantalum layer and aluminum or a material layer mainly composed of aluminum;
A third step of selectively anodizing only the aluminum or a material layer mainly composed of aluminum to form a porous alumina layer;
A nonporous alumina layer is formed on the surface of the aluminum or the material layer containing aluminum as a main component by anodic oxidation again, and at the same time, all or a part of the tantalum layer located under the porous alumina layer is tantalum. A fourth step of transforming into an oxide layer;
A fifth step of etching the gate insulating film using the nonporous alumina layer and the porous alumina layer as a mask;
A sixth step of adding an impurity imparting N-type or P-type using the gate electrode, tantalum oxide layer and gate insulating film as a mask;
It is characterized by having.

  In the above structure, the third step is performed in a solution containing oxalic acid as a main component. In such a solution, only the aluminum material is selectively anodized, and the tantalum layer remains as it is.

  The fourth step is performed in a solution containing tartaric acid as a main component. In this solution, both the aluminum material and the tantalum layer are anodized. By this treatment, the aluminum material is covered with a dense nonporous alumina layer, and a part of the tantalum layer (a portion in contact with the solution) is transformed into a tantalum oxide layer.

  By using the present invention, defects such as a short circuit between the gate electrode and the active layer can be prevented even in a TFT using aluminum or a material mainly composed of aluminum as the gate electrode.

  In addition, since the LDD region and the offset region can be formed without causing extra damage to the gate insulating film, the long-term reliability of the TFT is also improved.

  Accordingly, a highly reliable TFT can be manufactured with a high yield, and an electro-optical device that functions in a semiconductor circuit including such a TFT and a yield of an electronic device equipped with such a semiconductor circuit or electro-optical device. Improvement is realized.

  An embodiment of the present invention will be described with reference to FIG. FIG. 1A is a cross-sectional view along the channel direction (direction in which the carrier moves) using the present invention. However, the interlayer insulating film covering the gate electrode, the source / drain electrode, etc. are omitted.

  In FIG. 1A, 101 is a substrate, and 102 is a base film (insulating silicon film). In the case of providing a base film, the substrate 101 can be made of glass (including crystallized glass), a silicon wafer, ceramics, quartz, or the like. When quartz is used, there is no need to have a base film.

  Reference numeral 103 denotes an active layer, which is obtained by patterning a semiconductor thin film (typically a polycrystalline polysilicon film) in an island shape. In the present invention, any semiconductor thin film may be used as the active layer 103.

  For example, an SOI substrate (UNIBOND) or a SIMOX substrate using a smart cut method can be used. In that case, since the active layer can be formed of single crystal silicon, a TFT having very high operation performance can be realized.

  A gate electrode is disposed on the active layer 103 via a gate insulating film 104. The gate electrode is mainly composed of the aluminum layer 105, and a TFT with a small signal delay is realized by taking advantage of the low resistance of the aluminum material.

  FIG. 1B shows an enlarged view of a region surrounded by a dotted line 106. As shown in FIG. 1B, the active layer 103 includes a channel formation region 107, an LDD (Lightly Doped Drain) region 108, and a drain (or source) region 109, and a gate is formed on the channel formation region 107 and the LDD region 108. An insulating film 104 is provided.

Note that the gate insulating film is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (expressed as SiO _x N _y ), or a laminated film thereof.

  In particular, since the silicon nitride film has a high ion blocking effect, it is effective to use it as a part of the gate insulating film. A silicon oxynitride film is suitable as a gate insulating film because it has the physical properties of both a silicon oxide film and a silicon nitride film.

  Further, the laminated structure is not limited to two layers, and may be a plurality of layers. For example, a laminated film (referred to as ONO film) having a three-layer structure of silicon oxide / silicon nitride / silicon oxide is suitable as the gate insulating film of the present invention because of its high reliability.

  Further, the gate electrode is laminated in the order of the tantalum layer 110 and the aluminum layer 105, and a part of the aluminum layer 105 becomes a nonporous alumina layer 111 and a part of the tantalum layer 110 becomes a tantalum oxide layer 112 by anodizing treatment. ing.

  In the above-described anodic oxidation, only the tantalum layer that does not overlap with the aluminum layer 105 and the nonporous alumina layer 111 is anodized, and as shown in FIG. In this way, a tantalum oxide layer is formed.

  Further, when forming the source / drain region, the LDD region 108 can be formed by intentionally lowering the impurity concentration using the tantalum oxide layer 112 as a mask. Accordingly, the position of the junction (source or drain junction) between the drain (or source) region 109 and the LDD region 108 is defined in a self-aligned manner by the end portion (protruding end portion) of tantalum oxide.

  The configuration of the present invention having the above-described configuration will be described in detail in the embodiments described below.

  A manufacturing process of a TFT using the present invention will be described with reference to FIGS. The invention of the present application is characterized from the formation of the gate electrode to the formation of the source / drain regions, and other parts can use known techniques. Therefore, the present invention is not limited to the manufacturing process of this embodiment.

  First, a glass substrate is prepared as the substrate 201, and a silicon oxide (silicon oxide) film is formed as a base film 202 to a thickness of 200 nm thereon. Then, an active layer 203 is formed thereon by a known means. The thickness of the active layer 203 is 10 to 100 nm (preferably 15 to 75 nm, more preferably 20 to 45 nm). (Fig. 2 (A))

  The active layer 203 may be any of a single crystal silicon film, a polycrystal silicon film (polysilicon film), and an amorphous silicon film (amorphous silicon film). It is better to use crystalline silicon.

  If a single crystal silicon film is used as described above, it is desirable to use a UNIBOND substrate using the smart cut method, a SIMOX substrate using the oxygen ion implantation method, or the like. In this case, since the silicon substrate and the base film are obtained integrally, it is not necessary to provide a base film again.

  Further, if a polycrystalline silicon film is used, it can be obtained directly or by crystallizing an amorphous silicon film. The crystallization means may be laser annealing by excimer laser light irradiation, lamp annealing by infrared or ultraviolet light irradiation, or furnace annealing using an electric furnace. Furthermore, the technique described in Japanese Patent Laid-Open No. 7-30652 by the present inventors may be used in combination.

  When the state of FIG. 2A is obtained in this way, a gate insulating film 204 made of a silicon oxynitride film is formed, and a 50 nm thick tantalum layer 205 and a 350 nm thick aluminum layer 206 are sequentially stacked. In this embodiment, an aluminum layer containing 2 wt% scandium is used as the aluminum layer 206.

  The tantalum layer 205 and the aluminum layer 206 may be formed by a vapor phase method (typically, a sputtering method). (Figure 2 (B))

  Next, the tantalum layer 205 and the aluminum layer 206 are etched by a dry etching method or a wet etching method to form a laminated pattern 207 that becomes a prototype of a later gate electrode.

  As an etching gas for dry etching, a chlorine-based gas can be used for etching an aluminum layer, and a fluorine-based gas can be used for etching a tantalum layer. It has been confirmed that when the tantalum layer is as thin as about 50 nm, the aluminum layer and the tantalum layer can be etched together with a chlorine-based gas. (Fig. 2 (C))

  Although a resist mask (not shown) is used for patterning the laminated pattern 207, adhesion is improved by covering the surface of the aluminum layer with a thin anodic oxide film before forming the resist mask.

  Next, with the resist mask left, an anodizing treatment is performed at a final voltage of 8 V in a 3% oxalic acid aqueous solution to form a porous alumina layer 208 having a thickness of 600 to 800 nm. In this solution, the tantalum layer remains unanodized and only the aluminum layer is selectively anodized. (Fig. 2 (D))

  Further, after removing the resist mask (not shown), an anodic oxidation treatment with an ultimate voltage of 80 V is performed in an ethylene glycol solution containing 3% tartaric acid. In this treatment, both the aluminum layer and the tantalum layer are anodized. (Figure 2 (E))

  Only the portion of the tantalum layer 205 in contact with the porous alumina layer 208 is anodized to form a tantalum oxide layer 209. This is because only that portion touches the electrolytic solution that has permeated the inside of the porous alumina layer 208.

  The aluminum layer 206 has a non-porous alumina layer 210 with a thickness of 100 to 120 nm formed on the surface (inside the porous alumina layer). The film thickness of the nonporous alumina layer 210 is determined by the ultimate voltage.

  Here, an SEM photograph showing the state shown in FIG. 2E is shown in FIG. FIG. 10A is an SEM photograph in which a sample experimentally reproducing the structure of FIG. 2E is enlarged 40,000 times, and shows a state in the vicinity of the porous alumina layer.

  A schematic diagram of FIG. 10A is shown in FIG. 10B, 10 is a base made of a silicon oxide film, 11 is a tantalum layer, 12 is an aluminum layer, 13 is a tantalum oxide layer, 14 is a nonporous alumina layer, and 15 is a porous alumina layer. .

  As shown in FIG. 10B, the surface of the aluminum layer 12 is covered with a nonporous alumina layer 14, and a porous alumina layer 15 is formed on the outside thereof. A tantalum oxide layer 13 is formed at the end of the tantalum layer 11 (under the porous alumina layer).

  As seen from the photograph shown in FIG. 10A, the volume of the tantalum layer expands to about twice when it is transformed into a tantalum oxide layer by anodization, and the film thickness is 2 to 4 times (typical). It seems to be about 3 times thicker.

When such a structure is obtained, the gate insulating film 204 is etched by dry etching using the gate electrode and the porous alumina layer as a mask. As an etching gas, CHF ₃ gas is used at a flow rate of 55 sccm, pressure 55 mTorr and supply power 800 W.

  Through this process, the gate insulating film 204 is etched in a self-aligned manner and processed into an island-like pattern as indicated by 211. At this time, the end portion (GI end portion) 212 of the gate insulating film remains in a shape protruding outward from the gate electrode. Further, an active layer that will later become a source / drain region is exposed.

  When this etching step is completed, the porous alumina layer 208 used as a mask is removed using an aluminum mixed acid (mixed solution of phosphoric acid, acetic acid, nitric acid, water) kept at 45 ° C.

  At this time, since the selection ratio between the porous alumina layer 208 and the tantalum oxide layer 209 is large, the tantalum oxide layer 209 is not etched. This is apparent from the SEM photograph shown in FIG.

  The SEM photograph shown in FIG. 11 shows a state in which only the porous alumina layer 15 has been removed from the state shown in FIG. From this photograph, it can be confirmed that the tantalum oxide layer remains in an eaves shape.

  When the state shown in FIG. 3A is thus obtained, the first impurity ion implantation step is performed by an ion implantation method or a plasma doping method. First, the acceleration voltage is increased to 70 to 85 keV. (Fig. 3 (B))

  Note that P (phosphorus) or As (arsenic) may be selected when an N-channel TFT (NTFT) is manufactured, and B (boron) may be selected when a P-channel TFT (PTFT) is manufactured. This embodiment will be described using phosphorus as an example.

  Since this process has a high acceleration voltage, impurity ions are implanted through the tantalum oxide layer 209 and the GI end portion 212. That is, impurities are also added under the region covered with the GI end and the like.

In this step, impurities implanted below the GI end 212 will later determine the impurity concentration of the LDD region. Therefore, it is necessary for the practitioner to set an optimum value for the dose during ion implantation so that the LDD region contains impurities having a desired concentration. In this embodiment, adjustment is made so that phosphorus is added at a concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ below the GI end portion 212.

  By performing the impurity ion implantation step as described above, the low concentration impurity regions 213 and 214 are formed.

  At this time, since the tantalum oxide layer 209 exists on the GI end portion 212, there is an advantage that damage during ion implantation does not reach the gate insulating film directly. That is, it is possible to suppress the generation of an extra trap level in the gate insulating film.

  Next, a second ion implantation process is performed at an acceleration voltage as low as 5 to 10 keV. In this step, since the acceleration voltage is low, the GI end portion 212 completely functions as a mask (the mask effect is improved over the technique described in Japanese Patent Laid-Open No. 7-13318 because there is a tantalum oxide layer).

Therefore, in this step, impurity ions are added only to regions (source or drain regions) indicated by 215 and 216. In this embodiment, adjustment is made so that phosphorus is added at a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

  At the same time, the impurity region formed in the first ion implantation step remains as it is under the GI end portion 212 to become an LDD region 217. Therefore, the junction between the source or drain regions 215 and 216 and the LDD region 217 is defined by the GI end (end of the tantalum oxide layer).

  Further, the region 218 in which no impurity is implanted in the first and second impurity ion implantation steps is an intrinsic or substantially intrinsic channel formation region that later becomes a carrier movement path.

Intrinsic refers to a completely neutral region where electrons and holes are perfectly balanced, and a substantially intrinsic region is a concentration range (1 × 10 ¹⁵ to 1 × 10 10) that allows threshold control. ¹⁷ atoms / cm ³ ) refers to a region containing an impurity imparting N-type or P-type, or a region in which the conductivity type is canceled by intentionally adding a reverse conductivity type impurity.

  When the implantation of impurity ions into the active layer is completed as described above, the impurities are activated by laser annealing, lamp annealing, or furnace annealing. At the same time, the damage at the time of ion implantation is recovered.

  Next, an interlayer insulating film 219 is formed. As the interlayer insulating film 219, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. Examples of the organic resin film include polyimide, polyamide, polyimide amide, and acrylic.

  After the interlayer insulating film 219 is formed, contact holes are formed, and the source electrode 220 and the drain electrode 221 are formed. In this embodiment, a laminated conductive layer made of titanium / aluminum / titanium is used as these electrode materials.

  Finally, hydrogen treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere, and the entire TFT is subjected to hydrogen termination. Thus, a TFT having a structure as shown in FIG. 3D is completed. Since the TFT manufactured in this manner has a tantalum layer between the gate electrode and the gate insulating film, it is possible to prevent a short circuit between the two due to the heat treatment during the manufacturing.

  Therefore, it is possible to manufacture TFTs with a very high yield, and a high yield rate can be secured even in manufacturing AMLCDs that manufacture one million or more TFTs on the same substrate. Accordingly, it is possible to reduce the manufacturing cost of the liquid crystal module and a product (electronic device) on which the liquid crystal module is mounted.

  In the first embodiment, the case where an NTFT is manufactured has been described as an example, but it goes without saying that the present invention can be applied to a PTFT. If a known CMOS technology is used, it is easy to configure a CMOS circuit in which NTFT and PTFT are complementarily combined.

  In this embodiment, FIG. 4 shows an example in which an active matrix substrate in which a drive circuit composed of a CMOS circuit and a pixel matrix circuit composed of NTFT are formed on the same substrate.

  In FIG. 4, NTFT 401 and PTFT 402 constitute a CMOS circuit 403. As described above, if a known CMOS technology is used, it can be easily realized by almost the same process as in the first embodiment.

  Further, the pixel TFT (NTFT in this embodiment) 404 constituting the pixel matrix circuit can be realized by adding some steps to the manufacturing process described in Embodiment 1.

  First, the structure of FIG. 3D is obtained according to the steps of Example 1. Next, a first planarizing film 40 is formed as shown in FIG. In this embodiment, a laminated structure of silicon nitride (50 nm) / silicon oxide (25 nm) / acryl (1 μm) is used as the first planarizing film.

  Note that since an organic resin film such as acrylic or polyimide is a solution-coated insulating film formed by a spin coating method, a thick film can be easily formed and a very flat surface can be obtained. Therefore, a film thickness of about 1 μm can be formed with high throughput, and a good flat surface can be obtained.

  Next, a black mask 41 made of a light-shielding conductive film is formed on the first planarization film 40. Prior to forming the black mask 41, the first planarizing film 40 is etched to form a recess that leaves only the lowermost silicon nitride film.

  By doing so, the drain electrode and the black mask are brought close to each other through the silicon nitride film only in the portion where the recess is formed, and the auxiliary capacitor 42 is formed there. Since silicon nitride has a high relative dielectric constant and a thin film thickness, it is easy to ensure a large capacity.

  When the auxiliary capacitor 42 is formed at the same time when the black mask 41 is formed in this way, the second planarizing film 43 is formed of 1.5 μm thick acrylic. A portion where the auxiliary capacitor 42 is formed has a large step, but such a step can be sufficiently flattened.

  Finally, contact holes are formed in the first planarization film 40 and the second planarization film 43, and a pixel electrode 44 made of a transparent conductive film (typically ITO) is formed. Thus, a pixel TFT 404 as shown in FIG. 4 can be manufactured.

  Note that an active matrix substrate for a reflective AMLCD can be manufactured by using a highly reflective conductive film as a pixel electrode, typically aluminum or a material mainly containing aluminum.

  In FIG. 4, the gate electrode of the pixel TFT has a double gate structure. However, a single gate structure or a multigate structure such as a triple gate structure may be used.

  The structure of the active matrix substrate is not limited to the structure of this embodiment. Since the feature of the present invention lies in the configuration of the gate electrode, the practitioner may determine the other configurations as appropriate.

  In this embodiment, an example in which an LDD region is formed by a process different from that in Embodiment 1 will be described with reference to FIG. Note that the configuration of the present embodiment can be used for the configuration of the second embodiment.

  First, the state shown in FIG. 2E is obtained according to the same steps as in the first embodiment. Then, the porous alumina layer 208 is selectively removed to obtain the state of FIG. In this state, the tantalum oxide layer 209 is exposed.

Next, an impurity ion implantation process using a high acceleration voltage is performed. This step is a step for forming a later LDD region as described in the first embodiment. Accordingly, the impurity concentration of the low-concentration impurity regions 501 and 502 is adjusted to be about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ .

  Note that the step shown in FIG. 3B and the step shown in FIG. 5B described in Embodiment 1 are different in the presence or absence of a gate insulating film on the source / drain region later. In this embodiment, impurity ions are implanted into the active layer by through doping through the gate insulating film.

  The advantages of through-doping are that the process is shortened (the gate insulating film etching process can be omitted) and that the active layer is not directly damaged during ion implantation.

  Next, as shown in FIG. 5C, an impurity ion implantation process is performed at a low acceleration voltage. In this step, since the region where the tantalum oxide layer 209 exists functions as a mask, the above-described low concentration impurity region remains below the region.

  As a result, a source region 503, a drain region 504, an LDD region 505, and a channel formation region 506 are formed. Also in this case, since the tantalum oxide layer 209 exists on the LDD region 505, damage at the time of ion implantation received by the GI is reduced in that portion.

  After that, the impurity is activated in the same manner as in Example 1 to form an interlayer insulating film 507, a source electrode 508, and a drain electrode 509, and finally a hydrogenation step is performed, as shown in FIG. TFT is completed.

  In this embodiment, an example in which an offset region is provided instead of the LDD region in Embodiment 1 will be described with reference to FIG.

  First, the state shown in FIG. Then, the first impurity ion implantation step shown in Embodiment 1 is not performed, and the ion implantation step with a low acceleration voltage as described with reference to FIG. 3C is performed. (Fig. 6 (A))

In this implantation step, since the tantalum oxide layer and the gate insulating film function as a mask, a source region 601 and a drain region 602 containing impurities having a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ are formed.

  In addition, the region indicated by reference numeral 603 retains an intrinsic or substantially intrinsic state since no impurity ions are added, and functions as a mere high resistance region because no gate voltage is applied. Such a region 603 is called an offset region.

  While the LDD regions shown in the first to third embodiments are effective in reducing the electric field at the drain junction, the offset region is more effective in reducing off current (current that flows when the TFT is off) or leakage current.

  Also in this case, the tantalum oxide layer 209 has an effect of reducing damage that the gate insulating film receives during ion implantation.

  Further, a configuration as shown in FIG. 6B is also possible. In FIG. 6B, the source region 604 and the drain region 605 are formed by through doping while leaving the gate insulating film on the entire surface of the active layer. In this case also, the offset region 606 can be formed by the mask function of the tantalum oxide layer 209. .

  It should be noted that this embodiment can be easily applied to the configuration of the second embodiment.

  In this embodiment, a structure when the film thickness is increased when the tantalum layer is formed will be described with reference to FIG.

  FIG. 7 (A) shows a point in time until the porous alumina layer is removed according to the steps of Example 1. In FIG. 7A, reference numeral 701 denotes a tantalum layer, and in this embodiment, the film thickness is set to 150 to 200 nm.

  Reference numeral 702 denotes a tantalum oxide layer, which is thicker than the tantalum oxide layer 702 formed with the tantalum layer 701, and therefore, a tantalum layer 703 having a thickness of several hundred nm remains below the tantalum oxide layer.

  In this embodiment, the impurity ion implantation process is performed in this state. However, since the protruding tantalum layer 703 functions almost completely as a mask regardless of the acceleration voltage, an offset region is formed therebelow. .

  In this case, damage reaching the gate insulating film 704 at the time of ion implantation can be almost completely prevented, so that an extra trap level or the like is not generated in the gate insulating film 704. Therefore, a highly reliable TFT with less deterioration can be realized.

  Note that, as shown in FIG. 7B, the same effect can be obtained even when through doping is performed with the gate insulating film 705 completely left.

  It should be noted that this embodiment can be easily applied to the configuration of the second embodiment.

  In this embodiment, an example in which an AMLCD is configured using an active matrix substrate (element formation side substrate) including the configurations shown in Embodiments 1 to 5 will be described. Here, the appearance of the AMLCD of this embodiment is shown in FIG.

  In FIG. 8A, reference numeral 801 denotes an active matrix substrate on which a pixel matrix circuit 802, a source side driver circuit 803, and a gate side driver circuit 804 are formed. The drive circuit is preferably composed of a CMOS circuit in which an N-type TFT and a P-type TFT are complementarily combined. Reference numeral 805 denotes a counter substrate.

  In the AMLCD shown in FIG. 8A, an active matrix substrate 801 and a counter substrate 805 are bonded to each other with their end surfaces aligned. However, only a portion of the counter substrate 805 is removed, and an FPC (flexible printed circuit) 806 is connected to the exposed active matrix substrate. The FPC 806 transmits an external signal into the circuit.

  Further, IC chips 807 and 808 are attached using a surface to which the FPC 806 is attached. These IC chips are configured by forming various circuits on a silicon substrate, such as a video signal processing circuit, a timing pulse generation circuit, a γ correction circuit, a memory circuit, and an arithmetic circuit. Although two pieces are attached in FIG. 8A, one piece or a plurality of pieces may be provided.

  Further, a configuration as shown in FIG. 8B, the same portions as those in FIG. 8A are denoted by the same reference numerals. Here, an example is shown in which the signal processing performed by the IC chip in FIG. 8A is performed by a logic circuit 809 formed using TFTs over the same substrate. In this case, the logic circuit 809 is also configured based on a CMOS circuit, like the drive circuits 803 and 804.

  In addition, the AMLCD of this embodiment employs a configuration (BM on TFT) in which a black mask is provided on an active matrix substrate, but in addition, a configuration in which a black mask is provided on the opposite side may be employed.

  Further, color display may be performed using a color filter, or the liquid crystal may be driven in an ECB (electric field control birefringence) mode, a GH (guest host) mode, or the like, and the color filter may not be used.

  Further, a configuration using a microlens array may be used as in the technique described in Japanese Patent Laid-Open No. 8-15686.

  The configuration of the present invention can be applied to various other electro-optical devices and semiconductor circuits besides AMLCD.

  Examples of electro-optical devices other than AMLCDs include EL (electroluminescence) display devices and image sensors.

  Further, examples of the semiconductor circuit include an arithmetic processing circuit such as a microprocessor constituted by an IC chip, and a high-frequency module (such as MMIC) that handles input / output signals of portable devices.

  As described above, the present invention can be applied to all semiconductor devices functioning by a circuit composed of insulated gate TFTs.

  The AMLCD shown in Example 6 is used as a display of various electronic devices. Note that the electronic device described in this embodiment is defined as a product on which an active matrix liquid crystal display device is mounted.

  Examples of such electronic devices include a video camera, a still camera, a projector, a projection TV, a head mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, etc.). . An example of them is shown in FIG.

  FIG. 9A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, an operation switch 2005, and an antenna 2006. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and the like.

  FIG. 9B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the audio input unit 2103, and the image receiving unit 2106.

  FIG. 9C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the image receiving unit 2203, the display device 2205, and the like.

  FIG. 9D illustrates a head mounted display which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302.

  FIG. 9E shows a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403.

  FIG. 9F illustrates a front projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to the display device 2503.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. In addition, it can also be used for electric billboards, advertising announcement displays, and the like.

The figure which shows the structure of the gate electrode vicinity of TFT. FIG. 6 shows a manufacturing process of a TFT. FIG. 6 shows a manufacturing process of a TFT. The figure which shows the structure of an active matrix substrate. FIG. 6 shows a manufacturing process of a TFT. FIG. 6 shows a manufacturing process of a TFT. The figure which shows the structure of the gate electrode vicinity of TFT. The figure which shows the structure of AMLCD. FIG. 11 illustrates a structure of an electronic device. The SEM photograph which shows the structure of the gate electrode vicinity. The SEM photograph which shows the structure of the gate electrode vicinity.

Claims (10)

A semiconductor layer provided on an SOI substrate or a SIMOX substrate;
A gate insulating film provided on the semiconductor layer;
A tantalum layer provided via the gate insulating film;
An aluminum or material layer mainly composed of aluminum provided on the tantalum layer;
The end portion of the tantalum layer protrudes outside the end portion of the aluminum or aluminum-based material layer, and the protruding end portion is provided with a tantalum oxide layer.
The tantalum layer has a thickness of 5 to 200 nm. A semiconductor layer provided on an SOI substrate or a SIMOX substrate;
A gate insulating film provided on the semiconductor layer;
A tantalum layer provided via the gate insulating film;
An aluminum or material layer mainly composed of aluminum provided on the tantalum layer;
The end portion of the tantalum layer protrudes outside the end portion of the aluminum or aluminum-based material layer, and the protruding end portion is provided with a tantalum oxide layer.
The semiconductor layer has a source region, a drain region, a channel region, and an LDD region,
The position of the junction between the source and drain regions and the LDD region is defined by the end of the tantalum oxide layer,
The tantalum layer has a thickness of 5 to 200 nm. A semiconductor layer provided on an SOI substrate or a SIMOX substrate;
A gate insulating film provided on the semiconductor layer;
A tantalum layer provided via the gate insulating film;
An aluminum or material layer mainly composed of aluminum provided on the tantalum layer;
The end portion of the tantalum layer protrudes outside the end portion of the aluminum or aluminum-based material layer, and the protruding end portion is provided with a tantalum oxide layer.
The semiconductor layer has a source region, a drain region, a channel region, and an LDD region,
The position of the junction between the source and drain regions and the LDD region is defined by the end of the tantalum oxide layer,
The gate insulating film is not provided on the source region and the drain region,
The tantalum layer has a thickness of 5 to 200 nm.   4. The semiconductor device according to claim 2, wherein the tantalum oxide layer is provided on the LDD region.   5. The semiconductor device according to claim 1, wherein the film thickness of the tantalum oxide layer is 2 to 4 times the film thickness of the tantalum layer.   6. The semiconductor device according to claim 1, wherein the semiconductor layer is made of single crystal silicon.   7. The semiconductor device according to claim 1, wherein the aluminum or the material layer containing aluminum as a main component contains scandium.   8. The semiconductor device according to claim 1, wherein end portions of the tantalum oxide layer and the gate insulating film are aligned.   9. The method according to claim 1, further comprising an interlayer insulating film including a silicon oxide film, a silicon nitride film, or a silicon oxynitride film over the aluminum or the material layer containing aluminum as a main component. Semiconductor device.   8. The semiconductor device according to claim 2, wherein the LDD region has an impurity implanted through the gate insulating film and the tantalum oxide layer.