JP4142141B2 - コンピュータ・システム - Google Patents

コンピュータ・システム Download PDF

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Publication number
JP4142141B2
JP4142141B2 JP35991697A JP35991697A JP4142141B2 JP 4142141 B2 JP4142141 B2 JP 4142141B2 JP 35991697 A JP35991697 A JP 35991697A JP 35991697 A JP35991697 A JP 35991697A JP 4142141 B2 JP4142141 B2 JP 4142141B2
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JP
Japan
Prior art keywords
burst
memory
buffer
data
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP35991697A
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English (en)
Japanese (ja)
Other versions
JPH10232826A (ja
JPH10232826A5 (enExample
Inventor
ドミニク・ポール・マッカーシー
スチュアート・ヴィクター・クイック
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
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Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP97300113A external-priority patent/EP0853283A1/en
Priority claimed from GBGB9723704.4A external-priority patent/GB9723704D0/en
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH10232826A publication Critical patent/JPH10232826A/ja
Publication of JPH10232826A5 publication Critical patent/JPH10232826A5/ja
Application granted granted Critical
Publication of JP4142141B2 publication Critical patent/JP4142141B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/28—DMA
    • G06F2213/2806—Space or buffer allocation for DMA transfers

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
JP35991697A 1997-01-09 1997-12-26 コンピュータ・システム Expired - Fee Related JP4142141B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP97300113A EP0853283A1 (en) 1997-01-09 1997-01-09 Computer system with memory controller for burst transfer
GB9723704.4 1997-11-11
GB97300113.4 1997-11-11
GBGB9723704.4A GB9723704D0 (en) 1997-11-11 1997-11-11 Computer systems

Publications (3)

Publication Number Publication Date
JPH10232826A JPH10232826A (ja) 1998-09-02
JPH10232826A5 JPH10232826A5 (enExample) 2005-06-23
JP4142141B2 true JP4142141B2 (ja) 2008-08-27

Family

ID=26147251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35991697A Expired - Fee Related JP4142141B2 (ja) 1997-01-09 1997-12-26 コンピュータ・システム

Country Status (3)

Country Link
US (2) US6321310B1 (enExample)
JP (1) JP4142141B2 (enExample)
DE (1) DE69727465T2 (enExample)

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US20030126591A1 (en) * 2001-12-21 2003-07-03 Youfeng Wu Stride-profile guided prefetching for irregular code
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US7191318B2 (en) * 2002-12-12 2007-03-13 Alacritech, Inc. Native copy instruction for file-access processor with copy-rule-based validation
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US20050063008A1 (en) * 2003-09-24 2005-03-24 Perry Lea System and method of processing image data
JP4455593B2 (ja) * 2004-06-30 2010-04-21 株式会社ルネサステクノロジ データプロセッサ
US7962731B2 (en) * 2005-10-20 2011-06-14 Qualcomm Incorporated Backing store buffer for the register save engine of a stacked register file
US7844804B2 (en) * 2005-11-10 2010-11-30 Qualcomm Incorporated Expansion of a stacked register file using shadow registers
US9201819B2 (en) 2005-12-26 2015-12-01 Socionext Inc. Command processing apparatus, method and integrated circuit apparatus
US8572302B1 (en) * 2006-10-13 2013-10-29 Marvell International Ltd. Controller for storage device with improved burst efficiency
US7617354B2 (en) * 2007-03-08 2009-11-10 Qimonda North America Corp. Abbreviated burst data transfers for semiconductor memory
KR100891508B1 (ko) * 2007-03-16 2009-04-06 삼성전자주식회사 가상 디엠에이를 포함하는 시스템
US8806461B2 (en) * 2007-06-21 2014-08-12 Microsoft Corporation Using memory usage to pinpoint sub-optimal code for gaming systems
US7730244B1 (en) * 2008-03-27 2010-06-01 Xilinx, Inc. Translation of commands in an interconnection of an embedded processor block core in an integrated circuit
US8386664B2 (en) * 2008-05-22 2013-02-26 International Business Machines Corporation Reducing runtime coherency checking with global data flow analysis
US8281295B2 (en) * 2008-05-23 2012-10-02 International Business Machines Corporation Computer analysis and runtime coherency checking
US8285670B2 (en) * 2008-07-22 2012-10-09 International Business Machines Corporation Dynamically maintaining coherency within live ranges of direct buffers
JP2010146084A (ja) * 2008-12-16 2010-07-01 Toshiba Corp キャッシュメモリ制御部を備えるデータ処理装置
US9417685B2 (en) * 2013-01-07 2016-08-16 Micron Technology, Inc. Power management
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US9965326B1 (en) * 2016-06-27 2018-05-08 Rockwell Collins, Inc. Prediction and management of multi-core computation deration
US10108374B2 (en) * 2016-07-12 2018-10-23 Nxp Usa, Inc. Memory controller for performing write transaction with stall when write buffer is full and abort when transaction spans page boundary
US10409727B2 (en) * 2017-03-31 2019-09-10 Intel Corporation System, apparatus and method for selective enabling of locality-based instruction handling
US10175912B1 (en) * 2017-07-05 2019-01-08 Google Llc Hardware double buffering using a special purpose computational unit
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Also Published As

Publication number Publication date
DE69727465T2 (de) 2004-12-23
US6321310B1 (en) 2001-11-20
JPH10232826A (ja) 1998-09-02
DE69727465D1 (de) 2004-03-11
US6336154B1 (en) 2002-01-01

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