JP4122113B2 - 高破壊耐量電界効果型トランジスタ - Google Patents
高破壊耐量電界効果型トランジスタ Download PDFInfo
- Publication number
- JP4122113B2 JP4122113B2 JP17795099A JP17795099A JP4122113B2 JP 4122113 B2 JP4122113 B2 JP 4122113B2 JP 17795099 A JP17795099 A JP 17795099A JP 17795099 A JP17795099 A JP 17795099A JP 4122113 B2 JP4122113 B2 JP 4122113B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- layer
- fixed potential
- drain
- electrode film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S370/00—Multiplex communications
- Y10S370/901—Wide area network
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17795099A JP4122113B2 (ja) | 1999-06-24 | 1999-06-24 | 高破壊耐量電界効果型トランジスタ |
| US09/595,910 US6369424B1 (en) | 1999-06-24 | 2000-06-20 | Field effect transistor having high breakdown withstand capacity |
| EP00113361A EP1063705A3 (en) | 1999-06-24 | 2000-06-23 | Field effect transistor having high breakdown withstand capacity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17795099A JP4122113B2 (ja) | 1999-06-24 | 1999-06-24 | 高破壊耐量電界効果型トランジスタ |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001007322A JP2001007322A (ja) | 2001-01-12 |
| JP2001007322A5 JP2001007322A5 (enExample) | 2005-10-27 |
| JP4122113B2 true JP4122113B2 (ja) | 2008-07-23 |
Family
ID=16039925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17795099A Expired - Lifetime JP4122113B2 (ja) | 1999-06-24 | 1999-06-24 | 高破壊耐量電界効果型トランジスタ |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6369424B1 (enExample) |
| EP (1) | EP1063705A3 (enExample) |
| JP (1) | JP4122113B2 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2381480A1 (en) | 2001-04-04 | 2011-10-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a drain layer |
| US6492679B1 (en) * | 2001-08-03 | 2002-12-10 | Semiconductor Components Industries Llc | Method for manufacturing a high voltage MOSFET device with reduced on-resistance |
| EP2259325B1 (en) * | 2002-02-20 | 2013-12-25 | Shindengen Electric Manufacturing Co., Ltd. | Transistor device |
| JP3779243B2 (ja) * | 2002-07-31 | 2006-05-24 | 富士通株式会社 | 半導体装置及びその製造方法 |
| JP4731796B2 (ja) * | 2003-03-31 | 2011-07-27 | 三洋電機株式会社 | Mosfet |
| DE102004004045B4 (de) * | 2004-01-27 | 2009-04-02 | Infineon Technologies Ag | Halbleiterbauelement mit temporärem Feldstoppbereich und Verfahren zu dessen Herstellung |
| JP5048273B2 (ja) * | 2006-05-10 | 2012-10-17 | オンセミコンダクター・トレーディング・リミテッド | 絶縁ゲート型半導体装置 |
| TWI381455B (zh) * | 2008-04-22 | 2013-01-01 | Pfc Device Co | 金氧半p-n接面二極體結構及其製作方法 |
| JP5765251B2 (ja) * | 2012-01-24 | 2015-08-19 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
| KR20130100557A (ko) * | 2012-03-02 | 2013-09-11 | 삼성전자주식회사 | 무선통신 시스템에서 메모리 클럭 주파수를 제어하는 장치 및 방법 |
| JP2016174030A (ja) | 2015-03-16 | 2016-09-29 | 株式会社東芝 | 半導体装置 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3391287A (en) | 1965-07-30 | 1968-07-02 | Westinghouse Electric Corp | Guard junctions for p-nu junction semiconductor devices |
| DK157272C (da) * | 1978-10-13 | 1990-04-30 | Int Rectifier Corp | Mosfet med hoej effekt |
| US5191396B1 (en) | 1978-10-13 | 1995-12-26 | Int Rectifier Corp | High power mosfet with low on-resistance and high breakdown voltage |
| JPS57160159A (en) | 1981-03-28 | 1982-10-02 | Toshiba Corp | High breakdown voltage planar type semiconductor device |
| JPS58100460A (ja) * | 1981-12-11 | 1983-06-15 | Hitachi Ltd | 縦形mos半導体装置 |
| US4789882A (en) | 1983-03-21 | 1988-12-06 | International Rectifier Corporation | High power MOSFET with direct connection from connection pads to underlying silicon |
| JPS61285764A (ja) * | 1985-06-12 | 1986-12-16 | Tdk Corp | 高耐圧半導体装置 |
| US5686750A (en) * | 1991-09-27 | 1997-11-11 | Koshiba & Partners | Power semiconductor device having improved reverse recovery voltage |
| US5430314A (en) * | 1992-04-23 | 1995-07-04 | Siliconix Incorporated | Power device with buffered gate shield region |
| JP2870402B2 (ja) * | 1994-03-10 | 1999-03-17 | 株式会社デンソー | 絶縁ゲート型電界効果トランジスタ |
| US5747853A (en) | 1996-08-07 | 1998-05-05 | Megamos Corporation | Semiconductor structure with controlled breakdown protection |
-
1999
- 1999-06-24 JP JP17795099A patent/JP4122113B2/ja not_active Expired - Lifetime
-
2000
- 2000-06-20 US US09/595,910 patent/US6369424B1/en not_active Expired - Fee Related
- 2000-06-23 EP EP00113361A patent/EP1063705A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP1063705A3 (en) | 2003-05-21 |
| US6369424B1 (en) | 2002-04-09 |
| JP2001007322A (ja) | 2001-01-12 |
| EP1063705A2 (en) | 2000-12-27 |
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