JP4093991B2 - Oscillator - Google Patents

Description

  The present invention relates to an oscillator used in, for example, a communication device for performing wired or wireless communication.

Conventionally, there are oscillators used in, for example, a communication device for performing wired or wireless communication.
A specific example of such an oscillator will be described with reference to FIG.
An oscillator B which is an example of a conventional oscillator has a conventionally known PLL (Phase Locked Loop) configuration, and includes a latch signal (LE), a DATA signal (DATA), and a clock signal output from the MPU 100. It is controlled by receiving (CLK) by the control unit 150 provided inside.
Specifically, the oscillator B has a reference signal (hereinafter simply referred to as “REF”) adjusted with high accuracy externally so as to be a reference for obtaining an output signal of a desired frequency from the RF output terminal 170, and the oscillator B. Detects the phase difference between the acquired REF and RF by acquiring the output signal actually output (hereinafter simply referred to as “RF”), and based on the detection result, A phase detector 130 that outputs a control command signal for controlling the frequency, a charge pump that performs processing such as inversion or non-inversion of the control command signal output from the phase detector 130 according to the phase difference, and 140 A loop filter 300 that performs a smoothing process on the control command signal output from the charge pump 140, and a control that has been subjected to the smoothing process by the loop filter. It is configured by including a voltage controlled oscillator 400 for generating an RF (output signal) of a desired frequency in accordance with a command signal.
The RF is output from the RF output terminal 170, and the REF is input from the REF input terminal 160.
The REF and the RF are signals acquired by the phase detector 130. The two signals are divided by a predetermined division ratio before being input to the phase detector 130 in advance. The frequency is divided by the frequency divider 110 (for RF) and the frequency divider 120 (for REF), and a signal having the same period is generated. Further, if the REF and RF periods are the same, the frequency dividers 110 and 120 need not be provided.
The charge pump 140 converts the output signal of the phase detector 130 into three modes of positive constant current output, negative constant current output, or no output (off) according to the phase difference of the input signal. So it can be omitted.
The frequency synthesizer IC is an example of an IC chip in which the frequency divider 110, the frequency divider 120, the phase detector 130, the charge pump 140, and the control unit 150 are configured as one integrated circuit.

The oscillator B configured as described above acquires and generates each signal at the timing shown in FIG. 4, for example.
For example, the REF input from the REF input terminal 160 is frequency-divided by the frequency divider 120 (in this case, the frequency division ratio R = 2) to become FR1, while the RF output from the voltage controlled oscillator 400 is The frequency is divided by the frequency divider 110 (in this case, the frequency division ratio N = 8) to become FN1, and the two signals (FR1 and FN1) become signals having the same period and are acquired by the phase detector 130. .
The phase detector 130 detects a mutual phase difference between the acquired two signals (FR1 and FN1), and outputs a control command signal according to the phase difference.
Further, the charge pump 140 processes the control command signal based on the output control command signal, and the processed signal CP1 is further smoothed by the loop filter 300. Finally, the voltage controlled oscillator 400 outputs an RF having a desired frequency based on the signal subjected to the smoothing process.
Here, processing of the control command signal performed by the charge pump 140 will be described. For example, as shown in FIG. 4, when the phase of FR1 is ahead of the phase of FN1, the charge pump 140 outputs CP1 as a positive constant current pulse having a pulse width corresponding to the phase difference, while FIG. As shown, when the phase of FR1 is delayed from the phase of FN1, the charge pump 140 outputs CP1 as a negative constant current pulse having a pulse width corresponding to the phase difference. Note that the output of the charge pump is released during a period of no pulse.
Therefore, the voltage controlled oscillator 400 controls the RF frequency to be a desired value according to the polarity and pulse width of the constant current pulse of CP1.
JP 2001-144607 A

By the way, in a wired or wireless communication environment that has been remarkably developed in recent years, an advanced digital modulation method has been used at a higher frequency.
Therefore, it is required to reduce as much as possible the phase noise generated by the oscillator B used for frequency conversion of the digital modulation signal when demodulating the digital modulation signal.
It is known that the phase noise generated by this oscillator increases as the frequency dividing ratio of the frequency dividers 110 and 120 increases.
As a concrete experimental result, when the RF output frequency is 6 GHz, the frequency division ratio N = 200, and the processing frequency 30 MHz in the phase detector 130, the floor level of the phase noise is about −97 dB / Hz (note that The floor level is a low frequency component of phase noise viewed from the maximum value of the RF output frequency, and is mainly the level of phase noise generated from the frequency synthesizer IC).
On the other hand, when the RF output frequency is 6 GHz, the frequency division ratio N = 6000, and the processing frequency in the phase detector 130 is 1 MHz, the floor level of the phase noise is about −84 dB / Hz.
From the experimental results, it can be seen that the phase noise increases as the frequency division ratio increases when RF is the same value.
Therefore, it is conceivable to reduce the frequency dividing ratio of the frequency divider. However, since the phase detector 130 currently has an upper limit (about 56 MHz at maximum) in the phase comparison frequency to be handled, the high frequency is handled as described above. In this case, it is difficult to suppress the phase noise because it is necessary to increase the frequency division ratio using a frequency divider.
On the other hand, Patent Document 1 discloses a technique of switching between using a digital phase comparator having a wide PLL synchronization range and an analog phase comparator having a low phase noise depending on whether the PLL is unlocked or locked. . According to this technology, it is possible to obtain a signal with low phase noise while widening the synchronization range, but there is a problem that a high-accuracy phase comparator that can realize the target phase noise must be prepared. was there.
Therefore, the present invention has been made in view of the above circumstances, and its object is to reduce phase noise without increasing the actual phase comparison frequency and without using a highly accurate device. is there.

In order to achieve the above object, the present invention inputs two signals, an output signal of an oscillation means that outputs a signal having a frequency corresponding to an input control command signal, and a reference signal obtained from the outside, and calculates the phase difference between them. A plurality of phase detectors for detecting and outputting the control command signal for controlling the output signal of the oscillating means to a desired frequency based on the phase difference, and a plurality of phase detectors output for each of the plurality of phase detectors An oscillator having a basic configuration in which a combined control command signal obtained by combining the control command signals is input to the oscillating means.
In addition to the basic configuration, the present invention includes a plurality of stabilized power supplies that respectively supply power signals to one or a plurality of the phase detectors.
Further, in addition to the basic configuration, a configuration may be considered in which a plurality of stabilized power supplies are provided and a power signal obtained by synthesizing the outputs is supplied to each of the plurality of phase detectors.
With these configurations, the synthesized control command signal obtained by synthesizing the outputs of the phase detectors is phase-compared at a frequency that is virtually proportional to the number of the phase detectors, compared to the case where one phase detector is used. This corresponds to the control signal.
On the other hand, since the phase noise of each of the phase detectors is almost random, a part of the phase noise cancels each other by their synthesis, and the phase noise in the synthesized control command signal is proportional to the number of the phase detectors. It does not increase as much as you do. In addition, since a plurality of the stabilized power supplies for supplying power to the phase detector are provided in parallel, a part of the phase noise of each power supply that is random to each other is also canceled.
For this reason, it is possible to reduce the phase noise (improve the S / N ratio) while using a (expensive) phase detector with the conventional performance (accuracy) .

  Further, in the present invention, if the plurality of phase detectors and the stabilized power supply are configured as a unit, and the plurality of units are configured to be connected in parallel, depending on a required level of phase noise. Since the unit can be added, the flexibility (general versatility) of the device configuration is increased.

According to the present invention, two signals of the output signal of the oscillating means that outputs a signal having a frequency corresponding to the input control command signal and the reference signal obtained from the outside are input to detect the phase difference between them. A plurality of phase detectors for outputting the control command signal for controlling the output signal of the oscillating means to a desired frequency based on a phase difference, and a plurality of the control command signals output for each of the plurality of phase detectors; And a plurality of stabilized power supplies for supplying power signals to one or a plurality of the phase detectors, respectively, Since the power signal composed of the output of the stabilized power supply is supplied to each of the plurality of phase detectors, the phase detector can be used while using the (expensive) phase detector with the conventional performance (accuracy). Reduce noise To improve the S / N ratio) it becomes possible.
In addition, if the plurality of phase detectors and the stabilized power supply are configured as a unit and the plurality of units are configured to be connected in parallel, the unit is added according to the required phase noise level. This increases the flexibility (general versatility) of the device configuration .

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that the present invention can be understood. The following embodiment is an example embodying the present invention, and does not limit the technical scope of the present invention.
Here, FIG. 1 is a schematic configuration diagram of an oscillator A having a first configuration for explaining the principle of the oscillator according to the present invention, FIG. 2 is a timing chart in signal processing of the oscillator A, and FIG. 4 is a timing chart in the signal processing of the oscillator B, FIG. 5 is a timing chart in the signal processing of the oscillator B, and FIG. 6 has a second configuration for explaining the principle of the oscillator according to the present invention. 7 is a schematic configuration diagram of the oscillator A1, FIG. 7 is a timing chart in the signal processing of the oscillator A1, FIG. 8 is a timing chart when the phase difference of the input signal in the signal processing of the oscillator A1 is small, and FIG. 9 is an input in the signal processing of the oscillator A1. FIG. 10 is a timing chart when the signal phase difference is large, FIG. 10 is a graph showing the spectrum of phase noise in the conventional oscillator B, and FIG. FIG. 12 is a graph showing the phase noise spectrum of an oscillator with two phase detectors in parallel, FIG. 12 is a graph showing the phase noise spectrum of an oscillator with three phase detectors in parallel, and FIG. 13 is a diagram showing four phase detectors in parallel. 14 is a graph showing the phase noise spectrum in the oscillator, FIG. 14 is a graph showing the phase noise spectrum in the oscillator in which eight phase detectors are arranged in parallel, and FIG. 15 is a schematic configuration diagram of the oscillator X1 according to the first embodiment of the present invention. 16 is a schematic configuration diagram of an oscillator X2 according to a second embodiment of the present invention, FIG. 17 is a schematic configuration diagram of an oscillator X3 according to a third embodiment of the present invention, and FIG. 18 is a fourth embodiment of the present invention. FIG. 19 is a schematic configuration diagram of an oscillator X4 according to a fifth embodiment of the present invention, FIG. 20 is a schematic configuration diagram of an oscillator X6 according to a sixth embodiment of the present invention, and FIG. Schematic diagram of a phase detector module constituting an oscillator X7 according to a seventh embodiment of the invention, FIG 22 is a schematic configuration diagram of an oscillator X7 multiple phase detector module is connected in parallel to the motherboard.

First, before describing an embodiment of an oscillator according to the present invention, a schematic configuration of an oscillator A having a first configuration for explaining the principle of the oscillator according to the present invention will be described with reference to FIG.
The oscillator A is roughly divided into integrated circuits IC1 and IC2 having functions such as a phase detector, and a voltage-controlled oscillator that generates RF (output signal) by forming a PLL by performing processing together with the IC1 and IC2. 410 and the MPU 10 for controlling the IC1 and IC2.
Here, the schematic configuration of the IC 1 will be described first.
The IC 1 inputs (acquires) the REF that has been adjusted externally with high accuracy so as to serve as a reference for obtaining an output signal of a desired frequency from the RF output terminal 170 and the RF that is actually output by the oscillator A. And RF input signals (specifically, signals FR and FN after frequency division by frequency dividers (111 and 121, 112 and 122) described later) are detected, and the detection result Based on this, a phase detector 131 for outputting a control command signal for controlling the output signal to a desired frequency, and a charge for processing the control command signal output from the phase detector 131 according to the phase difference A pump 141 is provided and is schematically configured.
The IC 1 also includes a frequency divider 111 (for RF) and a frequency divider 121 (REF) for dividing the REF and RF input (acquired) by the phase detector 131 in advance at a predetermined frequency division ratio. 2), and the frequency divider divides each of the two signals to generate two signals (FN1, FR1; see FIG. 2) having the same period.
If the REF and RF periods are the same, the frequency dividers 111 and 121 need not be provided.
Further, the IC 1 includes a charge pump 141 that outputs a positive or negative constant current pulse according to the output signal of the phase detector 131.
This can be omitted.
Note that IC2 has components having the same functions as IC1, but the first digit of the code is set to “2” to distinguish from IC1 (for example, the phase detector of IC1 is 131). In some cases, the phase detector of IC2 is 132).

The IC1 and IC2 configured as described above are controlled by the MPU 10 for controlling the IC1 and the IC2.
Specifically, the MPU 10 controls the IC1 and IC2 by transmitting the latch signal (LE), the DATA signal (DATA), and the clock signal (CLK) to the control unit 150 provided in the IC1 and IC2.
In particular, in the case of the oscillator A, by using two D-flip flop circuits 21 and 22, the latch signal is input to the control units 151 and 152 of IC1 and IC2 at different timings. The operation start timings of IC1 and IC2 are different.
Specifically, as shown in FIG. 2, the operation start timing of the frequency dividers 111 and 121 of the IC1 is one cycle in the REF waveform than the operation start timing of the frequency dividers 112 and 122 of the IC2. The advance phase is set in advance so as to be faster. (For example, the rising edge of FR1 is a phase advanced by one cycle in the waveform of REF than the rising edge of FR2.)
The D-flip flop circuits 21 and 22 are an example of phase changing means for shifting the phases of RF and REF by a predetermined amount for each phase detector (for each IC).

An operation performed by the oscillator A configured as described above will be described with reference to FIGS.
First, when the operation of the oscillator A starts, the MPU 10 sends a latch signal (LE), and the sent LE is delayed by the two D-flip flop circuits 21 and 22, respectively, and IC1 and IC2 are provided. Are input to the control units 151 and 152.
As described above, the operation start timings of IC1 and IC2 are set to be different in phase by one cycle in the REF waveform by the D-flip flop circuits 21 and 22, and first, IC1 starts the operation first. After that, the operation of IC2 starts.
Here, the operation of the IC 1 will be described first.
First, the REF input from the REF input terminal 160 is frequency-divided by the frequency divider 121 (in this case, the frequency division ratio R = 2) to become FR1, while the RF output from the voltage controlled oscillator 410 is The frequency is divided by the frequency divider 111 (in this case, the frequency division ratio N = 8) to become FN1, and the two signals (FR1 and FN1) are input to the phase detector 131 as signals having the same period. .
The phase detector 131 detects a phase difference between the two input signals (FR1 and FN1) and outputs a control command signal according to the phase difference.
Further, the charge pump 141 processes the control command signal based on the output control command signal, and the processed signal CP1 is further smoothed by the loop filter 310.

Next, the operation of IC2 will be described.
The IC2 performs the same operation as the IC1, but the operation start timing is delayed by one cycle with the REF waveform as described above.
First, the REF input from the REF input terminal 160 is frequency-divided by the frequency divider 122 (in this case, the frequency division ratio R = 2) to become FR2, while the RF output from the voltage controlled oscillator 410 is The frequency is divided by the frequency divider 112 (in this case, frequency division ratio N = 8) to become FN2, and the two signals (FR2 and FN2) are input to the phase detector 132 as signals having the same period. .
The phase detector 132 detects the phase difference between the two input signals (FR2 and FN2) and outputs a control command signal according to the phase difference.
Further, the charge pump 142 processes the control command signal based on the output control command signal, and the processed signal CP2 is further subjected to smoothing processing by the loop filter 310.

Subsequently, CP1 and CP2 output from IC1 and IC2 are input to the loop filter 310, whereby the signal waveform is smoothed and synthesized. The CP1 and CP2 will be described.
The timing at which CP1 and CP2 are input to the loop filter 310 is as shown in FIG.
As is apparent from FIG. 2, CP1 and CP2 are alternately output from IC1 and IC2 every cycle in the REF waveform and input to the loop filter 310.
In this way, the output timings of CP1 and CP2 are alternated for each cycle in the REF waveform, as described above with respect to the operation start timings of IC1 and IC2 having phase detectors 131 and 132, respectively. This is because the phase of the waveform is shifted by one cycle.
Therefore, the loop filter 310 generates a new signal CP by simply combining CP1 and CP2 that are out of phase as described above, and finally transmits the signal CP to the voltage controlled oscillator 410 that outputs RF. The voltage controlled oscillator 410 is controlled.
By the way, since the CP frequency generated by the loop filter 310 is simply a combination of CP1 and CP2, it is twice the frequency of CP1 or CP2 (in proportion to the number of phase detectors). Therefore, it can be said that the operating frequency of the phase detector as viewed from the whole oscillator A has doubled apparently. Here, the loop filter 310 synthesizes a control command signal output for each phase detector.
Therefore, when the oscillator A is composed of the same two phase detectors with the same frequency division ratio as the conventional oscillator B described above, the oscillator A is virtually twice the frequency of the oscillator B compared to the oscillator B. The phase-controlled control signal CP can be input to the voltage controlled oscillator 410.
On the other hand, since the phase noise of each of the CP1 and CP2 is almost random, a part of the phase noise is canceled out by the synthesis, and the phase noise of the synthesis control command signal VLF is proportional to the number of the plurality of phase detectors. It does not increase as much as possible, and theoretically it is only (√2) times. Therefore, the floor level of the phase noise can be lowered as compared with the oscillator B. As a result, it is possible to reduce the phase noise (improve the S / N ratio) while using the (expensive) phase detector with the conventional performance (accuracy).

The oscillator A has been shown to output the control signal CP at twice the frequency of the conventional oscillator B. For example, the number of D-flip flop circuits is three, and an integrated circuit having the same configuration as the IC 1 is used. In the case of an oscillator configured with three REF frequency dividers of 3, the control signal CP can be output at a frequency three times that of the conventional oscillator B.
Therefore, by constructing an oscillator in which the number of D-flip flop circuits, the number of integrated circuits, and the frequency division ratio of the REF frequency divider are each an integral multiple, the control signal CP is generated at a frequency that is an integral multiple of the oscillator B. Can be output.
In the above description, the case of a voltage controlled oscillator is shown as means for outputting RF. However, if the control signal output from the loop filter 310 is a current value, a current controlled oscillator may be used.

The oscillator A has a configuration in which the phase of RF and REF is shifted by a predetermined amount for each phase detector (each IC) by the D-flip flop circuits 21 and 22. You may not change.
The schematic configuration of the oscillator A1 having the second configuration for explaining the principle of the oscillator according to the present invention will be described below.
FIG. 6 is a diagram illustrating a schematic configuration of an oscillator A1 that is a mode in which the phase is not changed for each phase detector (for each IC).
The oscillator A1 is obtained by removing the MPU 10 and the two D-flip flop circuits 21 and 22 from the oscillator A. As a result, the phases of the output signals of the IC1 and IC2 are only slightly shifted due to variations in the characteristics of the IC1 and IC2.
In the oscillator A1, resistors 51 and 52 are provided on the signal paths from the IC1 and IC2 to the loop filter 310 in order to limit the current that flows when the output currents of the charge pumps 141 and 142 have opposite polarities. Is provided.
Further, filters F1 and F2 are provided for each power supply path to each of the IC1 and IC2 (that is, the phase detectors 131 and 132, respectively).
In this oscillator A1, since the phases of the output signals of the IC1 and IC2 are not shifted as in the oscillator A, the levels (pulses) of the output signals of the devices constituting the IC1 and IC2 change almost simultaneously. For this reason, when the devices share the power supply and are directly connected, a phenomenon may occur in which a large pulsed current flows through the devices all at once and the power supply voltage decreases in a pulsed manner. This voltage drop becomes pulsed noise. Therefore, the generation of the pulsed noise is prevented by providing the filters F1 and F2.
In the example shown in FIG. 6, RC low-pass filters including resistors 61 and 62 and capacitors 71 and 72 are configured as the circuits of the filters F1 and F2, respectively. However, the present invention is not limited to this. For example, an active filter such as an LC filter composed of a coil and a capacitor or a three-terminal regulator can be considered.

FIG. 7 is a timing chart in the signal processing of the oscillator A1.
As shown in FIG. 7, the waveforms of the output signals CP1 and CP2 of the charge pumps 141 and 142 are slightly delayed from the original timing shown by the broken lines.
IC (integrated circuit) is composed of digital circuits, but the delay time of the signal passing through the digital circuit is affected by random noise of semiconductor elements used in the digital circuit or random noise and fluctuation of power supply voltage. It changes randomly in a certain amount of time. Such a fluctuation (variation) in the delay time is called jitter.
The delays in the waveforms of CP1 and CP2 shown in FIG. 7 are due to jitter, and this delay changes randomly. Further, since the IC1 and IC2 are independent circuits, jitter affecting each of the CP1 and CP2 has little correlation and is random for each of the CP1 and CP2. Therefore, the jitter component in the signal synthesized by the loop filter 310 is considered to be the power sum of the jitter components of the output signals of the IC1 and IC2.
On the other hand, since the REF and the RF supplied to the IC1 and IC2 are exactly the same signal, the original phase comparison signal component (the original output signal of the IC1 and IC2 (excluding the jitter component)) is , It is considered to be a synchronized signal. For this reason, the original phase comparison signal component in the signal synthesized by the loop filter 310 is the current sum of the original phase comparison signal component in the CP1 and CP2.
When these are logarithmically expressed, the jitter component Noise in the signal synthesized by the loop filter 310 increases by Noise = 10 * log (N) according to the number N of ICs. Here, when N = 2, Noise increases by 3 dB.
In contrast, the original phase comparison signal component Signal is increased by Signal = 20 * log (N). Here, when N = 2, Signal is increased by 6 dB.
Therefore, the SN ratio (Signal / Noise) is improved by 3 dB, and the floor level of the phase noise is calculated by 3 dB.
As described above, the parallel operation of the ICs (phase detectors) makes it possible to reduce phase noise without using a highly accurate device.

The oscillator A and the oscillator A1 operate two ICs 1 and 2 in parallel. However, the present invention is not limited to this, and the same effect can be obtained by using three or more.
According to the concept described above, when N ICs (phase detectors) are operated in parallel, the floor level of the phase noise can be improved by 10 * log (N).
Actually, when an experiment was performed with N = 4 (four ICs operated in parallel) with the same configuration as in FIG. 6, according to the conventional configuration shown in FIG. 3, the floor of the phase noise was −95 dBc / Hz. The level was improved to -101dBc / Hz. In other words, it was confirmed that the phase noise was reduced by an amount corresponding to 10 * log (4) = 6 dB. The configuration of the parallel operation as shown in FIG. 6 can be easily realized by arranging a plurality of ICs on the printed circuit board. It is also possible to arrange a plurality of integrated circuit chips in an IC package and connect them in parallel by wiring. In this case, as the integrated circuit technology advances, the size of the chip decreases, so that more chips can be arranged in parallel.
For example, if 16 ICs are operated in parallel, the floor level of the phase noise can be lowered by 12 dB, 18 dB by 64, and 24 dB by 256.

10 to 14 are graphs showing an example of the spectrum of the phase noise of the oscillator (analysis result of the RF output), where the horizontal axis represents a deviation (frequency offset) from a predetermined carrier frequency, and the vertical axis represents the phase. Represents the level of noise. Of the plots represented by the four diamond-shaped markers (marker numbers 1 to 4) in the graph, the plot portion of marker number 1 (frequency offset = 10 kHz) is derived from the phase detector (131, 132, etc.). It represents the floor level of its own phase noise. Incidentally, the plot portions of marker numbers 2 to 4 represent the phase noise level of the voltage controlled oscillator 410.
Here, FIG. 10 shows the spectrum of the phase noise in the conventional oscillator B (one phase detector) shown in FIG. 3, and FIG. 11 shows the oscillator A1 (see FIG. 6) when two phase detectors are arranged in parallel. 12 shows a phase noise spectrum, FIG. 12 shows a phase noise spectrum in an oscillator when three phase detectors are arranged in parallel, FIG. 13 shows a phase noise spectrum in an oscillator when four phase detectors are arranged in parallel, and FIG. 14 shows a phase detection. It is an example of the graph showing the spectrum of the phase noise in an oscillator at the time of arranging eight units in parallel, respectively.
In the examples shown in the graphs of FIGS. 10 to 14, the floor level of the phase noise derived from the phase detector (the level at the point of 10 kHz from the carrier) is −99. 11 dBc / Hz, −103.58 dBc / Hz for two phase detectors, −105.59 dBc / Hz for three phase detectors, −107.30 dBc / Hz for four phase detectors, phase In the case of eight detectors, it is -110.00 dBc / Hz. This result also shows that the phase noise can be further reduced as the number of the phase detectors is increased.

In addition to providing the filters F1 and F2, as means for preventing pulsed noise caused by a drop in the power supply voltage, the phase of the RF and REF input for each phase detector (each IC) can be determined. A slight shift is also conceivable.
Since the width of the pulsed noise is as short as picoseconds to nanoseconds, pulse noises will not overlap each other even if the signal wiring length to each of the ICs is different by about 1 to 100 mm. Interference can be reduced, resulting in no noise correlation and reduced phase noise.

(First embodiment)
Next, the configuration of the oscillator X1 according to the first embodiment of the present invention will be described with reference to the configuration diagram of FIG. Hereinafter, the same components as those of the oscillators A and A1 described above are denoted by the same reference numerals.
Like the oscillators A and A1, the oscillator X1 includes a voltage controlled oscillator 410 (an example of an oscillating means) that outputs a signal having a frequency corresponding to an input control command signal, and an output signal of the voltage controlled oscillator 410. And the control for controlling the output signal of the voltage controlled oscillator 410 to a desired frequency based on the phase difference by inputting two signals of the reference signal (REF) obtained from the outside and detecting the phase difference. And a plurality of phase detectors 131 and 132 (integrated circuits IC1 and IC2 having command signals) for outputting a command signal. The internal configuration of IC1 and IC2 is omitted, but is the same as that of the oscillator A1.
Further, a combined control command signal VLF obtained by combining a plurality of control command signals CP 1 and CP 2 output for each of the plurality of phase detectors 131 and 132 is input to the voltage controlled oscillator 410 through the loop filter 310.
The above configuration is the same for the oscillators X2 to X7 according to second to seventh embodiments described later.
In addition to the configuration similar to that of the oscillators A and A1, the oscillator X1 has a phase noise for each of the phase detectors 131 and 132 (one phase detector) more than that of the phase detectors 131 and 132. Are provided with a plurality of stabilized power supplies 11 and 12, each supplying a sufficiently low power signal.
Here, each of IC1 and IC2 including the phase detectors 131 and 132 is set to a desired frequency by a frequency setting signal output from the start control circuit 7, and is also reset from the start control circuit 7. It is activated or reset by a signal.

  The lock detection circuits 161 and 162 are provided in a general frequency synthesizer IC. The detection method differs depending on the IC. For example, the phase difference between the two input signals FN and FR is a predetermined period (for example, five periods) continuously for a predetermined phase difference time (for example, 15 ns (nanoseconds)) or less (or When the phase angle is equal to or less than a predetermined phase angle, it is determined that the phase is synchronized, and the lock-on signal is output ON. In other cases, the lock-on signal is output OFF.

The configuration common to the above-described oscillators A and A1, that is, the configuration in which the plurality of phase detectors 131 and 132 are operated in parallel, the phase noise of the output RF signal is approximately 1 / sqrt (N) [N is the phase detection. The number of containers] is reduced. However, when the power supply for the plurality of phase detectors 131 is shared, the phase noise in the output RF signal caused by the noise voltage of the power supply is synchronized with the power supply noise in each of the plurality of phase detectors 131 and 132. Therefore, even if the plurality of phase detectors 131 and 132 are operated in parallel, they are not reduced (cancelled).
Therefore, if the stabilized power supplies 11 and 12 are provided for each of the phase detectors 131 and 132 (integrated circuits IC1 and IC2 provided) as in the oscillator X1, the noise voltage becomes the stabilized power supplies 11 and 12. Since they occur randomly, the phase noise caused by the power supply is reduced by canceling a part thereof.
According to the experiment, when the eight phase detectors (integrated circuit) are connected in parallel, all the phase detectors are provided in parallel from one DC-stabilized power source having a power supply noise of about 100 μVrms. When power was supplied to the integrated circuit), the floor level of the phase noise was improved only to -103 dBc / Hz (frequency offset = 10 kHz).
On the other hand, when the same stabilized power source is provided for each phase detector, the phase noise caused by the power source is approximately 1 / n as the number N of the phase detectors (= the number of stabilized power sources) increases. The floor level of the phase noise is reduced to -110 dBc / Hz (frequency offset = 10 kHz).
Needless to say, it is preferable to use a stabilized power source having as little phase noise as possible.

By the way, according to an experiment, a low-pass filter composed of an R-C circuit is provided between one stabilized power source and each of the phase detectors, and the noise voltage of the power source is attenuated to thereby reduce the eight phase detectors. When the devices are connected in parallel, the floor level of the phase noise can be improved to -110 dBc / Hz (frequency offset = 10 kHz).
However, the low-pass filter requires a large capacitor, which has the demerit of increasing the device size, power consumption, and cost.
Further, it is possible to reduce the phase noise by providing an ultra-stabilized power supply with extremely small phase noise and increasing the bypass capacitor for noise suppression (for example, 10 nF). For example, when eight phase detectors are connected in parallel, the phase noise can be improved to -110 dBc / Hz (frequency offset = 10 kHz). The power supply noise at this time is estimated to be about 30 nV / sqrt (Hz) [frequency offset = 10 kHz] from various experiments.
However, when it is desired to improve the phase noise by increasing the number of phase detectors, there is a limit to the noise reduction of the power supply itself. In addition, since the bypass capacitor is increased to the maximum, there is a demerit that the power supply circuit easily oscillates.
In addition, the combination of a low-pass filter and an ultra-stabilized power supply causes further demerits such as increased device size, power consumption, and cost.
In order to eliminate the above disadvantages, the above-mentioned multiple power sources are effective.

(Second embodiment)
Next, an oscillator X2, which is another embodiment (second embodiment) of multiple power sources, similar to the oscillator X1, will be described using the configuration diagram of FIG.
Similarly to the above-described oscillators A and A1, the oscillator X2 has a configuration in which a plurality of the phase detectors are connected in parallel (here, four phase detectors 131 to 134 (integrated circuits IC1 to IC4 each including each)). have. The internal configuration of IC1 to IC4 is omitted, but is the same as that of the oscillator A1.
In addition to the configuration similar to that of the oscillators A and A1, the oscillator X1 includes a phase detector 131 to each of a plurality of (two) phase detectors 131 and 132, 133 and 134. A plurality of stabilized power supplies 11 and 12 with noise reduced to such an extent that the phase noise of 134 is not deteriorated are provided.
If a general stabilized power supply is used, the noise voltage of the output signal is about 60 mV / SQRT (Hz), and the phase noise of the phase detectors 131 to 134 is not deteriorated. For this reason, even if a relatively small number of the phase detectors (for example, about 2 to 4) are connected to each of the stabilized power supplies 11 or 12, the phase noise caused by the power supply does not matter so much. .
Therefore, if a stabilized power source is provided for each relatively small number of phase detectors (every two in the example of FIG. 7) like the oscillator X2, the number of stabilized power sources can be reduced. Of course, a configuration in which a stabilized power source is provided for each of the three or four phase detectors is also conceivable.

(Third embodiment)
Next, an oscillator X3, which is another embodiment (third embodiment) having a plurality of power sources, similar to the oscillators X1 and X2, will be described with reference to the configuration diagram of FIG.
Similarly to the above-described oscillators A and A1, the oscillator X3 has a configuration in which a plurality of the phase detectors are connected in parallel (here, four phase detectors 131 to 134 (integrated circuits IC1 to IC4 each including each)). have. The internal configuration of IC1 to IC4 is omitted, but is the same as that of the oscillator A1.
Further, in addition to the same configuration as the oscillators A and A1, the oscillator X3 includes a plurality of stabilized power supplies 11 in which noise is reduced to such an extent that the phase noise of each of the phase detectors 131 to 134 is not deteriorated. 12, and a power signal obtained by synthesizing the outputs of the plurality of stabilized power supplies 11 and 12 (outputs through the resistors 61 and 62) is supplied to each of the plurality of phase detectors 131 to 134. ing.
As described above, even if power is supplied to the plurality of phase detectors 131 to 134 after the outputs of a plurality of power sources are synthesized in advance, the same effect as the oscillators X1 and X2 can be obtained.

(Fourth embodiment)
Next, an oscillator X4 according to a third embodiment of the present invention will be described using the configuration diagram of FIG. Note that
Similarly to the above-described oscillators A and A1, the oscillator X4 has a configuration in which a plurality of the phase detectors are connected in parallel (here, four phase detectors 131 to 134 (integrated circuits IC1 to IC4 each including each)). have. The internal configurations of IC1 to IC4, the input / output signals other than the reference signal (REF) for IC1 to IC4, their paths, and the devices on the paths are omitted, but the oscillator A1 and The same.
In addition to the same configuration as the oscillators A and A1, the oscillator X4 includes a high-frequency signal line 2 such as a microstrip line provided with a termination resistor 32 for preventing signal reflection. . The line 2 transmits the reference signal (REF), and branches and outputs the reference signal to each of the plurality of phase detectors 131 to 134 (IC1 to IC4 including the phase detectors 131). An example of a high-frequency signal line). The branch signal from the line 2 is output to the phase detectors 131 to 134 via capacitors 81 to 84 for cutting the DC component.

When the frequency of the reference signal (REF) is increased and the wiring length of the signal line is longer than about 2% of the wavelength of the reference signal, the wiring cannot be regarded as a lumped constant circuit and is treated as a distributed constant circuit. Need arises. That is, in order to supply the reference signal (REF) at the same level to each of the phase detectors 131 to 134 under such conditions, it is necessary to design a circuit for signal distribution by applying the concept of a distributed constant circuit. There is.
For example, if the frequency of the reference signal (REF) is 100 MHz, the wavelength of the reference signal (REF) is about 160 cm on the FR4 glass epoxy printed circuit board. Therefore, the wiring length of the signal line for transmitting the reference signal (REF) is If it exceeds 3 cm, it is necessary to design as a distributed constant circuit.
On the other hand, when the eight phase detectors are operated in parallel, the distance between the input ends of the reference signal (REF) between the phase detectors arranged farthest from each other is about 16 cm. Will have to be designed as.
Here, when the frequency of the reference signal (REF) is up to about 100 MHz, the input impedance of the reference signal (REF) in the phase detector is 300Ω or more, so this is a line having a distributed capacity of about 50Ω ( Even if connected to a high-frequency signal line), there is almost no effect.
Therefore, the reference signal (REF) is supplied to the line 2 such as a microstrip line having a distributed capacity of 50Ω, for example, and provided with the termination resistor 32 (for example, a pure resistance of 50Ω) for preventing reflected waves at the end thereof. If transmitted, the reference signal (REF) having a substantially uniform amplitude flows through the line 2 over its entire length. Therefore, if the reference signal (REF) is branched and output from the line 2 to the phase detectors 131 to 134 via the capacitors 81 to 84, the phase detectors 131 to 134 are respectively output. Thus, a signal having the same voltage amplitude can be supplied. As a result, it is easy to design without handling as a distributed constant circuit.
Since the input impedance (about 300Ω) of the phase detector is sufficiently larger than the distributed capacity (about 50Ω) of the line 2, the reference signal (REF) on the line 2 is not disturbed.

The same applies to the transmission of the output signal (RF) of the voltage controlled oscillator 410 as the transmission of the reference signal (REF).
Therefore, a configuration in which the signal transmitted through the line 2 in the oscillator X4 is replaced with the output signal (RF) of the voltage controlled oscillator 410 from the reference signal (REF) is also conceivable. Of course, it goes without saying that the input ends of the signals in the phase detectors 131 to 134 are different. In FIG. 18, symbols representing the configuration are shown in parentheses. The oscillator with the configuration replaced with the symbol in the parenthesis is hereinafter referred to as an oscillator X4 ′. In this case, the line 2 is an example of a second high-frequency signal line.
Also in this case, for example, when the frequency of the output signal (RF) of the voltage controlled oscillator 410 is 300 MHz or less, if the line 2 such as a microstrip line having a distributed capacitance of 50Ω and a termination resistance of 50Ω is used, Since the input impedance of the phase detectors 131 to 134 is sufficiently large, the RF signal on the line 2 is not disturbed.

(5th Example)
Next, an oscillator X5 according to a fifth embodiment of the present invention will be described using the configuration diagram of FIG.
The oscillator X5 includes buffer amplifiers 91 to 94 between the signal branch points of the line 2 in the oscillator X4 ′ and the capacitors 81 to 84 provided at the RF signal input terminals of the phase detectors 131 to 134, respectively. Is provided.
In the oscillator X4 ′, when the frequency of the output signal (RF) of the voltage controlled oscillator 410 becomes 1 GHz or more, the impedance of the RF signal input in the phase detectors 131 to 134 decreases and approaches 50Ω. In the configuration of ', the RF signal cannot be transmitted properly (without being disturbed).
Under such conditions, as in the oscillator X5 shown in FIG. 19, the output signal of the voltage controlled oscillator 410 (an example of the oscillation means) branched from the line 2 (an example of the second high-frequency signal line). What is necessary is just to comprise so that each may be output to each of the said phase detectors 131-134 via the buffer amplifiers 91-94 whose input impedance in the said phase detectors 131-134 will be about 300 ohms or more.
Thereby, even if the frequency of the output signal of the voltage controlled oscillator 410 becomes higher, the RF signal on the line 2 is not disturbed.

(Sixth embodiment)
Next, an oscillator X6 according to a sixth embodiment of the present invention will be described using the configuration diagram of FIG.
Similarly to the oscillators A and A1, the oscillator X6 has a configuration in which a plurality of the phase detectors are connected in parallel (here, four phase detectors 131 to 134 (integrated circuits IC1 to IC4 each including each)). have. The internal configurations of IC1 to IC4, input / output signals other than RF signals for IC1 to IC4, their paths, and devices on the paths are omitted, but are the same as those of the oscillator A1.
In addition to the same configuration as the oscillators A and A1, the output signal of the voltage controlled oscillator 410 (an example of oscillation means) is supplied to the oscillator X6 to each of the plurality of phase detectors 131 to 134. A hybrid circuit 500 is provided for distribution.
The oscillator X6 shown in FIG. 20 is provided with a multi-branch hybrid circuit 500 configured by connecting two-branch hybrid circuits 341 to 343, which are a kind of distributed capacitance circuit, in multiple stages.
By such a hybrid circuit 500, the output signal (RF) of the voltage controlled oscillator 410 is branched into two branches, four branches, eight branches,... And input to each of the plurality of phase detectors 131 to 134. , A signal having the same voltage amplitude can be supplied to each of the phase detectors 131 to 134.

(Seventh embodiment)
Next, an oscillator X7 according to a seventh embodiment of the present invention will be described with reference to the configuration diagrams of FIGS.
The oscillator X7 has a connector 35 in which a plurality of the phase detectors 131 and 132, 133 and 134 (each of which includes IC1 and IC2) and the stabilized power supply 11 or 12 constituting the oscillator X2 are modularized. It is configured as a unit, and a plurality of the units can be connected in parallel. Hereinafter, this unit is referred to as a phase detector module U.
FIG. 21 is a block diagram showing a schematic configuration of one of the phase detector modules U constituting the oscillator X7. FIG. 22 is a schematic configuration diagram of the oscillator X7 configured by connecting a plurality of the phase detector modules U to the motherboard MB in parallel.
Each of the phase detector modules U has one or a plurality of (two in the case of FIG. 21) phase detectors 131 and 132, and phase noise sufficiently lower than that of each of the phase detectors 131 and 132. One stabilized power supply 11 for supplying a power signal, and a buffer amplifier provided in each input path of the reference signal (REF) and the output signal (RF) of the voltage controlled oscillator 410 to the phase detectors 131 and 132 101 and 102 are provided.
Further, each of the phase detector modules U is detachably connected to the external motherboard MB, and the path of each input / output signal to the phase detectors 131 and 132 is externally connected. A connector 35 is provided for connection with the motherboard MB.
The motherboard MB includes a connector 35 'for connecting the phase detector module U, a reference oscillator 160a for supplying the reference signal (REF) to each of the phase detector modules U, and the phase detector. The loop filter 310 that synthesizes and smooths the control signals output from each of the modules U, and oscillates a signal having a frequency corresponding to the output signal of the loop filter 310, and the oscillation signal is recorded in the phase detector module U. The voltage controlled oscillator 410 for supplying to each is provided. The reference signal (REF) may be supplied from the outside.
With such a configuration, the phase detector module U (unit) can be added according to the required phase noise level, so that the flexibility (general versatility) of the device configuration is increased.

  The present invention can be applied to an oscillator.

The schematic block diagram of the oscillator A which has a 1st structure for demonstrating the principle of the oscillator which concerns on this invention. 4 is a timing chart in the signal processing of the oscillator A. The schematic block diagram of the conventional oscillator B. FIG. 4 is a timing chart in signal processing of the oscillator B. 4 is a timing chart in signal processing of the oscillator B. The schematic block diagram of oscillator A1 which has a 2nd structure for demonstrating the principle of the oscillator which concerns on this invention. The timing chart in the signal processing of oscillator A1. The timing chart when the phase difference of the input signal in the signal processing of oscillator A1 is small. The timing chart when the phase difference of the input signal in the signal processing of oscillator A1 is large. The graph showing the spectrum of the phase noise in the conventional oscillator B. The graph showing the spectrum of the phase noise in the oscillator which paralleled two phase detectors. The graph showing the spectrum of the phase noise in the oscillator which paralleled three phase detectors. The graph showing the spectrum of the phase noise in the oscillator which paralleled four phase detectors. The graph showing the spectrum of the phase noise in the oscillator which paralleled eight phase detectors. The schematic block diagram of the oscillator X1 which concerns on 1st Example of this invention. The schematic block diagram of the oscillator X2 which concerns on 2nd Example of this invention. The schematic block diagram of the oscillator X3 which concerns on 3rd Example of this invention. The schematic block diagram of the oscillator X4 which concerns on 4th Example of this invention. The schematic block diagram of the oscillator X5 which concerns on 5th Example of this invention. The schematic block diagram of the oscillator X6 which concerns on 6th Example of this invention. The schematic block diagram of the phase detector module which comprises the oscillator X7 which concerns on 7th Example of this invention. The schematic block diagram of the oscillator X7 with which the several phase detector module was connected in parallel with respect to the motherboard.

Explanation of symbols

A, A1, X1 to X7 ... Oscillator U ... Phase detector module IC1 to IC4 ... Integrated circuit (frequency synthesizer IC)
MB ... Motherboard 2 ... Line 7 ... Start-up control circuit 11, 12 ... Stabilized power supply 32 ... Terminating resistor 35 ... Connectors 91-94, 101, 102 ... Buffer amplifiers 111, 112, 121, 122 ... Frequency dividers 131-134 ... Phase detectors 141, 142 ... charge pump 310 ... loop filter 410 ... voltage controlled oscillator

Claims (3)

Two signals, an output signal of an oscillation means that outputs a signal having a frequency corresponding to an input control command signal and a reference signal obtained from the outside, are input, the phase difference is detected, and the oscillation is performed based on the phase difference. An oscillator comprising a phase detector for outputting the control command signal for controlling the output signal of the means to a desired frequency,
A plurality of the phase detectors, a combined control command signal obtained by combining a plurality of the control command signals output for each of the plurality of phase detectors is input to the oscillation means,
An oscillator comprising a plurality of stabilized power supplies each supplying a power signal to one or a plurality of the phase detectors.   The oscillator according to claim 1, wherein the plurality of phase detectors and the stabilized power supply are configured as a unit, and the plurality of units are configured to be connected in parallel. Two signals, an output signal of an oscillation means that outputs a signal having a frequency corresponding to an input control command signal and a reference signal obtained from the outside, are input, the phase difference is detected, and the oscillation is performed based on the phase difference. An oscillator comprising a phase detector for outputting the control command signal for controlling the output signal of the means to a desired frequency,
A plurality of the phase detectors, a combined control command signal obtained by combining a plurality of the control command signals output for each of the plurality of phase detectors is input to the oscillation means,
An oscillator comprising a plurality of stabilized power supplies, wherein a power signal obtained by combining the outputs of the plurality of stabilized power supplies is supplied to each of the plurality of phase detectors .

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