JP2001016077A - Variable multiplication ratio pll frequency multiplying circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the variable multiplication ratio PLL frequency multiplying circuit which can select a frequency multiplication ratio of a PLL, actualizes a multiplication ratio higher than that of a conventional PLL circuit, and solve the problem of the conventional PLL circuit where the maximum operating frequency of a feedback counter is restricted as the multiplication ratio is made high. SOLUTION: This circuit is equipped with a VCO 14, which has its output frequency controlled according to the control signal that a phase difference detecting circuit 11 makes a phase comparison between a reference clock signal and a feedback clock signal and outputs the signal corresponding to their phase difference, a counter 151 which inputs the output clock of the VCO, a 1st multiplexer circuit 152 which inputs multiple clocks taken out of respective stage outputs of the counter and supplies a selected signal as a feedback clock signal to the phase difference detecting circuit, a circuit 16 which generates a multiplied clock, having a frequency higher than the VCO output frequency by using the signal of the VCO, a 2nd multiplexer 17 which inputs the VCO output clock and a multiplied clock, and an N-ary counter 18 which inputs the selected output clock signal of the 2nd multiplexer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplier circuit incorporated in a semiconductor integrated circuit device, and more particularly to a variable frequency multiplier circuit of a variable variable multiplier type using a PLL (phase locked loop). For use in digital ICs, for example.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional PLL frequency multiplier (PLL circuit).

This PLL frequency multiplier circuit has a phase frequency detector (PFD) 51 and a charge pump circuit (Charge) which receives the output of the PFD.
Pump; CHP) 52, a low-pass filter (LPF) 53 having the CHP output as an input,
Voltage-controlled oscillator (Voltage
Controlled Osci11ator (VCO) 54 and a feedback counter (FB) having the VCO output as an input.
C) 55.

The frequency multiplication ratio of the PLL, that is, the ratio of the frequency fout of the output clock signal VCOout to the frequency fin of the input clock signal RefClk is defined as follows.

Fout = P ・ fin Here, P is a frequency division ratio of the FBC 55, and when the FBC 55 is composed of an n-stage binary counter, P = 2 ⁿ .

Therefore, for example, when an output clock of 160 MHz is required for an input clock of 10 MHz, P = 2 ⁿ = 16, that is, four stages of FBC55 are used.
A hex counter may be used.

Further, the characteristics of the VCO 54 require that when the control voltage Vcntl of the VCO 54 is changed from the lower limit to the upper limit, the output frequency can take a frequency range including a desired frequency. Is referred to as a PLL lock range.

[0008] The following problems are involved in the conventional PLL as described above.

In the case where the output of the PLL is used, for example, for clock input of a microprocessor, the required output frequency fout of the VCO 54 increases as the operating frequency of the microprocessor increases. On the other hand, the input frequency fin given to the PLL is desirably a low frequency in order to reduce the power consumption of the chip mounted with the PLL and to facilitate the board design.

Therefore, the PLL frequency multiplication ratio P (=
fout / fin) is desired to be large, so PL
When the FBC55 inside L is constituted by a binary counter,
The number n of stages of the binary counter becomes larger than N = 2 ⁿ .

However, when the number n of stages of the binary counter is increased, the maximum operating frequency Fmax of the FBC is increased due to signal delay.
Is low, and the output frequency fout of the VCO 54 cannot pass through the FBC 55 when the VCO 54 is running at the highest frequency. Thereby, PFD51, CHP52, LPF53
The control voltage Vcntl of the VCO 54 is varied through
This makes it impossible to control the output frequency fout of the VCO 54 so as to decrease the output frequency fout. This problem becomes more pronounced as the need to increase the output frequency fout of the VCO 54 increases.

[0012]

As described above, the conventional PLL frequency multiplication circuit has a frequency multiplication ratio P (=
When the number of stages n of the binary counter for the feedback counter is increased in order to increase fout / fin), the maximum operating frequency Fmax of the feedback counter decreases, and the operation of the VCO becomes unlockable.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention has made it possible to select a frequency multiplication ratio of a PLL, realize a higher multiplication ratio than a conventional PLL circuit, and provide a feedback counter with a higher multiplication ratio. Variable multiplication ratio PL that can solve the problem of the conventional PLL circuit that the maximum operating frequency of
It is an object to provide an L frequency multiplier.

[0014]

A first variable frequency multiplier PLL frequency multiplier of the present invention compares the phase of a reference clock signal with the phase of a feedback clock signal and outputs a control signal corresponding to the phase difference. A voltage-controlled oscillator that outputs a clock signal whose frequency is controlled according to a control signal output of the phase difference detection circuit; a feedback counter that receives an output of the voltage-controlled oscillator as an input; and each stage of the feedback counter The plurality of clock signals extracted from the output are used as inputs, and the first
A first multiplexer circuit for supplying a clock signal selected by the selection control signal to the phase difference detection circuit as a feedback clock signal, and having a frequency higher than the output frequency of the voltage controlled oscillator using the signal of the voltage controlled oscillator A multiplied clock generation circuit for generating a multiplied clock signal, a second multiplexer circuit which receives as input the output clock signal of the voltage controlled oscillator and the multiplied clock signal output from the multiplied clock generation circuit, and selects the same with a second selection control signal Wherein the frequency of the signal output from the second multiplexer circuit is variably controlled by selection control of the first multiplexer circuit and the second multiplexer circuit.

A second variable frequency multiplier PLL frequency multiplier of the present invention comprises a phase frequency comparator receiving a reference clock signal and a feedback clock signal, and a charge pump circuit receiving an output of the phase frequency comparator as an input. A voltage-controlled oscillator including a low-pass filter receiving an output of the charge pump circuit as an input, a ring oscillation circuit outputting a clock signal whose frequency is controlled by an output voltage of the low-pass filter, and an output of the voltage-controlled oscillator. And a plurality of clock signals extracted from the output of each stage of the feedback counter, and a clock signal selected by a first selection control signal is supplied to the phase frequency comparator as a feedback clock signal. From the first multiplexer circuit and each stage of the ring oscillation circuit constituting the voltage controlled oscillator A logic circuit for extracting a force to generate a multiplied clock signal having a frequency higher than the output frequency of the voltage-controlled oscillator, a second clock signal output from the voltage-controlled oscillator and a multiplied clock signal output from the logic circuit, And a second multiplexer circuit for selecting the first multiplexer circuit and the second multiplexer circuit, the frequency of a signal output from the second multiplexer circuit being variably controlled by selection control of the first multiplexer circuit and the second multiplexer circuit. It is characterized by the following.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a variable frequency multiplier PLL frequency multiplier (hereinafter referred to as a variable frequency multiplier PLL) according to a first embodiment of the present invention.

This variable multiplication ratio PLL circuit has a PFD 11
, A CHP12 having the PFD output as an input,
An LPF 13 having the P output as an input, a VCO 14 having the LPF output as an input, a feedback counter 151 having the VCO output input, and an output of each stage selected to supply a feedback clock signal to the PFD 11 as a selected output. An FBC 15 including one multiplexer (Muxl) 152; a multiplied clock generation circuit 16 for generating a multiplied clock signal having a frequency higher than the VCO output frequency using the VCO 14; a second multiplexer (Mux2) 17; An output counter (OPC) 18 to which the selected output clock signal of the second multiplexer 17 is input.

This variable multiplication ratio PLL circuit has a P
The following points are different from those of the LL circuit, and the other points are the same.

(1) The FBC 15 receives a counter 151 similar to the conventional example having the VCO output as input, and a plurality of clock signals extracted from the output of each stage (BC), and receives a first selection control signal. A first multiplexer 152 is provided for supplying the clock signal selected by SelMux1 to the PFD 11 as a feedback clock signal. That is, the first multiplexer 152 selects a position to be extracted as a feedback position clock signal from the output of each stage of the counter 151.

(2) As the multiplied clock generation circuit 16,
An output is taken out from each stage of the ring oscillation circuit constituting the VCO 14, and a multiplier having a frequency higher than the frequency fVCO of the VCO output clock signal VCOout (M times the frequency of the conventional VCO output frequency, where M is the number of stages of the VCO). A logic circuit (Logic) 16 for generating the clock signal LGCout is provided.

(3) The second multiplexer 17 has the V
The output clock signal VCOout of the CO 14 and the multiplied clock signal LGCout output from the logic circuit 16 are input and selected by the second selection control signal SelMux2.

(4) The OPC 18 is a second multiplexer.
It comprises an N-ary counter to which the output of 17 is input, and its output clock signal is used as a PLL output signal PLLout.

FIG. 2 shows an example of the configuration of the VCO 14 and the logic circuit 16 in FIG. 1. FIG. 3 shows the relationship between the operation waveform and the timing of the PLL input clock signal RefClk.

In FIG. 2, VCO 14 has a control input Vcnt
Odd stage inverter circuit whose delay time can be controlled by l
It is configured by a ring oscillation circuit in which IV1 to IV5 are connected in a ring.

The logic circuit 16 takes out outputs from each stage of the ring oscillation circuit constituting the VCO 14, inputs the outputs of two stages of different combinations to five AND circuits 21 to 25, and By inputting the output to an OR circuit 26, a multiplied clock signal LGCout having a frequency five times the frequency fVCO of the VCO output clock signal VCOout is output.
Generate

In the PLL shown in FIG. 1, the number of stages of the ring oscillation circuit constituting the VCO 14 is five, and the counter 151 of the FBC 15 is a binary counter having two stages, and the dividing ratio P =
2 ² = 4, the OPC 18 comprises a one-stage binary counter, and its frequency division ratio D = 2 ¹ = 2. Therefore, the combination of the logic of the first selection control signal SelMux1 and the logic of the second selection control signal SelMux2 makes the PLL output clock signal PLLout
Frequency fout and frequency of PLL input clock signal RefClk
The relationship of fin can take the following combinations.

(1) SelMux1 = “L”, SelMux2 =
In the case of "L" fout = fVCO / 2 = 2/2 = 1 * fin (2) In the case of SelMux1 = "H" and SelMux2 = "L" fout = fVCO / 2 = 4/2 = 2 * fin (3) When SelMux1 = "L", SelMux2 = "H" fout = fVCO * 5/2 = 2 * 5/2 = 5 * fin (4) When SelMux1 = "H", SelMux2 = "H" fout = fVCO * 5/2 = 4 * 5/2 = 10 * fin As can be seen from the above, the VCO output frequency fVCO (corresponding to the conventional VCO output frequency fout) = 2 * fin or 4
In any case of * fin, fout = 5 * fin or 1
A variable frequency multiplier PLL circuit having a high frequency frequency multiplier of 0 * fin can be realized.

According to the variable multiplication ratio PLL circuit of this embodiment, the actual number of frequency division stages of the FBC 15 is controlled by the control signal SelM.
ux1 and a logic circuit 16 for taking out a signal from the output of each stage of the VCO 14 and performing logical processing on the output. The output of the logic circuit 16 or the output of the VCO 14 is made selectable by a control signal. , The PLL output multiplication ratio can be selected, and a higher frequency multiplication ratio than the conventional PLL circuit can be realized.

In other words, even if the VCO output frequency fVCO is lower than that of the conventional PLL circuit, the PLL output frequency can be increased, and the maximum operation of the FBC 15 can be increased with the increase of the PLL circuit. The conventional problem that the frequency Fmax is restricted can be solved.

When the same PLL output frequency as that of the conventional PLL circuit is obtained, the VCO input signal frequency fin, which is the original oscillation frequency, can be reduced, thereby reducing power consumption and facilitating board design. Becomes possible.

Further, since an odd-numbered inversion logic circuit is used as an internal circuit of the VCO 14, it is possible to realize a PLL circuit having an odd multiplication ratio which is difficult to realize with a conventional PLL circuit.

Further, SSCG (Spread Spectrum Clock)
Generation), and even when fVCO / fin cannot be high (only about four times can be obtained empirically), it is possible to realize a higher frequency multiplication ratio than the conventional PLL circuit.

In this embodiment, the FBC 15 and the OP
Although C18 is constituted by a binary counter, an N-ary counter may be used in general, and the last stage of the OPC18 may be a binary counter so that the duty cycle of the output signal is set to 50%. it can.

That is, the frequency multiplier of the variable multiplier PLL circuit according to the present invention is generally expressed by the following equation.

Fout = PMM / Dfin In particular, when the FBC and the OPC are n-stage and d-stage binary counters, respectively, the frequency multiplication ratio of the PLL is expressed by the following equation.

Fout = 2 ^nd · M · fin <Second Embodiment> In the first embodiment, VC
Although the ring oscillation circuit constituting O14 has an odd-numbered stage of an inverter circuit whose delay time can be controlled by a control input, which is ring-connected, in the second embodiment, a plurality of stages of differential amplifier circuits are used. A ring oscillation circuit connected by a ring is used.

FIG. 4 shows an example in which the VCO of the variable frequency multiplier PLL circuit according to the second embodiment is taken out.

The ring oscillating circuit constituting the VCO shown in FIG. 4 has a ring connection of odd-numbered stages (five stages in this example) of a differential amplifier circuit whose delay time can be controlled by a control input.
Each stage of differential amplifier circuit operates as an inverting amplifier circuit when the previous stage output is input to the inverting input terminal (-) and the reference voltage Vref is input to the non-inverting input terminal (+).

When a VCO is formed by ring-connecting even-numbered stages of a differential amplifier circuit whose delay time can be controlled by a control input, some odd-numbered stages of differential amplifier circuits have inverting input terminals ( Input the pre-stage output to-) and operate as an inverting circuit by inputting the reference voltage to the non-inverting input terminal (+). The remaining odd-stage differential amplifier circuits are connected to the non-inverting input terminal (+) by the pre-stage. By inputting an output and inputting a reference voltage to an inverting input terminal (-) to operate as a non-inverting amplifier circuit, the circuit becomes equivalent to the VCO shown in FIG.

It should be noted that the present invention is not limited to the above-described embodiments, but includes a phase frequency comparator, a charge pump circuit, and a low-pass filter that compare the phase of a reference clock signal with the phase of a feedback clock signal and respond to the phase difference. In this case, a phase difference detection circuit that outputs a control signal may be used. In addition, a multiplied clock generation circuit that generates a multiplied clock signal having a higher frequency than the output frequency of the VCO using a signal of the VCO may be used as the logic circuit.

[0042]

As described above, the variable multiplication ratio PL of the present invention is
According to the L frequency multiplying circuit, the frequency multiplying ratio can be selected, and a higher multiplying ratio than that of the conventional PLL circuit can be realized.
The problem of the conventional PLL circuit that Fmax is restricted can be solved.

[Brief description of the drawings]

FIG. 1 shows a variable multiplication ratio P according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating an example of an LL frequency multiplier.

FIG. 2 is a circuit diagram showing an example of a configuration of a VCO and a logic circuit in FIG.

3 is a timing chart showing the relationship between the operation waveform of the circuit of FIG. 2 and the timing of a PLL input clock signal RefClk.

FIG. 4 shows a variable multiplication ratio P according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an example of a VCO of an LL frequency multiplier circuit extracted.

FIG. 5 is a block diagram showing an example of a conventional PLL circuit.

[Explanation of symbols]

11 ... Phase Frequency Detector (P)
FD), 12: Charge pump circuit (Charge Pump; CHP), 13: Low pass filter (LP)
F), 14 ... Voltage Controlled Osci11ator
VCO), 151 ... Counter, 152 ... First multiplexer (Muxl), 15 ... Feedback counter (FBC), 16 ... Multiplied clock generation circuit, 17 ... Second multiplexer (Mux2), 18 ... Output counter (Output Counter; OPC).

Claims (6)

[Claims] 1. A phase difference detection circuit that compares a phase of a reference clock signal with a phase of a feedback clock signal and outputs a control signal according to a phase difference, and a frequency is controlled according to a control signal output of the phase difference detection circuit. A voltage-controlled oscillator that outputs a clock signal, a feedback counter that receives an output of the voltage-controlled oscillator, and a plurality of clock signals extracted from each stage output of the feedback counter. A first multiplexer circuit for supplying the selected clock signal to the phase difference detection circuit as a feedback clock signal; and generating a multiplied clock signal having a frequency higher than an output frequency of the voltage controlled oscillator using the signal of the voltage controlled oscillator. A clock generator circuit, and an output clock signal of the voltage controlled oscillator and an output from the clock generator circuit. A second multiplexer circuit that receives the doubled clock signal as an input and selects the same based on a second selection control signal, and outputs from the second multiplexer circuit by selection control of the first multiplexer circuit and the second multiplexer circuit. A variable frequency multiplier PLL frequency multiplier circuit variably controlling the frequency of a signal to be generated. 2. A phase frequency comparator having a reference clock signal and a feedback clock signal as inputs, a charge pump circuit having an output of the phase frequency comparator as an input, and a low-pass circuit having an output of the charge pump circuit as an input.
A filter, a voltage-controlled oscillator including a ring oscillation circuit that outputs a clock signal whose frequency is controlled by an output voltage of the low-pass filter, a feedback counter that receives an output of the voltage-controlled oscillator as an input, and each of the feedback counter A first multiplexer circuit that receives a plurality of clock signals extracted from the stage output and supplies a clock signal selected by a first selection control signal to the phase frequency comparator as a feedback clock signal; and the voltage controlled oscillator. A logic circuit that extracts an output from each stage of the ring oscillation circuit to generate a multiplied clock signal having a frequency higher than the output frequency of the voltage-controlled oscillator, and a multiplication clock signal output from the voltage-controlled oscillator and a multiplication output from the logic circuit. A clock signal is input and a second selection control signal selects a second signal. A multiplier circuit, wherein the frequency of a signal output from the second multiplexer circuit is variably controlled by selection control of the first multiplexer circuit and the second multiplexer circuit. Multiplier circuit. 3. The variable frequency multiplier PLL frequency multiplier according to claim 1, further comprising an output counter comprising an N-ary counter to which a selected output clock signal of said second multiplexer circuit is inputted. . 4. The variable frequency multiplier PLL frequency multiplier according to claim 3, wherein the last stage of said output counter is constituted by a binary counter circuit. 5. The variable multiplication ratio PLL according to claim 2, wherein the ring oscillation circuit forming the voltage controlled oscillator is formed by connecting odd-numbered stages of inverter circuits in a ring connection.
Frequency multiplier. 6. The variable frequency multiplier PLL frequency multiplier according to claim 2, wherein the ring oscillation circuit forming the voltage controlled oscillator is formed by connecting a plurality of stages of differential amplifier circuits in a ring connection.