JP2002305444A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely detect locked state of a PLL circuit generating an output signal having phase synchronized with an input signal. SOLUTION: The PLL circuit comprises a voltage control oscillator 40, a phase detector 10, control voltage generating circuits 20 and 30, a first delay means 61 for delaying an input signal for outputting a delayed input signal, a second delay means 62 for delaying a comparison signal for outputting a delayed comparison signal, a first holding means 63 for holding the delayed in put signal in synchronism with the comparison signal, a second holding means 64 for holding the delayed comparison signal in synchronism with the input signal, a logic means 65 for outputting an instantaneous lock signal, based on the outputs from first and second holding means, and detection means 66-69 for outputting a lock detection signal upon detecting the fact that the logic means is outputting the instantaneous lock signal continuously over a specified period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (Phase Locked Loop) circuit for generating an output signal whose phase is synchronized with an input signal.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a general PLL circuit. This PLL circuit compares the phase of an input signal with the phase of a signal obtained by multiplying the frequency of an output signal of a VCO (voltage controlled oscillator) 40 by 1 / N (hereinafter, referred to as a comparison signal) to control voltage V. _C is calculated, and VCO4 is calculated using the control voltage V _C.
By controlling 0, an output signal whose phase is synchronized with the input signal is generated. Here, N is an integer of 1 or more.
When N is 1, the frequency of the input signal is equal to the frequency of the output signal, and when N is 2 or more, the frequency dividing circuit 5
By dividing the output signal by N by 0, an output signal obtained by multiplying the frequency of the input signal can be obtained.

[0003] The phase comparison between the input signal and the comparison signal is performed by the phase detector 10. The phase difference signal output from the phase detector 10 is integrated by the charge pump circuit 20 and the loop filter 30. That is, the charge pump circuit 20 supplies the current I _OUT to the loop filter 30 based on the phase difference signal output from the phase detector, thereby controlling the control voltage V for controlling the VCO 40.
_C is obtained. The loop filter 30 includes, for example, a resistor and a capacitor connected in series, and has a low-pass characteristic.

A lock detection circuit 80 detects whether the phase of the input signal and the phase of the comparison signal fall within a predetermined range, and outputs a lock detection signal according to the detection result. Detecting the locked state of the PLL circuit in this manner is performed by the PL
This is because, when the output signal of the L circuit is used as a clock signal for a CPU or the like, it is necessary to notify the CPU or the like that the clock signal has stabilized after turning on the power or after a change in the clock frequency.

However, since the input signal and the comparison signal of the PLL circuit are narrow pulse signals, the operation of detecting the lock state has been unstable in the lock detection circuit included in the conventional PLL circuit.

[0006]

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to reliably detect a lock state in a PLL circuit that generates an output signal whose phase is synchronized with an input signal.

[0007]

In order to solve the above problems, a PLL circuit according to the present invention is a PLL circuit for generating an output signal whose phase is synchronized with an input signal, wherein the frequency changes according to a control voltage. A voltage-controlled oscillator for generating an output signal, and the frequency of the output signal of the voltage-controlled oscillator being 1 / N
A phase detector that compares the phase of the comparison signal (N is an integer of 1 or more) obtained by multiplying the phase of the input signal with the phase of the input signal, and outputs a phase difference signal corresponding to the phase difference between the two. Control voltage generating means for generating a control voltage to be applied to the voltage controlled oscillator based on the phase difference signal, and first delay means for delaying the input signal for a first predetermined period and outputting a delayed input signal; Second delay means for delaying the signal for a second predetermined period to output a delay comparison signal, first holding means for holding the delay input signal in synchronization with the comparison signal, and synchronization in synchronization with the delay comparison signal A second holding means for holding the input signal, and an instantaneous lock signal indicating that the phase of the input signal and the phase of the comparison signal are within a predetermined range based on the outputs of the first and second holding means. Logic means for outputting, and the logic means generate an instantaneous lock signal. When detecting that the continuously outputs a constant period of time, PLL circuit includes a detecting means for outputting a lock detection signal indicating that the locked state.

Here, the control voltage generating means includes a charge pump circuit for supplying a current based on the phase difference signal output from the phase detector, and a control for supplying the current from the charge pump circuit and applying the current to the voltage controlled oscillator. A loop filter that generates a voltage may be included.

In addition, each of the first and second delay means includes a buffer circuit, each of the first and second holding means includes a flip-flop circuit, or the logic means includes an AND circuit having a one-side inverted input. It may be included.

Further, the detecting means calculates a logical product of a plurality of flip-flop circuits connected in series for holding an instantaneous lock signal output from the logic means in synchronization with the input signal, and output signals of the plurality of flip-flop circuits. An AND circuit may be included. This detection means may further include control means for changing the number of output signals of the plurality of flip-flop circuits for which the AND circuit takes a logical product.

According to the above arrangement, the output of the first holding means for holding the delay input signal in synchronization with the comparison signal and the output of the second holding means for holding the delay comparison signal in synchronization with the input signal are provided. The logic means outputs an instantaneous lock signal based on the output signal, and the detection means outputs a lock detection signal when the instantaneous lock signal is continuously output for a predetermined period, so that the lock state of the output signal is reliably detected. be able to.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same elements are denoted by the same reference numerals and description thereof is omitted. FIG. 1 shows a configuration of a PLL circuit according to the first embodiment of the present invention. This P
The LL circuit compares the phase of the input signal REF with the phase of a signal (hereinafter, referred to as a comparison signal) FB obtained by multiplying the frequency of the output signal of the VCO (voltage controlled oscillator) 40 by 1 / N to control voltage. V _C is obtained, and VCO 4 is calculated using the control voltage V _C.
By controlling 0, an output signal whose phase is synchronized with the input signal is generated. Here, N is an integer of 1 or more.
When N is 1, the frequency of the input signal is equal to the frequency of the output signal, and when N is 2 or more, an output signal obtained by multiplying the frequency of the input signal is obtained. As the input signal, for example, a reference clock signal is used.

The VCO 40 oscillates at a frequency according to the applied control voltage V _C , and outputs a signal obtained by the oscillation as an output signal. The frequency dividing circuit 50 divides the frequency of the output signal of the VCO 40 by 1 / N to generate a comparison signal FB. In a case where the frequency of the input signal is always equal to the frequency of the output signal, the frequency dividing circuit 50
Is unnecessary. The phase comparator 10 compares the phase of the input signal REF with the phase of the comparison signal FB, and outputs a phase difference signal according to the phase difference. The phase difference signal output from the phase detector 10 is integrated by the charge pump circuit 20 and the loop filter 30.

The charge pump circuit 20 includes the phase detector 1
The current I _OUT is supplied to the loop filter 30 on the basis of the phase difference signal output from 0. The loop filter 30 is
It has a low-pass characteristic including a resistor and a capacitor connected in series. In the loop filter 30, by converting the current I _OUT supplied from the charge pump circuit 20 into a voltage, a control voltage V _C for controlling the VCO 40 is obtained.

On the other hand, the input signal REF and the comparison signal FB
Is also supplied to the lock detection circuit 60. The lock detection circuit 60 includes a buffer circuit 61 for delaying the input signal REF and a buffer circuit 62 for delaying the comparison signal FB. The lock detection circuit 60
Includes two flip-flop circuits 63 and 64 and a one-side inverted input AND circuit 65.

In the flip-flop circuit 63, the delayed input signal REF is input to the data input terminal D, and the comparison signal FB is input to the clock input terminal CK. On the other hand, in the flip-flop circuit 64, the input signal REF is input to the data input terminal D, and the delayed comparison signal FB is input to the clock input terminal CK. Therefore, when the phase of the comparison signal FB is within a predetermined range with respect to the phase of the input signal REF, the output signal Q1 of the flip-flop circuit 63 becomes low level, and the output signal Q2 of the flip-flop circuit 64 becomes High level. As a result, the instantaneous lock signal DET output from the one-side inverted input AND circuit 65 becomes high level. Thus, the positional relationship between the input signal REF and the comparison signal FB is detected.

M-stage flip-flop circuits 66 to 68 are connected in series to the output of the AND circuit 65 having one-side inverted input (M is a natural number). Since the input signal REF is supplied to the clock input terminal CK of these flip-flop circuits, the flip-flop circuit 68 of the M-th stage starts when the instantaneous lock signal DET becomes high level.
By the time the output of
A period corresponding to M periods of F is required.

The AND circuit 69 outputs the lock detection signal LOCK by calculating the logical product of the signals output from the M-stage flip-flop circuits 66 to 68. Therefore, only when the lock state of the PLL circuit continues for a period corresponding to M cycles of the input signal REF, the lock detection signal L
OCK is activated.

The operation of the PLL circuit according to this embodiment will be described with reference to FIGS. FIG. 2 is a timing chart showing the timing of each signal in the PLL circuit according to the present embodiment.

As shown in FIG. 2, immediately after the power is turned on, the comparison signal FB has a leading phase with respect to the input signal REF, and the output signal Q of the flip-flop circuits 63 and 64
1 and Q2 are at low level. When the phase of the comparison signal FB falls within a predetermined range with respect to the phase of the input signal REF, the output signal Q1 of the flip-flop 63 goes high, and the instantaneous lock signal DET also goes high.

In the M-stage flip-flop circuits 66 to 68, when M clocks are applied after the instantaneous lock signal DET goes high, the outputs of all flip-flop circuits go high, and AND Circuit 69
Is also at a high level.

Next, a second embodiment of the present invention will be described.
This will be described with reference to FIG. In the present embodiment,
As shown in FIG. 3, M-stage flip-flop circuits 66 to
A control circuit 71 is provided between 68 and the AND circuit 69. The control circuit 71 changes the number of output signals of the flip-flop circuit to be ANDed in the AND circuit 69 according to the applied control signal. That is, the output signal of the K-stage flip-flop circuit is selected from the output signals of the M-stage flip-flop circuits 66 to 68,
The signal is applied to the D circuit 69 (K is a natural number, K ≦ M), and a high-level signal is applied to the AND circuit 69 instead of the output signal of the flip-flop circuit at the subsequent stage.

Thus, the period from when the instantaneous lock signal DET goes high to when the lock detection signal LOCK goes high can be programmably changed by the control signal. This makes it possible to change the period required to determine the locked state according to the stability of the clock and the power supply at the system level.

[0024]

As described above, according to the present invention, a locked state can be reliably detected in a PLL circuit that generates an output signal whose phase is synchronized with an input signal.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing timings of respective signals in the PLL circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a PLL circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a conventional PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Phase detector 20 Charge pump circuit 30 Loop filter 40 VCO 50 Divider circuit 60, 70 Lock detection circuit 61, 62 Buffer circuit 63, 64, 66-68 Flip-flop circuit 65, 69 AND circuit 71 Control circuit

Claims (7)

[Claims] 1. A PLL circuit that generates an output signal whose phase is synchronized with an input signal, comprising: a voltage-controlled oscillator that generates an output signal whose frequency changes according to a control voltage; A phase detector that compares a phase of a comparison signal (N is an integer of 1 or more) obtained by multiplying 1 / N with a phase of the input signal, and outputs a phase difference signal according to a phase difference between them; Control voltage generating means for generating a control voltage to be applied to the voltage controlled oscillator based on the phase difference signal output from the detector; and a second delaying the input signal for a first predetermined period to output a delayed input signal. 1 delay means, second delay means for delaying the comparison signal for a second predetermined period to output a delay comparison signal, and first holding for holding the delay input signal in synchronization with the comparison signal Means and before A second holding unit that holds the input signal in synchronization with the delay comparison signal, and a phase of the input signal and a phase of the comparison signal are determined based on outputs of the first and second holding units. Logic means for outputting an instantaneous lock signal indicating that the signal is within the range; and when the logic means detects that the instantaneous lock signal is continuously output for a predetermined period, the PLL circuit is in a locked state. And a detection unit that outputs a lock detection signal indicating that the lock state has been reached. 2. The charge pump circuit, wherein the control voltage generating means supplies a current based on a phase difference signal output from the phase detector, and a current supplied from the charge pump circuit to the voltage controlled oscillator. The PLL circuit according to claim 1, further comprising: a loop filter that generates a control voltage to be applied. 3. The PLL circuit according to claim 1, wherein each of said first and second delay means includes a buffer circuit. 4. The apparatus according to claim 1, wherein each of said first and second holding means includes a flip-flop circuit.
4. The PLL circuit according to claim 3. 5. The PLL circuit according to claim 1, wherein said logic means includes an AND circuit having a one-side inverted input. 6. A plurality of serially connected flip-flop circuits for holding an instantaneous lock signal output by the logic means in synchronization with the input signal, and an output signal of the plurality of flip-flop circuits. And an AND circuit that takes a logical product of
6. The PLL circuit according to any one of 5. 7. The PLL circuit according to claim 6, wherein said detection means further includes control means for changing the number of output signals of said plurality of flip-flop circuits for which said AND circuit takes a logical product.