CN1945977B - Lock detecting circuit and method for phase lock loop system - Google Patents
Lock detecting circuit and method for phase lock loop system Download PDFInfo
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- CN1945977B CN1945977B CN2006101500255A CN200610150025A CN1945977B CN 1945977 B CN1945977 B CN 1945977B CN 2006101500255 A CN2006101500255 A CN 2006101500255A CN 200610150025 A CN200610150025 A CN 200610150025A CN 1945977 B CN1945977 B CN 1945977B
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Abstract
This invention relates to a locking detection circuit and a method for phase-locking loop system including a delay unit and an established logic unit, in which, the delay unit inputs phase error signals of the system to generate a current phase error signal and generate at least one delay phase error signal based on it, the established logic unit generates and sets up an un-locked instruction signal based on the current phase error signal and the delayed phase error signal, if said un-locked instruction signal is not established in a specific number of the pulse time, then a loop lock instruction signal is generated, which can adjust the tolerance to the error of static phase difference flexibly.
Description
Technical field
The invention relates to a kind of circuit for detecting and method of circuit state, particularly about a kind of locking detecting (lock detecting) circuit and method that is used for phase-locked loop (phase lock loop or PLL) system.
Background technology
Fig. 1 shows the system block diagrams of the typical phase locked loop system 100 of prior art, and it comprises preceding frequency divider (pre-divider) 110, phase frequency detector (phasefrequency detector or PFD) 120, charge pump (charge pump) 130, low pass filter (low pass filter) 140, voltage controlled oscillator (voltage controlledoscillator or VCO) 150, back frequency divider (post-divider) 160 and feedback divider (feedback divider) 170.Preceding frequency divider 110 receives input clock signal P
IN, and export reference clock signal RCLK behind the frequency division to phase frequency detector 120.Phase frequency detector 120 is connected to feedback divider 170, to receive VCO frequency division clock signal VCLK.Phase frequency detector 120 has two outputs, and last clock signal UP of output and following clock signal DOWN are to charge pump 130 respectively.Charge pump 130 is connected to low pass filter 140 and voltage controlled oscillator 150.Voltage controlled oscillator 150 output one VCO clock signal VCO_CLOCK also are connected to back frequency divider 160.The output of back frequency divider 160 is exported the output clock signal P of this phase locked loop system 100
OUTAnd be connected to feedback divider 170.Feedback divider 170 becomes VCO frequency division clock signal VCLK and is fed to phase frequency detector 120 after with its frequency division.
When phase locked loop system 100 was in stable state (steady state), reference clock signal RCLK that phase frequency detector 120 receives and the phase difference of VCO frequency division clock signal VCLK and difference on the frequency should be near zero.At this moment, the phase-locked loop is called and is in " locking " state the phase-locked loop is locked in other words.Need can arrive aforesaid stable state one period time of delay after the phase-locked loop is initial.Before arriving stable state, the output clock signal P of phase locked loop system 100
OUTBe to be in uncertain state and can't to use.Whether historical facts or anecdotes is engaged in going up the normal locking circuit for detecting (phase detectingcircuit) of a phase locked loop system that uses and is in the lock state with the detecting phase locked loop system.The locking circuit for detecting can be exempted phase locked loop system output clock signal P
OUTFrequency do to measure to simplify the detecting flow process.
Fig. 2 A shows the circuit diagram of a tradition locking circuit for detecting 200, and it comprises XOR gate (exclusive OR gate or XOR gate) 210 and clicks counter (one-shootcounter) 220.XOR gate 210 receives the last clock signal UP and the following clock signal DOWN of aforementioned phase locked loop system 100, and output phase error signal PH
ERRTo the replacement end of clicking counter 220 (reset terminal) T
RESETIn addition, the reference clock signal RCLK in the aforementioned phase locked loop system 100 is connected to the clock pulse input T that clicks counter 220
CLKClick the output of counter 220 and then export a loop lock indication signal LOCK.When detecting lock-out state, loop lock indication signal LOCK exports high level, and in the end T that resets
RESETBe maintained at high level before receiving next reset signal.The function of locking circuit for detecting 200 is to detect the static phase poor (static phase error) of a phase locked loop system.So-called static phase difference is meant the phase difference as the input end signal of the phase frequency detector 120 among Fig. 1.Ideally, when phase locked loop system was in the lock state, the static phase difference should be zero.On the practice, when static phase difference during less than a certain particular value, relative phase locked loop system just can be regarded as being in the lock state.
Shown in Fig. 2 A, last clock signal UP and following clock signal DOWN are through the operation result PH of XOR gate 210
ERRCan represent the static phase extent.Click counter 220 in clock pulse input T
CLKIf the reference clock signal RCLK that receives continues input in phase locked loop system 100 initial backs, enters the back no any PH at the RCLK of some clock pulse
ERRDo the action of replacement to clicking counter 220, then click the output of counter 220 and will export high level, and in the end T that resets
RESETReceive from PH
ERRNext reset signal before be maintained at high level.
As previously mentioned, locking circuit for detecting 200 is by judging the degree of its static phase difference to " logic XOR " operation result of going up clock signal UP and following clock signal DOWN in the phase locked loop system 100.Fig. 2 B to Fig. 2 D shows that each figure all comprises clock signal UP, time clock signal DOWN and relative phase error signal PH corresponding to the coherent signal sequential chart of static phase difference in various degree
ERRWaveform.Under the perfect condition, when phase locked loop system 100 was in perfect lock-out state, frequency and the phase place of last clock signal UP and following clock signal DOWN were identical, and the waveform of its phase difference will be maintained at low level always, shown in Fig. 2 B.During actual operation, last clock signal UP and the frequency of following clock signal DOWN or be positioned at difference to some extent of different time mutually, shown in Fig. 2 C, the not in-phase component of last clock signal UP and following clock signal DOWN produces high level through XOR gate 210 backs, and the duration of this high level is the phase place extent.When the frequency of last clock signal UP and following clock signal DOWN or phase place difference but when not being very remarkable to some extent, shown in Fig. 2 D, though clock signal UP and following clock signal DOWN still have a little difference on this moment, phase locked loop system can be considered locked on the practice.The locking circuit for detecting on historical facts or anecdotes border must detect the unlocked state shown in Fig. 2 C, and relative the ignored phase difference of mechanism eliminating shown in Fig. 2 D also must be arranged.
Tradition shown in Fig. 2 A locking circuit for detecting 200 is often because of element matching problem, process variation or variation of temperature, even and cause relative phase locked loop system 100 locked, but that locking circuit for detecting 200 still detects the static phase of can not ignore is poor.In other words, the phase error degrees of tolerance of tradition locking circuit for detecting 200 usually is not inconsistent actual demand.And the phase error degrees of tolerance of the locking of the traditional type shown in Fig. 2 A circuit for detecting 200 can't elasticity change, and this shortcoming makes traditional type locking circuit for detecting 200 can't look the suitable phase error degrees of tolerance of actual needs adjustment to meet the demand of different application.In view of the shortcoming of above-mentioned tradition locking circuit for detecting, it is necessary to propose on a kind of performance not can be with element matching problem, process variation or variation of temperature unstable and use and go up than the flexible locking circuit for detecting of tool.
Summary of the invention
For improving the tradition disappearance, the present invention promptly proposes a kind of locking circuit for detecting and method of phase locked loop system, and its performance can be because of the matching of element, the variability or the variation of temperature instability of processing procedure.
And the present invention proposes a kind of locking circuit for detecting and method of phase locked loop system in addition, and it is for the phase error degrees of tolerance elasticity adjustment in addition of static phase difference.
In view of this, the present invention proposes the locking circuit for detecting of a kind of phase locked loop system (PLL), mainly comprises delay cell, selector and establishes logical block.Delay cell is in order to the phase error signal of input phase locked loop system, and this phase error signal is postponed producing a present phase error signal, and this present phase error signal of foundation produces at least one delayed phase error signal.Selector in order to according to an error degrees of tolerance control signal, is selected one from this at least one delayed phase error signal that inputs to this selector; Establish logical block then according to the state of phase error signal and selected this delayed phase error signal at present, to produce a non-locking index signal.Wherein, this error degrees of tolerance control signal is adjusted the tolerance of this phase error signal in order to control.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned selector is a multiplexer.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned delay cell are a shift register (shift register), in order to import the phase error signal of this phase locked loop system, to produce a plurality of above-mentioned delayed phase error signals.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned shift register comprises the trigger of a plurality of series connection, a plurality of a plurality of these delayed phase error signals of trigger output that should connect.
The locking circuit for detecting of phase locked loop system of the present invention, the clock pulse input of wherein above-mentioned shift register or trigger receive VCO (VCO) clock signal of this phase locked loop system.
The present invention proposes the locking circuit for detecting of a kind of phase locked loop system (PLL) in addition, mainly comprises: input time-pulse error detecting logical block, sampling logical block and counting logical block.Wherein, input time-pulse error detecting logical block according to this phase locked loop system one with reference to clock signal and a VCO frequency division clock signal to produce a phase error signal.The sampling logical block then postpones this phase error signal to produce a present phase error signal, this present phase error signal of foundation is to produce at least one delayed phase error signal, this sampling logical block comprises a selector, in order to according to an error degrees of tolerance control signal, from at least one delayed phase error signal that inputs to this selector, select one, and the logical block of should sampling is according to the state of this present phase error signal and selected delayed phase error signal, to produce a non-locking index signal.The counting logical block then is in order to count this with reference to clock signal, if this non-locking index signal is not established in the burst length in this given number with reference to clock signal, then to produce and establish a loop lock indication signal; Wherein, this error degrees of tolerance control signal is adjusted the tolerance of this phase error signal in order to control.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned sampling logical block comprises: a delay cell, in order to import this phase error signal to produce this at least one delayed phase error signal; Reach one and establish logical block, it is according to the state of this present phase error signal and selected this delayed phase error signal, to produce this non-locking index signal.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned selector is a multiplexer.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned delay cell are a shift register (shift register), in order to import the phase error signal of this phase locked loop system, to produce a plurality of above-mentioned delayed phase error signals.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned shift register comprises the trigger of a plurality of series connection, a plurality of a plurality of these delayed phase error signals of trigger output that should connect.
The locking circuit for detecting of phase locked loop system of the present invention, the clock pulse input of wherein above-mentioned shift register or trigger receive VCO (VCO) clock signal of this phase locked loop system.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned counting logical block are to click (one-shoot) counter, and it counts this with reference to clock signal, when this non-locking index signal is established, then reset (reset) this click counter.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned input time-pulse error detecting logical block comprises: clock pulse on (UP)/following clock pulse (DOWN) signal generating circuit, its according to the reference clock signal of this phase locked loop system and VCO frequency division clock signal to produce on one clock signal and clock signal once; And an XOR (exclusive OR) gate, input should be gone up clock signal, this time clock signal, to produce this phase error signal.
The locking circuit for detecting of phase locked loop system of the present invention, wherein above-mentioned clock pulse (UP)/following clock pulse (DOWN) signal generating circuit of going up comprises the trigger of two parallel connections, the clock pulse input of described trigger receives this respectively with reference to clock signal, this VCO frequency division clock signal, the replacement end of described trigger all is controlled by this non-locking index signal, the data input pin of described trigger is connected in its oppisite phase data output separately, and the noninverting data output end of described trigger all is connected in the input of this XOR (exclusive OR) gate.
A kind of locking method for detecting of phase locked loop system is proposed in addition according to the present invention.At first, according to the reference clock signal and the VCO frequency division clock signal of phase locked loop system, to produce a phase error signal; Phase error signal is postponed to produce a present phase error signal, this present phase error signal of foundation is to produce at least one delayed phase error signal more again; Select one of them of this at least one delayed phase error signal again according to an error degrees of tolerance control signal.Then, according to the state of present phase error signal and selected delayed phase error signal, to produce and to establish a non-locking index signal.At last, counting if the non-locking index signal is not established in the burst length in the given number of reference clock signal, then produces and establishes a loop lock indication signal with reference to clock signal; Wherein, this error degrees of tolerance control signal is adjusted the tolerance of this phase error signal in order to control.
The locking method for detecting of phase locked loop system of the present invention, wherein the generation step of above-mentioned at least one delayed phase error signal is that this phase error signal is carried out shift LD (shift registering), to produce a plurality of above-mentioned delayed phase error signals.
The locking method for detecting of phase locked loop system of the present invention in the generation step of wherein above-mentioned non-locking index signal, when this present phase error signal and selected delayed phase error signal are when establishing, then produces this non-locking index signal.
The locking circuit for detecting and the method for phase locked loop system of the present invention, it is for the phase error degrees of tolerance elasticity adjustment in addition of static phase difference.
Description of drawings
Fig. 1 shows the system block diagrams of the typical phase-locked loop of prior art.
Fig. 2 A shows the circuit diagram of a tradition locking circuit for detecting.
Fig. 2 B to Fig. 2 D shows the sequential chart that concerns of the input clock pulse of tradition locking circuit for detecting and output phase error.
Fig. 3 shows the schematic diagram according to the locking circuit for detecting of one embodiment of the invention.
Fig. 4 shows the built-in system calcspar according to the locking circuit for detecting of the embodiment of the invention.
The logical circuitry of the embodiment of the input time-pulse error detecting logical block of Fig. 5 displayed map 4.
The logical circuitry of the embodiment of the input sample logical block of Fig. 6 A displayed map 4.
The main signal sequence graph of a relation of Fig. 6 B displayed map 6A sampling logical block.
Another main signal sequence graph of a relation of Fig. 6 C displayed map 6A sampling logical block.
Fig. 7 shows the flow chart of the locking method for detecting of the embodiment of the invention.
Embodiment
It is the state of presentation logic " 1 " that the so-called logic of this specification (comprising claims) is established (logically asserted) state, and it can be high level state in the positive logic system (positive logic system) or the low level state in the negative logic system (negative logic system).One logical signal is established (asserted) and represents that this logical signal is set as the state of logical one.
Fig. 3 shows the schematic diagram according to the locking circuit for detecting 300 of one embodiment of the invention.Basically, whether locking circuit for detecting 300 is the typical phase locked loop systems 100 (but not as limit) that are connected to as shown in Figure 1, be in the lock state in order to detecting phase locked loop system 100.Particularly, locking circuit for detecting 300 receives as the reference clock signal RCLK in the typical phase locked loop system 100 of Fig. 1, VCO frequency division clock signal VCLK and VCO clock signal VCO_CLOCK.So long as frequency is than the input clock signal P of phase locked loop system 100
INBig VCO clock signal VCO_CLOCK all goes for embodiments of the invention, and the VCO clock signal VCO_CLOCK between between 500 megahertz to 1 gigahertzs is better.In addition, locking circuit for detecting 300 outputs one loop lock indication signal LOCK is in order to the state of indication phase locked loop system 100.Judge that when locking circuit for detecting 300 phase locked loop system 100 enters lock-out state, then establish this loop lock indication signal LOCK.On the other hand, locking circuit for detecting 300 also receives a plurality of error degrees of tolerance control signal MUX_CTRLs adjust the static phase difference with control tolerance simultaneously.Suppose that locking circuit for detecting 300 receives N error degrees of tolerance control signal MUX_CTRLs, then can select 2
NPlant error degrees of tolerance for the static phase difference.The user can be according to the demand of total system, and the selection that sees through error degrees of tolerance control signal MUX_CTRLs is used comparatively strict or comparatively loose static phase mistake difference degrees of tolerance with decision to total system.Subsequent embodiment will be described further the details of error degrees of tolerance control signal.
According to another embodiment of the present invention, the locking circuit for detecting 300 of Fig. 3 can also be connected to respectively as last clock signal UP in the typical phase locked loop system 100 of Fig. 1 and following clock signal DOWN, to replace above-mentioned reference clock signal RCLK and VCO frequency division clock signal VCLK.
Fig. 4 shows the built-in system calcspar according to the locking circuit for detecting 300 of the embodiment of the invention, and it comprises input time-pulse error detecting logical block 310, sampling logical block 320 and clicks counting logical block 330.Input time-pulse error detecting logical block 310 receives the reference clock signal RCLK and the VCO frequency division clock signal VCLK of phase locked loop system 100, and output is with reference to the phase error signal PH of clock signal RCLK and VCO frequency division clock signal VCLK
ERRTo the logical block 320 of sampling, this phase error signal PH
ERRPromptly represent the static phase of aforementioned phase locked loop system 100 poor.The input time-pulse error detecting logical block 310 and the logical block 320 of sampling certainly receive a non-locking index signal UNLOCK.
Sampling logical block 320 receives the phase error signal PH of input time-pulse error detecting logical block 310 as previously mentioned
ERRIn addition, sampling logical block 320 also receives the VCO clock signal VCO_CLOCK of phase locked loop system 100, and it is the output signal of voltage controlled oscillator 150 in the phase locked loop system 100; The aforesaid non-locking index signal UNLOCK of sampling logical block 320 outputs is to importing time-pulse error detecting logical block 310 and clicking counting logical block 330.Sampling logical block 320 also receives aforesaid a plurality of error degrees of tolerance control signal MUX_CTRLs simultaneously.
Click that counting logical block 330 receives the reference clock signal RCLK of phase locked loop systems 100 and from the non-locking index signal UNLOCK of sampling logical block 320.Click counting logical block 330 output one loop lock indication signal LOCK, and enter in phase locked loop system 100 and to establish this loop lock indication signal LOCK in the lock-out state.If non-locking index signal UNLOCK was not established in the time of reference clock signal RCLK given number pulse, then lock indication signal LOCK in loop will be established to represent that this phase locked loop system is in the lock state.
The logical circuitry of input time-pulse error detecting logical block 310 embodiment of Fig. 5 displayed map 4, it comprises first trigger (flip-flop) 312, second trigger 314 and XOR gate 316 in parallel.The clock pulse input CLK of first trigger 312 receives the reference clock signal RCLK of phase locked loop system 100.The data input pin D of first trigger 312 is connected to the oppisite phase data output Q ' of itself.The noninverting data output end Q of first trigger 312 is connected to an input of XOR gate 316.The clock pulse input CLK of second trigger 314 receives the VCO frequency division clock signal VCLK of phase locked loop system 100.The data input pin D of second trigger 314 is connected to the oppisite phase data output Q ' of itself.The noninverting data output end Q of second trigger 314 is connected to another input of XOR gate 316.The replacement end nReset of first trigger 312 and second trigger 314 electrically connects and receives the non-locking index signal UNLOCK from sampling logical block 320 mutually.The output output of XOR gate 316 is with reference to the phase error signal PH of clock signal RCLK and VCO frequency division clock signal VCLK
ERRInput time-pulse error shown in Figure 5 detecting logical block 310 be an illustration only, and other that be familiar with that the present technique personnel ought can be traditional are imported time-pulse error circuit for detecting and replaced.
The logical circuitry of sampling logical block 320 embodiment of Fig. 6 A displayed map 4, it comprises a plurality of triggers (3220-322M), multiplexer 324 and logical AND gate (ANDgate) 326.Aforementioned a plurality of error degrees of tolerance control signal MUX_CTRLs is connected to the signal selection wire of multiplexer 324.If the number of aforementioned a plurality of error degrees of tolerance control signal MUX_CTRLs is N, then multiplexer 324 can see through N bars selection wire from 2
NSelect one as output in the individual input.The output of multiplexer 324 is connected to an input of logical AND gate 326.The output of logical AND gate 326 is in order to export aforesaid non-locking index signal UNLOCK.The data input pin D receiving phase error signal PH of trigger 3220
ERRIn a plurality of triggers (3220-322M), the Q output of prime trigger is connected to the data input pin D of back level trigger, being familiar with the present technique personnel will be understood that, this mode of being connected in series constitutes a shift register (shift register), and the data output end Q of trigger 3220 is first order outputs of this shift register, the rest may be inferred, and the data output end Q of trigger 322M is the output of the final stage of this shift register.The data output end Q of trigger 3220 also is connected to another input of logical AND gate 326 simultaneously except being connected to the data input pin D of trigger 3221.In a plurality of triggers (3220-322M), except first order trigger 3220, the data output end Q of all the other triggers (3221-322M) all is connected to the input of multiplexer 324.Therefore, by Fig. 6 A as can be known, M equals 2
N, wherein N is the number of the signal selection wire of multiplexer 324.The clock pulse input CLK of a plurality of triggers (3220-322M) is electrical connected each other, and receives the VCO clock signal VCO_CLOCK of phase locked loop system 100 thus.Logical AND gate 326 outputs one non-locking index signal UNLOCK, and all export in the high level when the output (phase error that its expression postpones) of data output end Q of first order trigger 3220 (phase error that its expression is present) and multiplexer 324, logical AND gate 326 is established this non-locking index signal UNLOCK.
In the present embodiment, trigger (3220-322M) is in order to obtain the phase error signal PH of a plurality of delays or displacement
ERR, be familiar with the present technique personnel when the delay circuit that know other all applicable to the present invention.In addition, in the present embodiment, multiplexer 324 is in order to selecting one of them in the middle of a plurality of delayed phase error signals, be familiar with the present technique personnel when the selector that know other all applicable to the present invention; Very the person if do not consider the adjustable of error degrees of tolerance, then can omit multiplexer 324.According to other embodiment of the present invention, the logical AND gate 326 that sampling logical block 320 comprises can also be replaced into logical AND not gate (NAND gate), logic sum gate (OR gate) or logic OR not gate (NORgate), and it depends on that the logic system that circuit design adopts is positive logic system, negative logic system or the combination of the two.
The main signal sequence graph of a relation of Fig. 6 B displayed map 6A sampling logical block 320.Fig. 6 B is the situation that illustration multiplexer 324 has been selected the data output end Q (that is Q_1) of second level trigger 3221, and it comprises phase error signal PH
ERR, the data output signal Q_1 of data output signal Q_0, second level trigger 3221 of VCO clock signal VCO_CLOCK, first order trigger 3220 and logical AND gate 326 output signal U NLOCK between sequential relationship.Suppose that all triggers (3220-322M) are reset in zero-time t0 (not being shown among the figure), the meaning i.e. Q output of all triggers all is eliminated and is low level.In the VCO_CLOCK of time t1 rising edge, phase error signal PH
ERRBe in low level, expression is with reference to clock signal RCLK and VCO frequency division clock signal VCLK homophase.VCO_CLOCK in the rising edge of time t1 respectively with PH
ERRWith low level difference feed-in trigger 3220 and the trigger 3221 of Q_0, so first order Q_0 and second level Q_1 still keep low level behind the VCO_CLOCK rising edge of this time t1, this makes the output signal U NLOCK of logical AND gate 326 also be maintained at low level.In the VCO_CLOCK of time t2 rising edge, phase error signal PH
ERRBecome high level, expression with reference to clock signal RCLK and VCO frequency division clock signal VCLK in this moment of homophase not.VCO_CLOCK in the rising edge of time t2 respectively with PH
ERRHigh level and the low level of Q_0 feed-in trigger 3220 and trigger 3221 respectively, then keep low level so Q_0 becomes high level Q_1 behind this VCO_CLOCK rising edge, this makes the output signal U NLOCK of logical AND gate 326 still keep low level.In the VCO_CLOCK of time t3 rising edge, phase error signal PH
ERRBe maintained at high level, expression is with reference to clock signal RCLK and VCO frequency division clock signal VCLK homophase not still.VCO_CLOCK in the rising edge of time t3 respectively with PH
ERRHigh level difference feed-in trigger 3220 and trigger 3221 with Q_0, so Q_0 and Q_1 all become high level behind this VCO_CLOCK rising edge, this makes the output signal U NLOCK of logical AND gate 326 become high level, and expression has exceeded selected phase error degrees of tolerance with reference to clock signal RCLK and the out of phase state of VCO frequency division clock signal VCLK.
Another main signal sequence graph of a relation of Fig. 6 C displayed map 6A sampling logical block 320.Different being in multiplexer 324 of Fig. 6 C and Fig. 6 B is to have selected the data output end Q (that is Q_2) of third level trigger 3222 (not being shown among the figure) as its output in this example.So Fig. 6 C content displayed is phase error signal PH
ERR, the data output signal Q_2 of data output signal Q_0, third level trigger 3222 of VCO clock signal VCO_CLOCK, first order trigger 3220 and logical AND gate 326 output signal U NLOCK between sequential relationship.The signal transition of Fig. 6 C in time t0 to t2 is identical with Fig. 6 B.In the VCO_CLOCK of time t3 rising edge, phase error signal PH
ERRBe maintained at high level, expression is with reference to clock signal RCLK and VCO frequency division clock signal VCLK homophase not still.VCO_CLOCK in the rising edge of time t3 respectively with PH
ERRHigh level difference feed-in first order trigger 3220 and second level trigger 3221 with Q_0, so Q_0 and Q_1 all become high level behind this VCO_CLOCK rising edge, but the data output end Q of trigger 3222 still keeps low level, and meaning is that Q_2 still keeps low level.Because this embodiment has selected the output of Q_2 as multiplexer 324,, still keep low level so the output signal U NLOCK of logical AND gate 326 is the result of Q_0 and 326 computings of Q_2 process logical AND gate.This expression does not exceed the selected phase error degrees of tolerance of this locking circuit for detecting with reference to clock signal RCLK and the out of phase degree of VCO frequency division clock signal VCLK.In other words, the phase error of this kind degree can't hinder the phase-locked loop to enter lock-out state.Fig. 6 C painstakingly enumerates identical phase error signal PH with Fig. 6 B
ERRCause different lock-out states to judge, this judgement mainly comes from the different configuration of multiplexer 324 input control ends and has selected different phase error degrees of tolerance.
Sampling logical block 320 by present embodiment, if because of element matching problem, process variation or variation of temperature, even and cause relative phase locked loop system 100 locked, but when locking circuit for detecting 300 still detects the static phase difference of can not ignore, then can select bigger phase error degrees of tolerance, that is multiplexer 324 is selected the trigger output of big progression.
According to the disclosed locking circuit for detecting 300 of the foregoing description, the locking method for detecting of the summary conclusion embodiment of the invention as shown in Figure 7.At first, according to the reference clock signal RCLK and the VCO frequency division clock signal VCLK of phase locked loop system, to produce a phase error signal PH
ERR(step 70).Then, according to phase error signal PH
ERRTo produce a plurality of delayed phase error signals (step 72).After selecting one of them delayed phase error signal (step 74), according to the state of present phase error signal and selected delayed phase error signal, to produce and to establish a non-locking index signal UNLOCK (step 76).At last, counting if non-locking index signal UNLOCK is not established in the burst length in the given number of reference clock signal RCLK, then produces and establishes a loop lock indication signal LOCK (step 78) with reference to clock signal RCLK.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100: phase locked loop system
110: front frequency divider
120: the phase frequency detector
130: charge pump
140: low pass filter
150: voltage controlled oscillator
160: rear frequency divider
170: feedback divider
200: tradition locking circuit for detecting
210,316: XOR gate
220: click counter
300: the locking circuit for detecting
310: input time-pulse error detecting logical block
312/314: trigger
320: the sampling logical block
324: multiplexer
326: logical AND gate
330: click the counting logical block
3220-322M: trigger
P
IN: phase-locked loop input clock signal
P
OUT: phase-locked loop output clock signal
RCLK: with reference to clock signal
VCLK: VCO frequency division clock signal
UP: go up clock signal
DOWN: following clock signal
T
CLK: the clock pulse input of clicking counter
T
RESET: the replacement end of clicking counter
PH
ERRPhase error signal
VCO_CLOCK: VCO clock signal
MUX_CTRLs: error degrees of tolerance control signal
LOCK: loop lock indication signal
UNLOCK: non-locking index signal
Q_0/Q_1/Q_2/Q_2
N: the flip-flop data output signal
D: flip-flop data input
Q: the noninverting data output end of trigger
Q ': trigger oppisite phase data output
CLK: trigger clock pulse input
NReset: the replacement end of trigger
N: the number of multiplexer control signal
AND: the mark of logical AND gate
XOR: the mark of logic XOR gate
T1/t2/t3/t4: the particular point in time of sequential chart
Claims (17)
1. the locking circuit for detecting of a phase locked loop system is characterized in that, the locking circuit for detecting of described phase locked loop system comprises:
One delay cell in order to importing a phase error signal of this phase locked loop system, and postpones this phase error signal to produce at least one delayed phase error signal to produce a present phase error signal according to this present phase error signal;
One selector in order to according to an error degrees of tolerance control signal, is selected one from this at least one delayed phase error signal that inputs to this selector; And
One establishes logical block, in order to the state according to this present phase error signal and selected this delayed phase error signal, to produce a non-locking index signal;
Wherein, this error degrees of tolerance control signal is adjusted the tolerance of this phase error signal in order to control.
2. according to the locking circuit for detecting of the described phase locked loop system of claim 1, it is characterized in that above-mentioned selector is a multiplexer.
3. according to the locking circuit for detecting of the described phase locked loop system of claim 1, it is characterized in that above-mentioned delay cell is a shift register, in order to import the phase error signal of this phase locked loop system, to produce a plurality of above-mentioned delayed phase error signals.
4. according to the locking circuit for detecting of the described phase locked loop system of claim 3, it is characterized in that above-mentioned shift register comprises the trigger of a plurality of series connection, a plurality of a plurality of these delayed phase error signals of trigger output that should connect.
5. according to the locking circuit for detecting of the described phase locked loop system of claim 4, it is characterized in that the clock pulse input of above-mentioned shift register or trigger receives the VCO clock signal of this phase locked loop system.
6. the locking circuit for detecting of a phase locked loop system is characterized in that, the locking circuit for detecting of described phase locked loop system comprises:
One input time-pulse error detecting logical block, its according to this phase locked loop system one with reference to a clock signal and a VCO frequency division clock signal, to produce a phase error signal;
One sampling logical block, it postpones this phase error signal to produce a present phase error signal, and this present phase error signal of foundation is to produce at least one delayed phase error signal; This sampling logical block comprises a selector, in order to according to an error degrees of tolerance control signal, from at least one delayed phase error signal that inputs to this selector, select one, and the logical block of should sampling is according to the state of this present phase error signal and selected delayed phase error signal, to produce a non-locking index signal; And
One counting logical block in order to count this with reference to clock signal, if this non-locking index signal is not established in the burst length in this given number with reference to clock signal, then produces and establishes a loop lock indication signal;
Wherein, this error degrees of tolerance control signal is adjusted the tolerance of this phase error signal in order to control.
7. according to the locking circuit for detecting of the described phase locked loop system of claim 6, it is characterized in that above-mentioned sampling logical block comprises:
One delay cell is in order to import this phase error signal to produce this at least one delayed phase error signal; And
One establishes logical block, and it is according to the state of this present phase error signal and selected this delayed phase error signal, to produce this non-locking index signal.
8. according to the locking circuit for detecting of the described phase locked loop system of claim 6, it is characterized in that above-mentioned selector is a multiplexer.
9. according to the locking circuit for detecting of the described phase locked loop system of claim 7, it is characterized in that above-mentioned delay cell is a shift register, in order to import the phase error signal of this phase locked loop system, to produce a plurality of above-mentioned delayed phase error signals.
10. according to the locking circuit for detecting of the described phase locked loop system of claim 9, it is characterized in that above-mentioned shift register comprises the trigger of a plurality of series connection, a plurality of a plurality of these delayed phase error signals of trigger output that should connect.
11. the locking circuit for detecting according to the described phase locked loop system of claim 10 is characterized in that, the clock pulse input of above-mentioned shift register or trigger receives the VCO clock signal of this phase locked loop system.
12. the locking circuit for detecting according to the described phase locked loop system of claim 6 is characterized in that, above-mentioned counting logical block is to click counter, and it counts this with reference to clock signal, and then resetting when this non-locking index signal is established, this clicks counter.
13. the locking circuit for detecting according to the described phase locked loop system of claim 6 is characterized in that, above-mentioned input time-pulse error detecting logical block comprises:
Clock pulse on one/following clock signal produces circuit, its according to the reference clock signal of this phase locked loop system and VCO frequency division clock signal to produce on one clock signal and clock signal once; And
One exclusive or logic gate, input should be gone up clock signal, this time clock signal, to produce this phase error signal.
14. locking circuit for detecting according to the described phase locked loop system of claim 13, it is characterized in that, above-mentioned clock pulse/following the clock signal of going up produces the trigger that circuit comprises two parallel connections, the clock pulse input of described trigger receives this respectively with reference to clock signal, this VCO frequency division clock signal, the replacement end of described trigger all is controlled by this non-locking index signal, the data input pin of described trigger is connected in its oppisite phase data output separately, and the noninverting data output end of described trigger all is connected in the input of this exclusive or logic gate.
15. the locking method for detecting of a phase locked loop system is characterized in that, the locking method for detecting of described phase locked loop system comprises:
According to this phase locked loop system one with reference to a clock signal and a VCO frequency division clock signal, to produce a phase error signal;
This phase error signal is postponed to produce a present phase error signal, and this present phase error signal of foundation is to produce at least one delayed phase error signal;
Select one of them of this at least one delayed phase error signal according to an error degrees of tolerance control signal;
According to the state of this present phase error signal and selected delayed phase error signal, to produce and to establish a non-locking index signal; And
Count this with reference to clock signal,, then produce and establish a loop lock indication signal if this non-locking index signal is not established in the burst length in this given number with reference to clock signal;
Wherein, this error degrees of tolerance control signal is adjusted the tolerance of this phase error signal in order to control.
16. the locking method for detecting according to the described phase locked loop system of claim 15 is characterized in that, the generation step of above-mentioned at least one delayed phase error signal is that this phase error signal is carried out shift LD, to produce a plurality of above-mentioned delayed phase error signals.
17. locking method for detecting according to the described phase locked loop system of claim 15, it is characterized in that, in the generation step of above-mentioned non-locking index signal,, then produce this non-locking index signal when this present phase error signal and selected delayed phase error signal are when establishing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2006101500255A CN1945977B (en) | 2006-10-24 | 2006-10-24 | Lock detecting circuit and method for phase lock loop system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101500255A CN1945977B (en) | 2006-10-24 | 2006-10-24 | Lock detecting circuit and method for phase lock loop system |
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| CN1945977A CN1945977A (en) | 2007-04-11 |
| CN1945977B true CN1945977B (en) | 2011-01-12 |
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| JP2002305444A (en) * | 2001-04-06 | 2002-10-18 | Seiko Epson Corp | Pll circuit |
| CN1380749A (en) * | 2001-04-10 | 2002-11-20 | 日本电气株式会社 | Phase-lock detecting circuit |
| US6757349B1 (en) * | 1998-01-16 | 2004-06-29 | Fujitsu Limited | PLL frequency synthesizer with lock detection circuit |
| US6762631B1 (en) * | 2001-11-06 | 2004-07-13 | National Semiconductor Corporation | Lock detection circuit for a phase locked loop circuit |
| CN1815891A (en) * | 2005-02-03 | 2006-08-09 | 联发科技股份有限公司 | Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof |
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2006
- 2006-10-24 CN CN2006101500255A patent/CN1945977B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6757349B1 (en) * | 1998-01-16 | 2004-06-29 | Fujitsu Limited | PLL frequency synthesizer with lock detection circuit |
| JP2002305444A (en) * | 2001-04-06 | 2002-10-18 | Seiko Epson Corp | Pll circuit |
| CN1380749A (en) * | 2001-04-10 | 2002-11-20 | 日本电气株式会社 | Phase-lock detecting circuit |
| US6762631B1 (en) * | 2001-11-06 | 2004-07-13 | National Semiconductor Corporation | Lock detection circuit for a phase locked loop circuit |
| CN1815891A (en) * | 2005-02-03 | 2006-08-09 | 联发科技股份有限公司 | Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof |
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