JPH03139011A - Phase comparator - Google Patents

Abstract

PURPOSE:To obtain a phase comparator with low noise by connecting inputs of plural phase comparators in parallel, adding phase outputs at each output, and extracting a difference output so as to improve the S/N. CONSTITUTION:Since phase detection output components among output signals of EOR gates 31-34 are in-phase, currents of four outputs are added after passing through resistors 41-44 to be 4-times phase detection output. However, the noise component in output signals of gates 31-34 is an independent signal, when the 4 independent noise components are in-phase, they are added after passing through the resistors 41-44 and when they are opposite in phase, they are cancelled after through the resistors 41-44. That is, when N sets of noise components are added, the total noise component is in general the total sum of each of noise power and when the noise power of each is equal to each other, the noise power is a multiple of N and the noise current is a multiple of N<1/2>. Thus, in the case of N=4, the noise goes to 41/2=2 and the S/N is improved double.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase comparator suitable for use in, for example, a frequency synthesizer or a phase periodic oscillator.

[Prior art] Figure 4 shows, for example, the exclusive jib orer (hereinafter referred to as ,
1 is a circuit diagram showing a conventional phase comparison device using an EOR (EOR) gate.

In the figure, (1) is the input terminal to which the reference signal φ8 is supplied, 2) is the input terminal to which the tested wave signal (phase comparison signal) φ8 is supplied, and (3) is the input terminal where one input terminal is supplied ( 1
), the other input terminal is connected to the input terminal (2), the EOR gate (4) is connected to the output terminal of the E○R gate (3), and a resistor that limits its output current, ( 5〉
is a capacitor connected between the other side of the resistor (4) and the ground to smooth the output current, and (6) is an output terminal from which an output voltage 5 is obtained.

The conventional phase comparator is configured as described above.
The operation will be explained in detail below.

The signals φ and φ6 inputted to the EOR gate (3) from the input terminals (1) and (2) are signals of the same frequency with a duty of 50%. The FOR gate (3) outputs a low level when the two input signals have the same logic level, and outputs a high level when the two input signals have different logic levels.

Therefore, when the phase difference between the signals φ9 and φ8 is zero, the logic levels of the two input signals are equal, so the output signal is always at a low level. Conversely, when the phase difference between the signals φ and φ3 is π, the logic levels of the two input signals are always different, so the output signal is always at a high level. Signal φ8. φ,
When the phase difference is in between, the output signal becomes high level only in a period proportional to the phase difference. This output signal is connected to a resistor (4
) and a capacitor 5), the output voltage V0 obtained at the output terminal (6) has characteristics as shown in FIG. 5, and the signal φ6. An output voltage vo proportional to the phase difference between φ and φ can be obtained. The detection sensitivity KD at this time is as follows. Here, v0□ is the minimum output voltage.

[Problem to be solved by the invention] As mentioned above, in the conventional phase comparator, the detection sensitivity is
v, , -v°' [V/rod is obtained. However, since the semiconductor used in the EOR gate (3) at π generates colored noise (current noise: voltage noise: phase jitter noise, etc.), the sum of this noise is converted into the output voltage and is
. Conventionally, the signal-to-noise ratio expressed in [V] is the maximum output voltage ■. , is high and the minimum output voltage V. There were problems such as having to use a separate element with low L or using a CMOS gate IC such as 748C86, which is a CMOS digital IC manufactured by Mitsubishi Electric Corporation, with a high power supply voltage.

This invention was made in order to solve the above-mentioned problems, and it is possible to achieve the above-mentioned signal-to-noise ratio without increasing the power supply voltage by using the same elements as before, and to create a phase comparator with less noise. It is a promise to obtain.

[Means for Solving the Problems] A phase comparator according to the present invention includes a plurality of phase comparators (
N pieces) are used, their input sides are connected in parallel, and their output sides are summingly connected using a resistor or the like.

In this invention, a plurality (N) of long phase ratio fR devices are used, their input sides are connected in parallel, and their output sides are connected so as to obtain a differential output.

In this invention, N phase comparators are arranged in parallel, and the signal components output from each phase comparator are summed so that a differential output is obtained. By setting N (Δ) and multiplying the signal component with no random correlation G output from each phase comparator, that is, the [component] by -N times, the signal-to-noise ratio is renamed to In- times.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

No. 111J is a circuit diagram showing an embodiment of the phase comparator according to the present invention, and in the figure, (1), (2) and (5) are completely the same as those in the conventional phase comparator. (31) to (34) are a plurality of phase comparators, for example, four phase comparators, for example, EOR gates, each of which has one input terminal commonly connected to the input terminal (1), and each other input terminal which is commonly connected. and is connected to the input terminal (2). (
41) to (44) are each FOR gate (31) to (34)
A resistor that sums the outputs of , each negative side of which is EOR
It is connected to each output terminal of the gates (31) to (34), respectively, and the other sides are commonly connected and connected to the output terminal (6). (5) is a smoothing capacitor, which is connected between the common connection point on the other side of the resistors (41) to (44) and the ground. ~(3・
It is exactly the same as the conventional phase comparator shown in Fig. 3.4, except that four resistors (41) to (44) are connected in parallel.

Among the output signals of the EOR gates (31) to (34), the phase detection output components are in phase, so the currents for the four outputs are added together after passing through the resistors (41) to (44), and the phase is quadrupled. This becomes the detection output current.

However, since the noise components of the output signals of the EOR gates (31) to (34) are each independent signals, when the four independent noise components are in phase, the resistors (41) to (44)
) are added together, and when the phase is reversed, the resistor (41)
~(44) and are canceled out.

When N independent noise components are added, the total noise component in the - shell is the sum of the power of each noise component, so when each noise power is equal, the noise power is N times. Converting this to current is: power - resistance x (current > 2), so the noise current is enormous. Therefore, when N = 4, the noise is JW
= 2a. Then, the signal-to-noise ratio is that the signal component is 4
Since the noise component is doubled, the improvement is doubled.

In this way, in this invention, four EOR gates (31) to
Since the output signals of (34) are added, it is possible to improve the signal-to-noise ratio by 2 (B).Since the CMOS digital IC C74HC86 includes four EOR gates, this example uses only one IC. Can be configured.

Although the number of phase comparators was four in the above embodiment, the same effect can be obtained no matter how many phase comparators are connected in parallel as long as they are two or more. - When the output signals of N phase comparators are added in the shell, the detection output current will be N times larger and the noise current will be 8" times larger, so the signal-to-noise ratio will be improved by 5 times. However, N is 2 is an integer greater than or equal to

Further, in the above embodiment, the phase comparator is an EOR gate, but it may also be a frequency phase comparator, a flip-flop, or a double-balanced mixer, and in these cases, the above embodiment also applies. It has the same effect as.

In the above embodiment, the input sides of the phase comparators are connected in parallel, but the same effect can be obtained by inverting the signals applied to the two input terminals of some phase comparators using an inverter or the like. Such an example is shown in a circuit diagram in FIG. That is, in FIG. 2 showing another embodiment of the present invention, the FOR gate (31
) are respectively connected to input terminals (1) and (2) via inverters (7) and (8), and each input terminal of the EOR gate (32) is connected to input terminals 7-(1) and (
2) directly connected to. EOR gate (31), (3
Each output terminal of 2) has a resistor (41) and (42), respectively.
After being connected in common via the output terminal (6). A capacitor (5) is connected between the common connection point of the resistors (41) and (42) and ground. Figure 2 shows that the number of FOR gates is 2, and the number of EOR gates (31) is 2.
The operation is similar to that of FIG. 1 except that both input signals are inverted by inverters (7) and (8).

An EOR gate is a gate whose output signal is low level when the logic levels of two input signals match, and whose output signal is high level when the logic levels of the two input signals are different. Even if the logic levels of both input signals are inverted as in 31), the operation is exactly the same. (2) However, since the signal is delayed by the inverters (7) and (8), the output voltage V obtained at the output terminal (6). are two EORs separated by the delay time of inverters (7) and (8)
The voltage is the average of the gate output signals.

Note that in the previous embodiments, the phase comparator had one output, but it is also possible to make the output a differential output. A circuit diagram of such an example is shown in FIG.

That is, in FIG. 3 showing a further embodiment of the present invention, each input terminal of the FOR game 1-(31) is connected to the input terminal <1) and (2), respectively, and the output terminal is connected to the resistor (
41) to the output terminal (61). A capacitor (51) is connected between the output terminal (61) and ground.

Further, one input end of the EOR gate (32) is connected to the input terminal (2), and the other input end is connected to the input terminal (1) via the inverter (9). FOR gate (32)
Connect the output terminal of the terminal to the output terminal (62) via the resistor (42), and connect the capacitor (5) between the output terminal (62) and ground.
2) Connect.

The operations of the upper half of FIG. 3 (31), (41), and (51) are exactly the same as those of the conventional phase comparator.

The lower half (32), (42), (52), and (9) will be explained. When the inverter (9) input terminal (1) input terminal (1) input signals φ and φ are at the same logic level, the output voltage ■1□9 obtained at the output terminal (6) becomes high level, and the opposite At the logic level, the output voltage V I m V becomes low level. Therefore, the output voltage Vo obtained at the output terminal (61) and the output voltage V obtained at the output terminal (62)
ImV is in reverse phase and a differential output is obtained.

In this embodiment, the inverter (9) is placed on the input terminal (1) side, but a differential output can be obtained in the same way even if the inverter (9) is placed on the input terminal (2) side.

It goes without saying that by connecting N such differential output phase comparators π in a differential array, the signal-to-noise ratio can be improved to 5 t=.

[Effects of the Invention] As detailed above, the present invention provides a plurality of phase comparators, connects each input side in parallel, and calculates the difference by adding the outputs of the phase comparators to each output side. Since the dynamic output can be taken out, the signal-to-noise ratio can be improved without increasing the power supply voltage using the same elements as before, and a low-noise phase comparator can be obtained. play.

[Brief explanation of the drawing]

1 (2ff) is a circuit diagram showing an embodiment of the phase comparator according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a circuit diagram showing a further embodiment of the present invention. 412I is a circuit diagram showing a conventional phase comparison device, No. 5
The figure is a waveform diagram showing the output voltage with respect to the phase difference of the input signal of the phase comparison device of FIG. 4. In the eyes, (31) to (34) are E OR gates, (
41) to (44) are resistors, (5), (51), (
52) is a capacitor, and (7) to (9) are inverters. Note that the same reference numerals in each figure indicate the same or corresponding parts. Representative Person Zeng Ga Dao Head Shape l Yifu 2 Centric Mind 3 Figure

Claims (2)

[Claims] (1) A phase comparison device comprising a plurality of phase comparators, each of whose input sides are connected in parallel, and each of whose output sides are connected in addition. (2) A phase comparison device comprising a plurality of phase comparators, each of whose input sides are connected in parallel, and whose output sides are connected so as to obtain a differential output.