1288530 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於一種在採用例如無線或者有線進行通信 的通信裝置等中使用的振盪器。 【先前技術】 在習知技術中具有在採用例如無線或者有線進行通信 的通信裝置等中使用的振盪器。 對於這樣的振盪器的具體例採用圖3進行說明。 習知技術的振盪器的一例的振盪器B，具有已知的相 鎖迴路（PLL)構成，藉由設置在內部的控制器15〇接收由 微處理單元（MPU) 100輸出的鎖存訊號（LE) 、DATA訊 號（DΑΤΑ )以及時鐘訊號（CLK )以進行控制。 具體而言，振盪器Β的構成包括，藉由獲取成爲用於 從RF輸出端子170獲取所需頻率的輸出訊號的基準的可 以在外部高精度調整的參考訊號（以下簡稱爲「REF」） 以及振盪器Β實際輸出的輸出訊號（以下簡稱爲「RF」 )偵測所獲取的REF以及RF相互之間的相位差、根據該 偵測結果輸出爲將上述輸出訊號控制成所需頻率的控制指 令訊號的相位頻率偵測器1 3 0、對應該相位差對由相位頻 率偵測器1 30輸出的控制指令訊號進行反轉或非反轉處理 的充電泵140、對由該充電泵140輸出的控制指令訊號進 行平滑處理的迴路濾波器300、根據被迴路濾波器3 00實 施平滑處理的控制指令訊號生成所需頻率的RF (輸出訊 -5 - 1288530 (2) 號）的壓控振盪器400。 另外，RF從RF輸出端子170輸出，REF從REF輸 入端子160輸入。 REF以及RF雖然是由相位頻率偵測器130獲取的訊 號，此兩訊號，在輸入到相位頻率偵測器1 3 0之前，預先 分別由分頻器1 10 ( RF用）、分頻器120 ( REF用）以預 定分頻比例對對應訊號進行分頻。當REF以及RF的周期 相同時，則沒有必要設置分頻器1 10、120。 對於充電泵1 40，由於是根據輸入訊號的相位差使相 位頻率偵測器1 3 0的輸出訊號在正恒定電流輸出、負恒定 電流輸出、或者無輸出（關斷）三種模式之間變換，但是 其也可以省略。 另外，頻率合成器1C是由分頻器110、分頻器120、 相位頻率偵測器1 3 0、充電泵1 4 0、以及控制器1 5 0整合 在一個積體電路中的1C晶片的一例。 這樣構成的振盪器B，例如按照圖4所示時序獲取以 及生成各訊號。 例如，從REF輸入端子160輸入的REF，由上述分 頻器120進行分頻（這時的分頻比r=2)後形成FR1， 另一方面由壓控振盪器400輸出的RF由上述分頻器110 分頻（這時的分頻比R=8)後形成FN1，上述兩個訊號 (FR1以及FN1 )變成相同周期後，由相位頻率偵測器 130獲取。 上述相位頻率偵測器1 3 0對所獲取的兩個訊號（FR 1 1288530 (3) 以及FN 1 )偵測相互之間的相位差，根據該相位差輸出控 制指令訊號。 進一步，充電泵1 40根據所輸出的控制指令訊號對該 控制指令訊號進行處理，處理後的訊號的CP 1進一步由 迴路濾波器3 00實施平滑處理。最後上述壓控振盪器400 根據實施了該平滑處理的訊號輸出所需頻率的RF。 在此，以下說明對充電泵1 40所進行的控制指令訊號 的處理。 例如，當圖4所示FR1的相位超前於FN1的相位時 ，充電泵1 40以與相位差對應的脈衝寬度的正恒定電流脈 衝形式輸出C P 1，另一方面，如圖5所示當F R1的相位滯 後於FN 1的相位時，充電泵1 4 0以與相位差對應的脈衝 寬度的負恒定電流脈衝形式輸出C P 1。另外，在沒有脈衝 的期間，充電泵1 40的輸出處於開放狀態。 因此，壓控振盪器400，根據上述CP1的恒定電流脈 衝的極性以及脈衝寬度將RF的頻率控制成所需値。 然而，在近年來顯著發展的有線或者無線的通信環境 中，高度的數位調製方式開始使用更高的頻率。 爲此’要求在彳數位g周製訊號解調時，在該數位調製 訊號的頻率變換中使用的振盪器B中盡可能降低所産生的 相位雜訊。 衆所周知，該振盪器B所産生的相位雜訊，在上述分 頻器110、120的分頻比越大時越大。 作爲具體的實驗結果，當RF的輸出頻率爲6 GHz、 (4) 1288530 分頻比N = 2 0 0、相位頻率偵測器1 3 0中的處理頻率爲 30MHz時，相位雜訊的底部電位爲 -97dB/Hz的程度 (底部電位是指從RF的輸出頻率的最大値觀察的相位雜 訊的低頻成份，主要是由頻率合成器1C産生的相位雜訊 的電位）。 另一方面，當RF的輸出頻率爲6GHz、分頻比N = 6 0 00、相位頻率偵測器130中的處理頻率爲1MHz時，相 位雜訊的底部電位爲-84dB/Hz的程度。 上述實驗結果表明，當RF爲相同値時，分頻比越大 ，相位雜訊增加。 爲此，雖然可以考慮縮小上述分頻器的分頻比，但現 實情況，由於相位頻率偵測器1 3 0所處理的相位比較頻率 具有上限（最大約爲56MHz )，如上述那樣處理高頻時 ’由於需要採用分頻比大的分頻器，要抑制相位雜訊是困 難的。 另一方面，在特開平11 一 32951號公報中，揭示了在 P L L的非鎖相和鎖相的過程中，在具有廣鎖相範圍之p l L 的數位相位比較器和相位雜訊低的類比相位比較器之間切 換使用的技術。依據該技術，隨著廣的鎖相範圍，雖然可 以獲得相位雜訊低的訊號，但仍然存在必須採用可以實現 所要求的相位雜訊的高精度的相位比較器的問題。 【發明內容】 因此，本發明正是針對上述情況的發明，其目的在於 -8- 1288530 (5) 在不提高實際的相位比較頻率的情況下，並且特別是不採 用高精度的機器的情況下，可以降低相位雜訊。 爲達到上述目的，依照本發明之第一觀點，於此提供 一種振盪器，包括一預定振盪單元用以輸出一輸出訊號； 和多數相位頻率偵測器。每一相位頻率偵測器偵測介於兩 輸入訊號，即，振盪單元的輸出訊號和從外部參考訊號的 兩個輸入訊號的相位差，和根據該相位差，輸出控制指令 訊號以將上述輸出訊號控制在所需頻率。藉由結合從多數 相位頻率偵測器輸出之多數控制指令訊號而產生的合成控 制指令訊號向上述振盪機構輸出。 藉由這樣的構成，依據實驗結果，即使採用並不特別 具有高精度的、在現有性能情況下之廉價的相位頻率偵測 器，也可以降低相位雜訊。 另外，依照本發明之第二觀點，於此提供一種振盪器 ，包括多數預定振盪單元用以輸出多數輸出訊號；多數相 位頻率偵測器，每一相位頻率偵測器用以偵測介於兩輸入 訊號，即對應振盪單元的輸出訊號和外部參考訊號間的相 位差，和根據該相位差，輸出一控制指令訊號以控制上述 輸出訊號在所需頻率；和一結合和輸出單元，用以結合從 多數振盪單元輸出的多數輸出訊號，和輸出一合成訊號。 以具有如同相位頻率偵測器相同數目之振盪單元之振 盪器構成，相位雜訊亦可降低至如同在依照本發明之第一 觀點中之振盪器相同的程度，其中合成控制指令訊號輸出 至單一振盪單元。 -9 - 1288530 (6) 然而，使上述多數相位頻率偵測器並行操作時，有時 會出現相位雜訊降低變異的情況。這可以推測爲，由於在 對上述相位頻率偵測器進行頻率設定和計數器設定的致動 訊號中的鎖存訊號（用於控制各設定訊號在上述相位頻率 偵測器側的讀取時序的訊號）的相位抖動的影響，在上述 多數相位頻率偵測器相互之間的致動時序出現微小的偏差 時，上述多數相位頻率偵測器分別以微小不同的相位作爲 目標値動作，其結果，出現不能充分降低相位雜訊的現象 〇 因此，即使在這樣的情況下，藉由使上述多數相位頻 率偵測器的再致動（重設）重復1次或者多次，可以始終 使相位雜訊穩定在預定的低水平狀態。這可以認爲，在重 復再致動的過程中，由致動訊號引起的再致動的時序的微 小偏差，可能會引起在上述多數相位頻率偵測器相互之間 的致動時序不出現微小偏差的狀態。 爲此，是否可以獲得充分降低的相位雜訊，可以藉由 上述合成控制指令訊號中的交流成份的振幅、或者上述多 數相位頻率偵測器中兩個輸入訊號的相鎖訊號（所謂的鎖 相訊號）中的一方或者兩分進行判定，在獲得充分降低的 相位雜訊之前，重復上述多數相位頻率偵測器的再致動。 具體而言，依照本發明第一觀點之振盪器，包括偵測 上述合成控制指令訊號中的交流成分的振幅是否小於或等 於預定位準的振幅偵測機構；當藉由上述振幅偵測機構未 偵測到上述振幅小於或等於預定位準時，再致動上述多數 -10 - (7) 1288530 相位頻率偵測器的第一再致動機構。 另外，依照本發明之第一或第二觀 偵測上述多數相位頻率偵測器中上述兩 是否相鎖的鎖偵測機構；當藉由上述鎖 上述多數相位頻率偵測器的全部或預定 時，再致動上述多數相位頻率偵測器的 這樣，可以使相位雜訊始終穩定在 另外，在各個通向上述多數相位頻 給路線中具備濾波器。 如本發明，當上述多數相位頻率偵 由於各元件的輸出訊號的電位（脈衝） 果各元件共用電源，在各元件中大致一 流，有可能出現電源電壓依照脈衝狀下 下降成爲脈衝雜訊。 爲此，藉由設置上述濾波器，可以 雜訊。 另外，在上述多數相位頻率偵測器 也可以設置有把由上述相位頻率偵測器 參考訊號分別分頻爲預定分頻比的分頻 藉由採用這樣的分頻器，可以任意 和上述參考訊號各自的分頻比的組合， 構的輸出頻率符合所需目標頻率。 然而，當多數相位頻率偵測器並行 出訊號中包含大的虛擬訊號，有時會出 點之振盪器，包括 個輸入訊號的相位 偵測機構未偵測到 的數量以上爲相鎖 第二再致動機構。 低位準狀態。 率偵測器的電源供 測器並行動作時， 大致一起變化，如 起流入大的脈衝電 降的現象。該電壓 防止産生上述脈衝 的全部或一部分中 取得的輸出訊號和 設定上述輸出訊號 容易使上述振盪機 動作時，在上述輸 現包含上述虛擬訊 -11 - 1288530 (8) 號的輸出訊號（分頻後的訊號）與參考訊號（分頻後的訊 號）相鎖的現象，即被稱爲所謂錯誤鎖相的現象。這時， 即使在本來不應該偵測到上述兩個輸入訊號相鎖的情況下 ，也可能偵測到相鎖。 爲此，包括在由上述鎖偵測機構進行相鎖偵測之前， 在以預定的順序設定了上述振盪機構的可調整範圍中超過 上限頻率的第一設定頻率和低於下限頻率的第二設定頻率 等兩個設定頻率的與上述輸出訊號對應的分頻器的分頻比 後’設定與所需頻率的輸出訊號對應的分頻器的分頻比的 分頻比順序設定機構。 這樣，上述輸出訊號的頻率，由於將振盪單元的上限 以及下限的各頻率鎖定後調整到所需頻率（目標頻率）， 可以避免錯誤鎖相的現象。 【實施方式】 以下參照附圖說明本發明的實施例以及變化例，以利 於對本發明的理解。另外，以下的實施例以及變化例，只 是對本發明具體化的一例，並不具有限定本發明的技術範 圍的性質。 第一實施例 參考圖1說明依照本發明的第一實施例的振盪器A 的槪略構成。 振盪器A，大致由具有相位頻率偵測器等功能的積體 -12· 1288530 (9) 電路IC1以及IC2，藉由使該IC1和IC2共同進行處理以 構成PLL和產生RF (輸出訊號）的壓控振盪器410，和 控制IC1以及IC2的MPU10所構成。 在此，首先說明1C 1的槪略構成。 1C 1的槪略構成包括相位頻率偵測器1 3 1和充電泵 1 4 1。相位頻率偵測器1 3 1接收REF，其爲用於從RF輸 出端子170獲得所需頻率的輸出訊號的基準的在外部被高 精度調整的REF，和RF，其由振盪器A實際輸出之RF。 相位頻率偵測器1 3 1偵測REF及RF的兩個輸入訊號（具 體而言，由後述的分頻器111以及121分頻後的訊號FR 和FN )相互之間的相位差，和根據該偵測結果，輸出用 於將上述輸出訊號控制成所需頻率的控制指令訊號。充電 泵1 4 1，其根據相位差，對由上述相位頻率偵測器1 3 1輸 出的控制指令訊號進行處理。 另外，1C 1包括具有用於按照預定分頻比預先將輸入 (獲取）到上述相位頻率偵測器1 3 1的REF以及RF進行 分頻的分頻器111CRF用）、分頻器121( REF用）。藉 由該分頻器對上述兩個訊號分別分頻產生兩個相同周期的 訊號（FN1、FR1，參見圖2 )。 另外，如果上述REF以及RF的周期相同，則沒有必 要設置上述分頻器111、121。 進一步，IC1具有根據相位頻率偵測器131的輸出訊 號輸出正或者負的恒定電流脈衝的充電泵1 4 1。但是，充 電泵亦可以省略。 -13- 1288530 (10) 另外，對於IC2，具有和IC1相同功能的構成要素， 爲了和1C 1區別，使符號的第1位元爲「2」（例如1C 1 的相位頻率偵測器爲' 1 3 1時，IC2的相位頻率偵測器則爲 132)。 上述那樣構成IC1以及IC2由用於控制該IC1以及該 IC2的MPU10所控制。 具體而言，MPU10藉由向設置在IC1以及IC2內部 的控制器150傳送鎖存訊號（LE) 、DATA訊號（DATA )以及時鐘訊號（CLK)，對IC1以及IC2進行控制。 特別是對於振盪器A，藉由採用2個D正反器電路 21、22，由於上述鎖存訊號在不同的時間輸入到IC1以及 IC2的控制器151、152。因此，IC1以及IC2的開始動作 的時間不同。 具體而言，如圖2所示，IC1的分頻器1 1 1、121的 動作開始時間，比IC2的分頻器1 12、122的動作開始時 間，要提早REF波形的1個周期，預先設定成相位超前 (例如FR1的上升緣比FR2的上升緣要相位超前REF波 形的1個周期。 上述D正反器電路21、22，是用於使每個相位頻率 偵測器（每個1C )的RF以及REF的相位偏移預定量的 相位變更機構的一例。 對於上述那樣構成的振盪器A所進行的動作，採用 圖1、2進行說明。 首先，振盪器A的動作開始後，MPU10傳送鎖存訊 -14 - 1288530 (11) 號（LE)，所傳送的LE分別由上述兩個D正反器電路 21、22延遲後，輸入到IC1以及IC2所具有的控制器151 、152° 如上所述，藉由D正反器電路21、22，IC1以及IC2 的動作開始時間設定成相差REF波形的1個周期，1C 1先 開始動作後，IC2才開始動作。 在此，首先對IC1的動作進行說明。 首先，從REF輸入端子160輸入的REF，由分頻器 121進行分頻（這時的分頻比R=2)後形成FR1，另一方 面由壓控振盪器410輸出的RF由分頻器111分頻（這時 的分頻比R = 8 )後形成FN1，上述兩個訊號（FR1以及 FN 1 )變成相同周期後被輸入到相位頻率偵測器1 3 1。 相位頻率偵測器1 3 1對所輸入的兩個訊號（FR1以及 FN 1 )偵測相互之間的相位差，根據該相位差輸出控制指 令訊號。 進一步，充電泵1 4 1根據所輸出的控制指令訊號對該 控制指令訊號進行處理，處理後的訊號CP1進一步由迴 路濾波器3 1 0實施平滑處理。 然後，對IC2的動作進行說明。 另外，IC2和IC1雖然同樣動作，但其動作開始時間 ，如上所述，在延遲REF波形的1個周期後開始。 首先，從REF輸入端子160輸入的ref，由分頻器 122進行分頻（這時的分頻比R = 2 )後形成FR2，另一方 面由壓控振Μ器410輸出的RF由分頻器112分頻（這時 -15- 1288530 (12) 的分頻比R = 8 )後形成FN2，上述兩個訊號（FR2以及 FN2 )變成相同周期後，被輸入到相位頻率偵測器1 3 2。 相位頻率偵測器1 3 2對所輸入的上述兩個訊號（FR2 以及FN2 )偵測相互之間的相位差，根據該相位差輸出控 制指令訊號。 進一步，充電泵1 42根據所輸出的控制指令訊號對該 控制指令訊號進行處理，處理後的訊號的CP2進一步由 迴路濾波器3 1 0實施平滑處理。 然後，IC1以及IC2所輸出的CP1以及CP2藉由輸入 到迴路濾波器3 1 0，在進行訊號波形的平滑處理的同時進 行合成。以下說明CP1以及CP2。 CP1以及CP2輸入到迴路濾波器310的時序如圖2所 示0 圖2表示 CP1以及CP2按照REF波形的1個周期交 互從IC1以及IC2輸出，輸入到迴路濾波器310。 這樣使CP1以及CP2的輸出時序按照REF波形的1 個周期交互，是爲了分別具有相位頻率偵測器1 3 1、1 32 的IC1以及IC2的動作開始時間，如上所述，偏移REF 波形的1個周期量的相位。 因此，迴路濾波器3 1 0，藉由對相位偏移後的CP 1以 及CP2單純合成，產生新訊號Cp，藉由向最終輸出RF 的壓控振盪器410傳送，控制該壓控振盪器410。 然而，由上述迴路濾波器310生成的CP的頻率，由 於是CP1以及CP2單純合成後的頻率，是CP1或者CP2 -16- 1288530 (13) 的頻率的2倍（與相位頻率偵測器的數量比例增加），從 振盪器A整體觀察的相位頻率偵測器的動作頻率看上去 提高了 2倍。即，迴路濾波器3 1 0，是將每個相位頻率偵 測器輸出的控制指令訊號合成的控制指令合成機構的一例 〇 因此，振盪器A，由和已經說明的習知技術的振盪器 B具有相同分頻比的兩個相同相位頻率偵測器構成時，和 振盪器B相比，可以向壓控振盪器4 1 0輸入假想以上述振 盪器B的2倍頻率進行相位比較的控制訊號CP。 另一方面，CP1以及CP2的各自的相位雜訊由於基本 上是隨機的，合成後一部分相互抵消，上述合成控制指令 訊號的相位雜訊，不會隨上述多數相位頻率偵測器的數量 比例增加，在理論上只有2 )倍的程度。其結果，採 用現有性能情況下價廉的相位頻率偵測器，可以降低相位 雜訊（提高S/N比）。 變化例 在上述實施例中，雖然對振盪器A以習知技術的振 盪器B的2倍頻率輸出控制訊號CP的情況進行說明，例 如，如果由三個D正反器電路、三個和上述IC1相同構 成的積體電路、三種REF的分頻器的分頻比構成振盪器 時，可以以習知技術的振盪器B的3倍頻率輸出控制訊號 CP 〇 因此，藉由採用D正反器電路的數量、積體電路的 -17- 1288530 (14) 數量、REF的分頻器的分頻比分別爲整數倍來構成振盪器 ，可以以上述振盪器B的整數倍頻率輸出控制訊號CP。 另外’在上述中’作爲輸出RF的機構雖然示出的是 壓控振盪器的情況，如果從迴路濾波器3 1 0輸出的控制訊 號是電流値，也可以採用電流控制振盪器。 另外’在上述實施例中，雖然示出的是利用上述D 正反器電路2 1、2 2，使每個相位頻率偵測器（每個I c ) 的RF以及REF的相位偏移預定量，也可以不進行這樣的 相位變更。 圖6表示不進行每個相位頻率偵測器（每個ic )的 相位變更的實施例的振盪器A 1的槪略構成。 振盪器A1，是從振盪器A中除去了上述MPU10以及 兩個D正反器器電路21、22後的裝置。這樣，上述IC1 、IC2分別輸出的訊號的相位，只是由於各IC 1、1C 2的 特性差異而稍微有所偏移。 另外，在振盪器A1中，爲了在充電泵141和142的 輸出電流爲相反極性時限制所流動的電流，從上述1C 1、 IC2分別到迴路濾波器310的訊號路線上設置電阻51、52 〇 進一步，在分別向上述IC 1、IC2 (即分別向上述相 位頻率偵測器1 3 1、1 32 )的電源供給路線上設置濾波器 FI 、 F2 ° 在該振盪器A1中，由於沒有像振盪器A那樣使各 IC1、IC2的輸出訊號的相位偏移，構成各IC1、IC2的元 -18- 1288530 (15) 件的輸出訊號電位（脈衝）大致一起變化。爲此，如果各 元件共用電源直接連接，在各機器中大致一起流入大的脈 衝電流，有可能出現電源電壓依照脈衝下降的現象。該電 壓下降成爲脈衝雜訊。爲此，藉由設置上述濾波器F !、 F2，可以防止産生脈衝雜訊。 在圖6所示的例中，作爲濾波器F1、F2的電路，雖 然採用分別由電阻61、62和電容71、72構成的RC低通 濾波器，但並不限定於此。例如，也可以考慮採用由線圈 和電容構成LC濾波器、或者採用三端子調整器等有源濾 波器等。 圖7是表示振盪器A1的訊號處理中的時序圖。 如圖7所示，充電泵141、142的輸出訊號CPI、CP2 的波形，比虛線所示的本來的時序稍微延遲一些。 1C (積體電路）由數位電路構成。由於數位電路中所 使用的半導體元件的隨機雜訊、或者電源電壓的隨機雜訊 或者變動等的影響，藉由數位電路的訊號的延遲時間在某 種程度的時間間隔內隨機變化。這樣的延遲時間的搖動（ 偏移）稱爲抖動。 圖7所示的CPI、CP2的波形延遲，是由於抖動的影 響，該延遲隨機變化。另外，1C 1、IC2，由於是分別獨立 的電路，分別對CP1以及CP2影響的抖動基本上沒有相 關，對於各個CP1以及CP2分別是隨機的。爲此，由迴 路濾波器310合成後的訊號中的抖動成份是IC1、IC2的 各自的輸出訊號的抖動成份的功率和。 -19· 1288530 (16) 另一方面，對IC1以及IC2供給的ref和RF，由於 完全是相同的訊號，本來的相位比較訊號成份（I C 1以及 IC2的本來的（除去抖動成份）的輸出訊號）是相鎖訊號 。爲此’由迴路濾波器3 1 0合成後的本來的相位比較訊號 成份是CP1以及CP2中本來的相位比較訊號成份的電流 和。 如果對此用對數表示，在由上述迴路濾波器310合成 後的訊號中，抖動成份Noise，根據上述1C的數量N，只 增力□ Noise=10*l〇g(N)。在此，當 N=2 時，只增加 Noise = 3dB 〇 對此，本來的相位比較訊號成份 Signal，只增加 Signal=20*log(N)。在此，當 N=2 時，只增加 Signal = 6dB。 因此，SN比（Signal/Noise )改善了 3dB，相位雜訊 的底部電位改善了 3dB。 這樣，藉由1C (相位頻率偵測器）的並行運行，在 不特別採用高精度的元件的情況下，可以降低相位雜訊。 在上述實施例中，雖然採用兩1C 1、IC2並行運行， 但並不限於此，採用三個以上也可以獲得相同的效果。 依據上述的考慮方法，當採用N個1C (相位頻率偵 測器）並行運行時，相位雜訊的底部電位可以改善 10*log(N) 〇 實際上，在和圖6同樣的構成中，以N=4(4個1C 並行運行）進行實驗，依據圖3所示的習知技術的構成， -20- 1288530 (17) 對於一 95dBc/Hz的相位雜訊的底部電位，改善到一 101dBc/Hz。即，降低相當於10*log(4)=6dB的量相位雜 訊。圖6所示的並行運行的構成，藉由在印刷電路板上配 置多數1C可以容易實現。另外，也可以在1C的封裝中配 置多數積體電路晶片後並聯佈線。這時，隨著積體電路技 術的進步，晶片尺寸也在縮小，並聯更多的晶片成爲可能 〇 例如，如果並聯運行1 6個上述1C，相位雜訊的底部 電位可降低12dB，如果是64個則可降低18dB，如果是 256個則可降低24dB的相位雜訊的底部電位。 圖10〜圖13表示振盪器的相位雜訊的頻譜（RF輸 出的分析結果）的一例，橫軸表示偏離預定的載波頻率的 偏差（截止頻率），縱軸表示相位雜訊的電位。另外’在 曲線中，4個菱形標記（標記編號1〜4 )所表示的繪圖中 ，標記編號1的繪圖部分（截止頻率=10kHz)表示上述 相位頻率偵測器（1 3 1、1 3 2等）本身的相位雜訊的電位 。而標記編號2〜4的繪圖部分，表示上述壓控振盪器 4 1 0的相位雜訊的電位。 在此，圖1 0表示圖3所示的習知技術的振盪器B ( 一個相位頻率偵測器）中相位雜訊的頻譜的一例，圖11 表示將兩個相位頻率偵測器並聯時的振盪器A 1 (參見圖 6)中的相位雜訊的頻譜的一例，圖12表示將三個相位頻 率偵測器並聯時的振盪器中的相位雜訊的頻譜的一例，圖 1 4表示將四個相位頻率偵測器並聯時的振盪器中的相位 -21 - 1288530 (18) 雜訊的頻譜的一例。 在圖1 0〜圖1 3的曲線所示的例中，上述相位頻率偵 測器本身的相位雜訊電位，當相位頻率偵測器爲一個（習 知技術）時爲—99.1 ldBc/Hz，當相位頻率偵測器爲兩個 時爲一 1 03.5 8 dBc/Hz，當相位頻率偵測器爲三個時爲― 1 05.5 9dBc/Hz，當相位頻率偵測器爲四個時爲― 1 0 7.3 0dBc/Hz。該結果也表明，隨著上述相位頻率偵測器 的數量增加，可以更加降低相位雜訊。 另外，作爲防止電源電壓脈衝下降引起的脈衝雜訊的 機構，除了設置上述濾波器F1、F2以外，也可以考慮將 輸入到每個相位頻率偵測器（每個1C)的RF以及REF 的相位微小偏移。 脈衝雜訊的寬度，由於在從ps(l〇_9秒）到nS(10·12秒） 程度的短時間內’只需使分別到1C的訊號佈線長度相差 1〜1 00mm的程度，脈衝雜訊不會相互重疊，可以減少干 擾，其結果，消除了雜訊的相關性，可以降低相位雜訊。 然而，如上述那樣當相位頻率偵測器多數並聯動作時 ，有時會出現相位雜訊降低的狀況分散的情況。 圖1 4表示和圖1 3同樣在使四個相位頻率偵測器並聯 動作的振盪器A 1中’相位雜訊降低的狀況不良時的相位 雜訊頻譜的一例。 在圖1 3、圖1 4所示例中，當使四個相位頻率偵測器 並聯動作時，處於良好狀態時可以改善（降低）到-1 07.3 0dBc/Hz (圖13 )，在狀況差時，只能改善到— -22- 1288530 (19) 1 03.20dBc/Hz (圖 14 )。 這可以推測爲，由於在對各IC1、IC2進行頻率設定 和計數器設定的致動訊號中的鎖存訊號（用於控制各設定 訊號在上述相位頻率偵測器側的讀取時序以及再致動的訊 號）的相位抖動的影響，在上述多數相位頻率偵測器相互 之間的致動時序出現微小的偏差時，上述多數相位頻率偵 測器分別以微小不同的相位作爲目標値動作，其結果，出 現不能充分降低相位雜訊的現象。 另一方面，圖8以及圖9表示圖6所示的振盪器A1 、即兩個相位頻率偵測器1 3 1、1 3 2並聯後的振盪器A 1 的訊號處理中的時序圖的一例。圖8表示向各相位頻率偵 測器13 1、132輸入的分頻後的RF訊號（FN1、FN2 )的 相位差小時的情況的例，圖9表示該相位差大時的例。另 外，在圖8、圖9表示，FR1以及FR2 (向各相位頻率偵 測器輸入的分頻後的REF訊號）相互之間的相位差，雖 然基本上均沒有，但爲向一方的相位頻率偵測器1 3 1輸入 的FR2和FN2之間的相位差，與向另一方的相位頻率偵 測器1 32輸入的FR2和FN2之間的相位差，具有相互相 反方向的相位差時的例。 在圖8和圖9中，藉由比較上述合成控制指令訊號 VLF (上述迴路濾波器310的輸出訊號）可以表明FN1和 FN2之間的相位差（各相位頻率偵測器相互之間的輸入訊 號的相位差）大的一方，上述合成控制指令訊號VLF的 交流成份（凹部）的振幅大。在這樣的狀態下’ RF訊號 -23· 1288530 (20) 的相位雜訊不能充分降低。 但是’即使出現圖1 4或者圖9所示那樣的狀態的情 況’藉由重復一次或者多次對多數相位頻率偵測器的再致 動（重設），可以始終獲得圖1 3或者圖8所示的良好狀 態（相位雜訊充分降低後的狀態）。這可以認爲，在重復 再致動的過程中，由致動訊號引起的再致動的時序的微小 偏差’可能會引起在上述多數相位頻率偵測器相互之間的 致動時序不出現微小偏差的狀態。 圖15是表示具有如下構成的本發明的第一實施例的 振盪器XI的槪略構成方塊圖，即，可以藉由上述合成控 制指令訊號中的交流成份的振幅、或者上述多數相位頻率 偵測器中兩個輸入訊號（FN1和FR1或者FN2和FR2、 以下稱爲FN和F.R )的相鎖訊號（所謂的鎖相訊號）判定 是否可以獲得充分降低的相位雜訊，在獲得充分降低的相 位雜訊之前，重復上述多數相位頻率偵測器的再致動。 振盪器XI，將兩個積體電路IC1、IC2並聯連接，各 IC1、IC2的輸出訊號分別經由電阻51、52後由上述迴路 濾波器3 10進行結合，結合後的合成控制指令訊號VLF 向上述壓控振盪器4 1 0輸出，對於這樣的構成，和上述振 盪器A1 (圖6)同樣。在此，上述壓控振盪器410是振 盪機構的一例。 振盪器XI與上述振盪器A1不同的點在於，各1C 1、 IC2具有偵測向各個上述相位頻率偵測器131、132輸入 的兩個輸入訊號（FN和FR )的相位是否相鎖的鎖相偵測 -24- 1288530 (21) 電路1 6 1、1 62 (鎖偵測機構的一例）‘，進一步，具有偵 測在上述合成控制指令訊號VLF中交流成份的振幅是否 在預定電位以下的振幅偵測電路9 (上述振幅偵測機構的 一例）、分別根據上述鎖相偵測電路1 6 1、1 62以及上述 振幅偵測電路9的偵測結果對上述1C 1、IC2輸出頻率設 定訊號以及重設訊號（即，對上述相位頻率偵測器131、 132的再致動訊號）的致動控制電路7(第一以及第二再 致動機構的一例）。進一步，振盪器X1，在各個鎖相偵 測電路1 61、1 62和致動控制電路7之間，具有只有從所 有的（兩者的）鎖相偵測電路161、1 62鎖相ON訊號（ 表示已經相鎖的訊號）時，才對致動控制電路7輸出ON 訊號（以下成爲全部鎖相ON訊號）的全部鎖相ON偵測 電路8。 鎖相偵測電路1 6 1、1 6 2，包括一般的頻率合成器IC 。其偵測方法雖然根據1C而不同，例如當兩個輸入訊號 FN以及FR的相位差在預定周期（例如5周期）連續、在 預定相位差時間（例如1 5ns )以下（或者預定相位角以 下）時，判定相位相鎖，上述鎖相ON訊號輸出爲ON， 而在其他情況下輸出爲OFF。 全部鎖相ON偵測電路8，具有輸入將所有（兩者） 的鎖相偵測電路1 6 1、1 62的輸出訊號經由電阻元件8 1、 82、1 9結合後的合成訊號和直流恒壓電源1 8的輸出訊號 的比較器20。這樣，只有在所有（兩者）的鎖相偵測電 路161、162的鎖相ON訊號爲ON時，其合成訊號的電位 -25- 1288530 (22) 高於直流恒壓電源1 8的輸出電位，使比較器2 0的輸出爲 ON 〇 作爲由任一個鎖相ON偵測電路沒有偵測到鎖相on 訊號的狀態，例如在相位頻率偵測器1 3 1、1 3 2的每個中 ，出現相反方向的相位偏移（2輸入FN、FR間的相位偏 移）時，對相位頻率偵測器1 3 1、1 3 2在相反方向上進行 相位的偏移修正控制，爲此觀察不向鎖相ON的方向收斂 的狀態。在這樣的狀態下，RF輸出的相位雜訊不能充分 降低。 在此，並聯動作的相位頻率偵測器的數量比較少（例 如在數個的程度）時，一個相位頻率偵測器處於沒有偵測 到上述鎖相ON訊號的狀態，對RF輸出中的相位雜訊影 響大。因此，在所有的相位頻率偵測器處於鎖相ON狀態 之前，希望重復進行再致動（重設）。 但是，相位頻率偵測器的數量多時，由於一個相位頻 率偵測器對相位雜訊的影響變小，即使並不是所有的相位 頻率偵測器處於鎖相ON狀態，只要在使預定數量以上的 相位頻率偵測器處於鎖相ON狀態爲止，重復再致動，就 可以充分降低相位雜訊。 另一方面，振幅偵測電路9，作爲從合成控制指令訊 號VLF中偵測包含在其中的交流成份的振幅電位（圖8、 圖9中的VLF的凹部深度）的電路連接的電阻元件25、 26、電容元件27、30、二極體28、29、和輸入表示抽出 的交流振幅電位的訊號和直流恒壓電源24的輸出訊號的 -26- 1288530 (23) 比較器23。這樣’只有在表示合成控制指令訊號VLF所 具有的交流成份的振幅電位的訊號高於直流恒壓電源24 的輸出電位時，比較器23的輸出才爲ON。 在此，直流恒壓電源24的輸出電位，只要根據並聯 動作的相位頻率偵測器的數量，設定成與獲得最良好的相 位雜訊的RF輸出時的振幅偵測電路9的輸出電位相比略 爲高一些的電位即可。 然後，採用圖1 6的流程圖，對於該振盪器X1接入 電源時的由致動控制電路7進行的IC 1、IC 2的致動以及 再致動的處理順序進行說明。以下，S 1、S2、…表示處理 順序（步驟）的編號， 首先，接入電源後，致動控制電路7，進行預定時間 (例如，100ms )的時間等待（S1 )後，進行針對IC1、 IC2的致動處理（S2 )。在該致動處理中，由致動控制電 路7依次執行對IC1、IC2設定RF輸出的目標頻率（所 需頻率）的頻率設定處理（S21)、和輸出使IC1、IC2的 致動（已經致動時進行重設（再致動））的重設訊號（鎖 存訊號）的計數器重設處理（S 22)。上述目標頻率被設 定後，在 IC1、IC2的內部，對分頻器 111、121、112、 122設定與該設定頻率對應的分頻比。 然後、致動控制電路7，等待經過預定時間（例如 10 0ms )( S3 )後，校對全部鎖相on偵測電路8和振幅 偵測電路9兩方的輸出訊號（S4、S5 )，當沒有偵測到兩 電路8、9均爲ON時（至少其中一方處於OFF狀態）， 1288530 (24) 返回到S 2，對IC 1、IC 2分別進行致動處理（即， 處理）。這樣，再致動相位頻率偵測器1 3 1、1 32 〜S5的處理，在致動（或者重設）後的預定時間 )內在偵測到從兩電路8、9均輸出ON訊號之前 行。 通常，在經過數次〜十數次以內的重設處理後 到從兩電路8、9均輸出ON訊號，進入到正常運 正常運行中，也要校對從上述兩電路8、9輸出的 號是否變成了 OFF訊號（S4、S5 )，如果偵測到 號時，再次執行重設處理（S2 )。 經過以上的重設處理後，進入正常運行時，始 獲得圖1 3所示那樣的充分降低了相位雜訊後的相 偵測器1 1、1 3 2的輸出，進而可以獲得充分降低了 訊的RF輸出（壓控振盪器410的輸出）。 雖然在圖16中沒有示出，當重設處理（S2) 定上限次數後仍然沒有偵測到上述兩電路8、9均 訊號的情況時，也可以考慮執行預定的錯誤處理。 以下，採用圖1 7的流程圖，對由致動控制電j 行的頻率設定處理（S2 1 )的內容進行說明。 在頻率設定處理（S2 1 )中，首先致動控制電 對各1C 1、IC2的設定頻率，設定成超過電源控制 410的可調整範圍的上限頻率（比頻率範圍高）的 定頻率（S31 )。這樣，與該設定頻率對應的分頻 控制器151、 152在分頻器111、 121、 112、 122設 再致動 。該S2 (10 0ms 重復執 ，偵測 行。在 ON訊 OFF訊 終可以 位頻率 相位雜 重復預 爲 ON 洛7進 路7， 振盪器 第一設 比，由 定（以 1288530 (25) 下相同）。 然後，等待預定時間（例如lms ) ( S32 )後，對各 IC1、IC2的設定頻率，設定成不到電源控制振盪器410 的可調整範圍的下限頻率（比頻率範圍低）的第二設定頻 率（S33 )。 進一步，等待預定時間（例如lms) ( S 3 4 )後，對 各IC1、IC2的設定頻率，再次設定成第一設定頻率（S35 )° 然後，等待預定時間（例如lms) ( S 3 6 )後，這次 對各1C 1、IC2的設定頻率，設定成RF輸出訊號的目標 頻率（所需頻率）（S 3 7 )後，等待預定時間（例如1 ms )後，結束頻率設定處理。例如，壓控振盪器410的可調 整範圍爲5990〜6010MHz時，第一設定頻率設定成6025 MHz，第二設定頻率設定成爲5 975MHz，最後設定成可調 整範圍內的預定目標頻率（例如6000MHz)。再次，S31 〜S 3 8的處理是分頻比依次設定機構的處理的一例。 這樣的頻率設定處理（分頻比依次設定處理），在由 上述全部鎖相ON偵測電路進行鎖相ON偵測（圖1 6的 S4)之前執行，RF輸出訊號的頻率，由於在將壓控振盪 器4 1 0的上限以及下限的各頻率鎖定後調整到目標頻率， 可以避免錯誤鎖相的現象。 在圖17所示例中，雖然是先進行第一設定頻率（超 過上限頻率的設定頻率）的設定，但並不限於此，也可以 先進行第二設定頻率的設定。 -29- 1288530 (26) 另外，在圖1 7的例中，第一設定頻率的設定雖然進 行了兩次（S31以及S35)，第二次處理（S35以及S36 )也可以省略。 第二實施例 圖18是表示本發明的第二實施例的振盪器X2的槪 略構成的方塊圖。 振盪器X2，不是如振盪器X 1般，合成控制指令訊號 VLF向一個壓控振盪器410輸出的構成，而是具有與IC1 、IC2相同數量的（即與相位頻率偵測器13 1、1 32相同 數目）迴路濾波器以及壓控振盪器（振盪機構），各1C 1 、IC2和與其分別對應的迴路濾波器311、312以及壓控 振盪器411、412，分別形成獨立的反饋閉迴路後並聯動 作。進一步，由混合器5 (外部輸出合成機構的一例）輸 出將各壓控振盪器411、412的輸出訊號RF1、RF2合成 後的RF輸出向外部輸出。 這樣，藉由採用多數壓控振盪器411、412的輸出合 成後向外部輸出的構成，和本發明之第一實施例（振盪器 X 1 )同樣，可以獲得降低相位雜訊的效果。 即，由於各壓控振盪器411、412的輸出訊號RF1、 RF2中除去雜訊的脈衝訊號本身，分別與REF (參考訊號 )相鎖（相位一致），其合成訊號的訊號電位爲電壓和。 另一方面，由於各壓控振盪器411、412.的輸出訊號 RF1、RF2中的相位抖動或者相位雜訊是隨機的，對其合 1288530 (27) 成後，有時是相加，有時是相抵消。因此，輸出訊號RF 1 、RF2的合成訊號中相位抖動和相位雜訊爲平均功率和。 其結果，提高了 SN比，降低（改善）了 RF輸出的 相位雜訊。理論上，兩個並聯動作時可以改善3dB。 進一步，振盪器X2構成爲，藉由多數相位頻率偵測 器中的兩個輸入訊號（FN和FR )的鎖相訊號判定是否獲 得了充分降低的相位雜訊，在獲得充分降低的相位雜訊之 前，重復進行多數相位頻率偵測器的再致動。具體而言， 和振盪器X1 (圖1 5 )同樣，具有針對相位頻率偵測器 1 3 1、1 3 2的每個的鎖相偵測電路1 6 1、1 62、全部鎖相ON 偵測電路8、對各1C 1、IC2進行頻率設定以及重設訊號 的輸出的致動控制電路7。 致動控制電路7的動作，由於和圖16、圖17所示振 盪器X1的致動控制電路7相同（但是S 5的處理除外） ，在此省略其說明。 振盪器X2，經過由致動控制電路7的重設處理後進 入正常運行時，始終可以獲得圖1 3所示充分降低了相位 雜訊後的相位頻率偵測器1 3 1、1 3 2的輸出，進入可以獲 得充分降低了相位雜訊後的RF輸出（混合器的輸出）。 【圖式簡單說明】 圖1表示本發明之第一實施例的振盪器A的槪略方 塊圖； 圖2表示振盪器A的訊號處理的時序圖； -31 - 1288530 (28) 圖3表示已知振盪器B的槪略方塊圖； 圖4表示振盪器B的訊號處理的時序圖； 圖5表示振盪器B的訊號處理的時序圖； 圖6表示本發明的第一實施例的振盪器A 1的槪略方 塊圖； 圖7表示振盪器A1的訊號處理的時序圖； 圖8表示當介於輸入訊號間之相位差較小時，振盪器 A1的訊號處理的時序圖； 圖9表示當介於輸入訊號間之相位差較大時，振盪器 A1的訊號處理的時序圖； 圖1 〇表示在已知振盪器B中的相位雜訊的頻譜圖； 圖1 1表示包括兩個相位頻率偵測器並聯的振盪器中 的相位雜訊的頻譜圖； 圖1 2表示包括三個相位頻率偵測器並聯的振盪器中 的相位雜訊的頻譜圖； 圖1 3表示包括四個相位頻率偵測器並聯的振盪器中 的相位雜訊的頻譜圖； 圖1 4表示包括四個相位頻率偵測器並聯的振盪器中 相位雜訊降低不充分時的相位雜訊的頻譜圖； 圖15表示本發明的第一實施例的振盪器XI的槪略 方塊圖； 圖1 6表示在振盪器X1中相位頻率偵測器的致動以 及再致動的處理流程圖； 圖17表示在振盪器XI中頻率設定處理的處理流程 -32- (29) 1288530 圖；和 圖18表示本發明的第二實施例的振盪器X2的槪略 方塊圖。 主要元件對照表 150 控制器 100 微處理單元 130 相位頻率偵測器 140 充電泵 300 迴路濾波器 400 壓控振盪器 170 RF輸出端子 160 REF輸入端子 120 分頻器 110 分頻器 10 MPU 13 1 相位頻率偵測器 14 1 充電泵 111 分頻器 12 1 分頻器 132 相位頻率偵測器 15 1 控制器 152 控制器 2 1 D正反器 22 D正反器1288530 (1) Field of the Invention The present invention relates to an oscillator used in a communication device or the like that performs communication using, for example, wireless or wired. [Prior Art] There is an oscillator used in a communication device or the like that performs communication using, for example, wireless or wired, in the prior art. A specific example of such an oscillator will be described with reference to Fig. 3 . The oscillator B of an example of a conventional oscillator has a known phase lock loop (PLL) configuration, and receives a latch signal output by the micro processing unit (MPU) 100 via an internal controller 15 ( LE), DATA signal (DΑΤΑ) and clock signal (CLK) for control. Specifically, the configuration of the oscillator 包括 includes a reference signal (hereinafter abbreviated as “REF”) that can be externally adjusted with high precision by acquiring a reference for output signals for obtaining a desired frequency from the RF output terminal 170, and The actual output signal of the oscillator (hereinafter referred to as "RF") detects the phase difference between the REF and the RF obtained, and outputs a control command for controlling the output signal to a desired frequency according to the detection result. The phase frequency detector of the signal 130, the charge pump 140 for inverting or non-reversing the control command signal outputted by the phase frequency detector 130, and the output of the charge pump 140 The loop filter 300 for controlling the smoothing of the command signal generates a voltage controlled oscillator 400 of the desired frequency based on the control command signal smoothed by the loop filter 300 (output No. -588530 (2)) . In addition, RF is output from the RF output terminal 170, and REF is input from the REF input terminal 160. Although the REF and the RF are signals obtained by the phase frequency detector 130, the two signals are previously divided by the frequency divider 1 10 (for RF) and the frequency divider 120 before being input to the phase frequency detector 130. (For REF) The corresponding signal is divided by a predetermined division ratio. When the periods of REF and RF are the same, it is not necessary to set the frequency dividers 1 10, 120. For the charge pump 140, since the output signal of the phase frequency detector 130 is changed between the positive constant current output, the negative constant current output, or the no output (off) according to the phase difference of the input signal, It can also be omitted. In addition, the frequency synthesizer 1C is a 1C chip integrated by the frequency divider 110, the frequency divider 120, the phase frequency detector 130, the charge pump 140, and the controller 150 in an integrated circuit. An example. The oscillator B thus constructed is obtained, for example, in accordance with the timing shown in Fig. 4 and generates respective signals. For example, REF input from the REF input terminal 160 is divided by the frequency divider 120 (the frequency division ratio r=2 at this time) to form FR1, and on the other hand, the RF output from the voltage controlled oscillator 400 is divided by the above. The frequency division unit 110 (the frequency division ratio R=8 at this time) forms FN1, and the two signals (FR1 and FN1) become the same period, and are acquired by the phase frequency detector 130. The phase frequency detector 130 detects the phase difference between the two received signals (FR 1 1288530 (3) and FN 1 ), and outputs a control command signal according to the phase difference. Further, the charge pump 140 processes the control command signal according to the output control command signal, and the CP 1 of the processed signal is further smoothed by the loop filter 300. Finally, the above-mentioned voltage controlled oscillator 400 outputs RF of a desired frequency according to the signal on which the smoothing process is performed. Here, the processing of the control command signal to the charge pump 140 will be described below. For example, when the phase of FR1 shown in FIG. 4 leads the phase of FN1, the charge pump 140 outputs CP 1 in the form of a positive constant current pulse of a pulse width corresponding to the phase difference. On the other hand, as shown in FIG. 5, when F When the phase of R1 lags behind the phase of FN 1, the charge pump 1404 outputs CP 1 in the form of a negative constant current pulse of a pulse width corresponding to the phase difference. In addition, the output of the charge pump 140 is in an open state during the absence of a pulse. Therefore, the voltage controlled oscillator 400 controls the frequency of the RF to a desired frequency in accordance with the polarity of the constant current pulse of the above CP1 and the pulse width. However, in the wired or wireless communication environment that has been significantly developed in recent years, a high degree of digital modulation has begun to use higher frequencies. For this reason, it is required to reduce the generated phase noise as much as possible in the oscillator B used in the frequency conversion of the digital modulated signal when the digital signal is demodulated. It is known that the phase noise generated by the oscillator B is larger as the division ratio of the above-described frequency dividers 110, 120 is larger. As a concrete experimental result, when the RF output frequency is 6 GHz, (4) 1288530 frequency division ratio N = 2 0 0, and the processing frequency in the phase frequency detector 1 30 is 30 MHz, the bottom potential of the phase noise The degree of -97 dB/Hz (bottom potential refers to the low frequency component of the phase noise observed from the maximum 値 of the RF output frequency, mainly the potential of the phase noise generated by the frequency synthesizer 1C). On the other hand, when the output frequency of the RF is 6 GHz, the division ratio N = 600 00, and the processing frequency in the phase frequency detector 130 is 1 MHz, the bottom potential of the phase noise is -84 dB/Hz. The above experimental results show that when the RF is the same, the larger the division ratio, the more the phase noise increases. For this reason, although it is conceivable to reduce the frequency division ratio of the above-mentioned frequency divider, in reality, since the phase comparison frequency processed by the phase frequency detector 130 has an upper limit (maximum about 56 MHz), the high frequency is processed as described above. When it is necessary to use a frequency divider with a large division ratio, it is difficult to suppress phase noise. On the other hand, in Japanese Laid-Open Patent Publication No. Hei 11-32951, a digital phase comparator with a wide phase-locked range of pl L and a low analog of phase noise are disclosed in the process of non-phase-locked and phase-locked phase of the PLL. The technique used to switch between phase comparators. According to this technique, with a wide phase-locked range, although a phase noise low signal can be obtained, there is still a problem that a high-precision phase comparator capable of realizing the required phase noise is required. SUMMARY OF THE INVENTION Therefore, the present invention is directed to the above-described invention, and its purpose is to -8-1288530 (5) without increasing the actual phase comparison frequency, and particularly without using a high-precision machine. Can reduce phase noise. In order to achieve the above object, in accordance with a first aspect of the present invention, there is provided an oscillator comprising a predetermined oscillating unit for outputting an output signal; and a plurality of phase frequency detectors. Each phase frequency detector detects a phase difference between the two input signals, that is, the output signal of the oscillating unit and the two input signals from the external reference signal, and outputs a control command signal according to the phase difference to output the output The signal is controlled at the desired frequency. The composite control command signal generated by combining a plurality of control command signals output from the plurality of phase frequency detectors is output to the oscillating mechanism. With such a configuration, according to the experimental results, phase noise can be reduced even by using an inexpensive phase frequency detector which is not particularly highly accurate and has an existing performance. In addition, in accordance with a second aspect of the present invention, an oscillator is provided, including a plurality of predetermined oscillating units for outputting a plurality of output signals; and a plurality of phase frequency detectors for detecting two inputs The signal, that is, the phase difference between the output signal of the oscillating unit and the external reference signal, and according to the phase difference, a control command signal is output to control the output signal at a desired frequency; and a combination and output unit is used to combine Most of the output signals output by most of the oscillating units, and output a composite signal. With an oscillator having the same number of oscillating units as the phase frequency detector, the phase noise can be reduced to the same extent as the oscillator in the first aspect of the invention, wherein the composite control command signal is output to a single Oscillating unit. -9 - 1288530 (6) However, when most of the above phase frequency detectors are operated in parallel, phase noise may sometimes be reduced. This can be presumed to be due to the latching signal in the actuation signal for frequency setting and counter setting of the phase frequency detector (the signal for controlling the reading timing of each setting signal on the phase frequency detector side). The influence of the phase jitter occurs when the phase timing of the majority of the phase frequency detectors is slightly different, and the majority of the phase frequency detectors respectively operate with a slightly different phase as a target, and the result appears. The phenomenon of phase noise cannot be sufficiently reduced. Therefore, even in such a case, the phase noise can be always stabilized by repeating the re-actuation (reset) of the above-mentioned majority phase frequency detector one or more times. At a predetermined low level. It can be considered that during the repeated re-actuation, the slight deviation of the timing of the re-actuation caused by the actuation signal may cause the actuation timing of the majority of the phase frequency detectors to be non-small. The state of the deviation. For this reason, whether sufficient phase noise can be obtained, the amplitude of the AC component in the composite control command signal or the phase lock signal of the two input signals in the majority phase frequency detector (so-called phase lock) can be obtained. One or two of the signals are determined, and the re-actuation of the majority of the phase frequency detectors is repeated until a sufficiently reduced phase noise is obtained. Specifically, the oscillator according to the first aspect of the present invention includes: an amplitude detecting mechanism that detects whether an amplitude of an alternating current component in the composite control command signal is less than or equal to a predetermined level; and when the amplitude detecting mechanism is not used The first re-actuating mechanism of the majority-10 - (7) 1288530 phase frequency detector is activated when the amplitude is less than or equal to the predetermined level. In addition, the first or second aspect of the present invention detects whether the two lock phase detecting mechanisms of the plurality of phase frequency detectors are locked; when all or a predetermined time of the plurality of phase frequency detectors are locked by the lock Then, the majority of the phase frequency detectors are activated, so that the phase noise can be stabilized at all times, and the filter is provided in each of the plurality of phase frequency routing routes. According to the present invention, when the majority of the phase frequencies are detected by the potential (pulse) of the output signals of the respective elements, and the components share the power supply, the current is substantially flowing in each of the elements, and there is a possibility that the power supply voltage drops to pulse noise in accordance with the pulse shape. For this reason, noise can be provided by setting the above filter. In addition, the majority of the phase frequency detectors may be provided with a frequency division that divides the phase frequency detector reference signals into predetermined frequency division ratios respectively. By using such a frequency divider, the reference signal may be arbitrarily selected. The combination of the respective division ratios, the output frequency of the configuration meets the desired target frequency. However, when most phase frequency detectors include large virtual signals in parallel signals, sometimes the oscillators that are out of the point, the phase detection mechanism including the input signals are not detected, the number is more than the second lock. Actuation agency. Low level state. When the power detectors of the rate detector operate in parallel, they change roughly together, such as the phenomenon of a large pulse current drop. The voltage prevents the output signal obtained in all or part of the pulse and the setting of the output signal to facilitate the operation of the oscillator, and the output signal including the virtual signal -11 - 1288530 (8) is divided. The phenomenon that the subsequent signal is locked with the reference signal (the frequency-divided signal) is called the phenomenon of so-called false phase locking. At this time, the phase lock may be detected even if the two input signals should not be detected to be locked. To this end, before the phase lock detection by the lock detecting mechanism, the first set frequency exceeding the upper limit frequency and the second setting lower than the lower limit frequency are set in an adjustable range of the oscillation mechanism in a predetermined order. a frequency dividing ratio order setting mechanism of a frequency divider ratio of a frequency divider corresponding to an output signal of a desired frequency, such as a frequency equal to a frequency ratio of two frequency dividers corresponding to the output signal. Thus, the frequency of the output signal can be prevented from being erroneously phase-locked by locking the respective frequencies of the upper and lower limits of the oscillating unit to the desired frequency (target frequency). [Embodiment] Hereinafter, embodiments and modifications of the present invention will be described with reference to the accompanying drawings in order to facilitate the understanding of the invention. Further, the following examples and modifications are merely examples of the invention and do not limit the technical scope of the invention. First Embodiment A schematic configuration of an oscillator A according to a first embodiment of the present invention will be described with reference to Fig. 1 . The oscillator A is roughly composed of an integrated body -12· 1288530 (9) circuit IC1 and IC2 having functions such as a phase frequency detector, and the IC1 and IC2 are processed together to form a PLL and generate RF (output signal). The voltage controlled oscillator 410 is composed of an MPU 10 that controls the IC 1 and IC 2 . Here, first, the schematic configuration of 1C 1 will be described. The schematic configuration of 1C 1 includes a phase frequency detector 1 3 1 and a charge pump 1 4 1 . The phase frequency detector 1 31 receives REF, which is a REF, and RF, which is externally adjusted with high precision for obtaining a reference of an output signal of a desired frequency from the RF output terminal 170, which is actually output by the oscillator A. RF. The phase frequency detector 1 3 1 detects the phase difference between the two input signals of REF and RF (specifically, the signals FR and FN divided by the frequency dividers 111 and 121 described later), and according to The detection result outputs a control command signal for controlling the output signal to a desired frequency. The charge pump 14 4 processes the control command signal outputted by the phase frequency detector 1 3 1 based on the phase difference. In addition, 1C 1 includes a frequency divider 111CRF having a frequency divider for dividing REF and RF which are input (acquired) to the phase frequency detector 1 3 1 in advance according to a predetermined frequency dividing ratio, and a frequency divider 121 (REF) use). The two signals are separately divided by the frequency divider to generate two signals of the same period (FN1, FR1, see Fig. 2). Further, if the periods of the above REF and RF are the same, it is not necessary to provide the above-described frequency dividers 111, 121. Further, IC1 has a charge pump 141 that outputs a positive or negative constant current pulse based on the output signal of the phase frequency detector 131. However, the charge pump can also be omitted. -13- 1288530 (10) In addition, for IC2, the component having the same function as IC1 is different from 1C1, so that the first bit of the symbol is "2" (for example, the phase frequency detector of 1C 1 is ' At 1 3, the phase frequency detector of IC2 is 132). The IC1 and IC2 configured as described above are controlled by the MPU 10 for controlling the IC1 and the IC2. Specifically, the MPU 10 controls the IC1 and the IC2 by transmitting a latch signal (LE), a DATA signal (DATA), and a clock signal (CLK) to the controller 150 provided inside the IC1 and IC2. In particular, for the oscillator A, by using the two D flip-flop circuits 21, 22, the latch signals are input to the controllers 151, 152 of IC1 and IC2 at different times. Therefore, the time at which IC1 and IC2 start to operate is different. Specifically, as shown in FIG. 2, the operation start time of the frequency dividers 1 1 1 and 121 of the IC 1 is earlier than the operation start time of the frequency dividers 1 12 and 122 of the IC 2, and one cycle of the REF waveform is advanced. Set to phase advance (for example, the rising edge of FR1 is one phase longer than the rising edge of FR2. The above-mentioned D flip-flop circuits 21 and 22 are used for each phase frequency detector (each 1C). An example of the phase change mechanism of the RF and REF phases shifted by a predetermined amount. The operation performed by the oscillator A configured as described above will be described with reference to Figs. 1 and 2. First, after the operation of the oscillator A is started, the MPU 10 Transmitting the latch signal -1488530 (11) (LE), the transmitted LE is delayed by the above two D flip-flop circuits 21, 22, and input to the controller 151, 152 of IC1 and IC2. As described above, the operation start time of the D1 flip-flop circuits 21 and 22, IC1 and IC2 is set to one cycle of the phase difference REF waveform, and the IC2 starts operating after 1C1 starts operating. Here, first, IC1 is started. The operation is explained. First, the RE input from the REF input terminal 160 F, the frequency division is performed by the frequency divider 121 (the frequency division ratio R = 2 at this time) to form FR1, and on the other hand, the RF outputted from the voltage controlled oscillator 410 is divided by the frequency divider 111 (the frequency division ratio R at this time) = 8 ) After FN1 is formed, the above two signals (FR1 and FN 1 ) become the same period and are input to the phase frequency detector 1 3 1. Phase frequency detector 1 3 1 pairs the two signals input (FR1 And FN 1 ) detecting a phase difference between each other, and outputting a control command signal according to the phase difference. Further, the charge pump 14 4 processes the control command signal according to the output control command signal, and the processed signal CP1 is further processed. The smoothing process is performed by the loop filter 310. Next, the operation of the IC 2 will be described. Further, although IC2 and IC1 operate in the same manner, the operation start time is started after one cycle of the delayed REF waveform as described above. First, the ref input from the REF input terminal 160 is divided by the frequency divider 122 (the frequency division ratio R = 2 at this time) to form FR2, and the RF output from the voltage controlled oscillator 410 is divided by the frequency divider. Divided by 112 (this time -15-1288530 (12)'s division ratio R = 8 ) After FN2 is formed, the above two signals (FR2 and FN2) become the same period and are input to the phase frequency detector 1 3 2. The phase frequency detector 1 3 2 pairs the two signals input ( FR2 and FN2) detect the phase difference between each other, and output a control command signal according to the phase difference. Further, the charge pump 1 42 processes the control command signal according to the output control command signal, and further processes the processed signal CP2 further. The smoothing process is performed by the loop filter 310. Then, CP1 and CP2 output from IC1 and IC2 are input to the loop filter 3 1 0, and are synthesized while smoothing the signal waveform. The following describes CP1 and CP2. The timing at which CP1 and CP2 are input to the loop filter 310 is as shown in Fig. 2. Fig. 2 shows that CP1 and CP2 are output from IC1 and IC2 in accordance with one cycle of the REF waveform, and are input to the loop filter 310. In this way, the output timings of CP1 and CP2 are alternated according to one cycle of the REF waveform, in order to respectively have the action start times of IC1 and IC2 of the phase frequency detectors 1 3 1 and 1 32, as described above, offset the REF waveform. The phase of one cycle amount. Therefore, the loop filter 301 generates a new signal Cp by simply synthesizing the phase-shifted CP 1 and CP2, and controls the voltage-controlled oscillator 410 by transmitting to the voltage-controlled oscillator 410 that finally outputs the RF. . However, the frequency of the CP generated by the above-described loop filter 310 is twice the frequency of CP1 or CP2 -16-1288530 (13) due to the simple synthesis of CP1 and CP2 (and the number of phase frequency detectors) The proportional increase)) The phase frequency detector's operating frequency as viewed from the oscillator A as a whole is increased by a factor of two. That is, the loop filter 301 is an example of a control command synthesizing mechanism that synthesizes the control command signals outputted by each of the phase frequency detectors. Therefore, the oscillator A is composed of the oscillator B of the prior art. When two identical phase frequency detectors having the same frequency dividing ratio are formed, compared with the oscillator B, a control signal for imagining phase comparison at twice the frequency of the oscillator B can be input to the voltage controlled oscillator 4 1 0 CP. On the other hand, the phase noise of CP1 and CP2 is basically random, and the synthesized part cancels each other. The phase noise of the synthesized control command signal does not increase with the number of the majority of the phase frequency detectors. In theory, there are only 2) times. As a result, phase noise (lower S/N ratio) can be reduced by using an inexpensive phase frequency detector with current performance. Variations In the above embodiment, although the case where the oscillator A outputs the control signal CP at twice the frequency of the oscillator B of the prior art is explained, for example, if three D flip-flop circuits, three and the above When the integrated circuit of IC1 and the frequency division ratio of the three REF dividers constitute an oscillator, the control signal CP can be output at a frequency three times that of the conventional oscillator B. Therefore, by using the D flip-flop The number of circuits, the number of -17-1288530 (14) of the integrated circuit, and the division ratio of the REF divider are integer multiples to form an oscillator, and the control signal CP can be output at an integer multiple of the above oscillator B. Further, the above-mentioned means as the output RF is shown as a voltage controlled oscillator. If the control signal output from the loop filter 310 is a current 値, a current controlled oscillator can also be used. Further, in the above embodiment, although it is shown that the phase of the RF and REF of each phase frequency detector (each I c ) is shifted by a predetermined amount by using the above-described D flip-flop circuits 2 1 and 2 2 It is also possible not to change such a phase. Fig. 6 shows a schematic configuration of an oscillator A 1 of an embodiment in which phase change of each phase frequency detector (each ic) is not performed. The oscillator A1 is a device in which the MPU 10 and the two D flip-flop circuits 21 and 22 are removed from the oscillator A. Thus, the phases of the signals output by IC1 and IC2 are slightly shifted due to the difference in characteristics of ICs 1 and 1C 2 . Further, in the oscillator A1, in order to limit the current flowing when the output currents of the charge pumps 141 and 142 are opposite polarities, the resistors 51, 52 are placed on the signal path from the above 1C1, IC2 to the loop filter 310, respectively. Further, filters FI and F2 are respectively disposed on the power supply routes of the IC 1 and IC 2 (i.e., to the phase frequency detectors 1 3 1 and 1 32, respectively). In the oscillator A1, since there is no oscillation like As in the case of the device A, the phase of the output signals of the ICs 1 and IC2 is shifted, and the output signal potential (pulses) of the elements -18 to 1288530 (15) constituting each IC1 and IC2 are substantially changed together. For this reason, if the components are directly connected to the power supply, a large pulse current flows in substantially all of the machines, and there is a possibility that the power supply voltage drops in accordance with the pulse. This voltage drop becomes pulse noise. For this reason, by setting the above filters F!, F2, it is possible to prevent generation of pulse noise. In the example shown in Fig. 6, although the RC low-pass filter including the resistors 61 and 62 and the capacitors 71 and 72 is used as the circuits of the filters F1 and F2, the present invention is not limited thereto. For example, an LC filter composed of a coil and a capacitor, or an active filter such as a three-terminal regulator may be used. Fig. 7 is a timing chart showing signal processing of the oscillator A1. As shown in FIG. 7, the waveforms of the output signals CPI, CP2 of the charge pumps 141, 142 are slightly delayed from the original timing shown by the broken line. 1C (integrated circuit) consists of a digital circuit. The delay time of the signal by the digital circuit varies randomly over a certain period of time due to the random noise of the semiconductor component used in the digital circuit or the random noise or variation of the power supply voltage. The shaking (offset) of such delay time is called jitter. The waveform delays of CPI and CP2 shown in Fig. 7 are due to the influence of jitter, which varies randomly. In addition, since 1C 1 and IC2 are independent circuits, the jitters affecting CP1 and CP2 are basically not related, and are random for each of CP1 and CP2. For this reason, the jitter component in the signal synthesized by the loop filter 310 is the power sum of the jitter components of the respective output signals of IC1 and IC2. -19· 1288530 (16) On the other hand, the ref and RF supplied to IC1 and IC2 are completely identical signals, and the original phase comparison signal components (the original (excluding jitter components) output signals of IC 1 and IC2) ) is a phase lock signal. For this reason, the original phase comparison signal component synthesized by the loop filter 3 1 0 is the current sum of the original phase comparison signal components in CP1 and CP2. If this is represented by a logarithm, in the signal synthesized by the above-described loop filter 310, the jitter component Noise is energized by the number N of the above 1C, and only the force □ Noise = 10 * l 〇 g (N). Here, when N=2, only Noise = 3dB is added. For this, the original phase comparison signal component Signal only increases Signal=20*log(N). Here, when N=2, only Signal = 6dB is added. Therefore, the SN ratio (Signal/Noise) is improved by 3 dB, and the bottom potential of the phase noise is improved by 3 dB. Thus, by the parallel operation of the 1C (phase frequency detector), phase noise can be reduced without particularly using high-precision components. In the above embodiment, although two 1C 1 and IC 2 are operated in parallel, the present invention is not limited thereto, and the same effect can be obtained by using three or more. According to the above considerations, when N 1C (phase frequency detectors) are operated in parallel, the bottom potential of the phase noise can be improved by 10*log(N). In fact, in the same configuration as in FIG. 6, N=4 (4 1C parallel operation) experiments were carried out according to the composition of the prior art shown in Fig. 3, -20-1283530 (17) For a bottom potential of a 95 dBc/Hz phase noise, improved to 101 dBc/ Hz. That is, the amount of phase noise equivalent to 10*log(4)=6dB is reduced. The configuration of the parallel operation shown in Fig. 6 can be easily realized by arranging a majority of 1C on a printed circuit board. Alternatively, a plurality of integrated circuit wafers may be arranged in a 1C package and then connected in parallel. At this time, with the advancement of integrated circuit technology, the size of the wafer is also shrinking, and it is possible to connect more wafers in parallel. For example, if 16 1 1Cs are operated in parallel, the bottom potential of the phase noise can be reduced by 12 dB, if it is 64 It can be reduced by 18dB, and if it is 256, the bottom potential of the phase noise of 24dB can be reduced. Figs. 10 to 13 show an example of the spectrum of the phase noise of the oscillator (analysis result of the RF output), in which the horizontal axis represents the deviation (cutoff frequency) from the predetermined carrier frequency, and the vertical axis represents the potential of the phase noise. In addition, in the graph represented by the four diamond marks (mark numbers 1 to 4) in the curve, the drawing portion (cutoff frequency = 10 kHz) of the mark number 1 indicates the above-described phase frequency detector (1 3 1 , 1 3 2 Etc.) The potential of the phase noise itself. The drawing portions of the mark numbers 2 to 4 indicate the potential of the phase noise of the voltage controlled oscillator 4 10 . Here, FIG. 10 shows an example of the spectrum of the phase noise in the oscillator B (a phase frequency detector) of the prior art shown in FIG. 3, and FIG. 11 shows the case where the two phase frequency detectors are connected in parallel. An example of the spectrum of the phase noise in the oscillator A 1 (see FIG. 6), and FIG. 12 shows an example of the spectrum of the phase noise in the oscillator when the three phase frequency detectors are connected in parallel, and FIG. The phase of the oscillator in the phase of the four phase frequency detectors in parallel - 2188530 (18) An example of the spectrum of the noise. In the example shown in the graph of Fig. 10 to Fig. 13, the phase noise potential of the phase frequency detector itself is -99 when the phase frequency detector is one (known technique). 1 ldBc/Hz, when the phase frequency detector is two, it is a 1 03. 5 8 dBc/Hz, when the phase frequency detector is three, it is -1 05. 5 9dBc/Hz, when the phase frequency detector is four, it is ― 1 0 7. 3 0dBc/Hz. This result also shows that as the number of phase frequency detectors described above increases, phase noise can be further reduced. In addition, as a mechanism for preventing pulse noise caused by a drop in the power supply voltage pulse, in addition to the above-described filters F1 and F2, the phases of RF and REF input to each phase frequency detector (each 1C) may be considered. Minor offset. The width of the pulse noise, because of the short period of time from ps (l〇_9 seconds) to nS (10·12 seconds), it is only necessary to make the length of the signal wiring to 1C differ by 1 to 100 mm. The noise does not overlap each other, which can reduce interference. As a result, the correlation of noise is eliminated, and phase noise can be reduced. However, as described above, when the phase frequency detectors are mostly operated in parallel, the situation in which the phase noise is reduced may be dispersed. Fig. 14 shows an example of the phase noise spectrum when the state of the phase noise reduction in the oscillator A 1 in which the four phase frequency detectors are operated in parallel is the same as in Fig. 13. In the example shown in Figure 13 and Figure 14, when the four phase frequency detectors are operated in parallel, they can be improved (decreased) to -1 07 when in good condition. 3 0dBc/Hz (Fig. 13), when the condition is poor, it can only be improved to - 22 - 1288530 (19) 1 03. 20dBc/Hz (Figure 14). This can be presumed to be due to the latching signal in the actuation signal for frequency setting and counter setting of each IC1 and IC2 (for controlling the reading timing of each setting signal on the phase frequency detector side and re-actuating) The influence of the phase jitter on the phase jitter of the majority of the phase frequency detectors, the majority of the phase frequency detectors respectively operate with a slightly different phase as a target, and the result There is a phenomenon that phase noise cannot be sufficiently reduced. On the other hand, FIG. 8 and FIG. 9 show an example of a timing chart in the signal processing of the oscillator A1 shown in FIG. 6, that is, the oscillator A1 in which the two phase frequency detectors 1 3 1 and 1 3 2 are connected in parallel. . Fig. 8 shows an example in which the phase difference between the divided RF signals (FN1, FN2) input to the phase frequency detectors 13 1 and 132 is small, and Fig. 9 shows an example in which the phase difference is large. In addition, FIG. 8 and FIG. 9 show that the phase difference between FR1 and FR2 (the divided REF signal input to each phase frequency detector) is substantially neither, but is a phase frequency to one side. The phase difference between FR2 and FN2 input from the detector 1 31 and the phase difference between FR2 and FN2 input to the other phase frequency detector 1 32 have an opposite phase difference. . In FIG. 8 and FIG. 9, the phase difference between FN1 and FN2 can be indicated by comparing the synthesized control command signal VLF (the output signal of the loop filter 310) (the input signals between the phase frequency detectors) The larger the phase difference is, the larger the amplitude of the AC component (concave portion) of the composite control command signal VLF is. In this state, the phase noise of the RF signal -23· 1288530 (20) cannot be sufficiently reduced. However, 'even if there is a state as shown in FIG. 14 or FIG. 9', by repeating the reset (reset) of the majority of the phase frequency detectors one or more times, FIG. 13 or FIG. 8 can always be obtained. The good state shown (the state in which the phase noise is sufficiently reduced). It can be considered that during the repeated re-actuation, the slight deviation of the timing of the re-actuation caused by the actuation signal may cause the timing of the actuation of the majority of the phase-frequency detectors to be small. The state of the deviation. Figure 15 is a block diagram showing a schematic configuration of an oscillator XI of a first embodiment of the present invention having the following configuration, i.e., the amplitude of an alternating current component in the composite control command signal or the majority of the phase frequency detection Two input signals in the device (FN1 and FR1 or FN2 and FR2, hereinafter referred to as FN and F. The phase-locked signal of R) (so-called phase-locked signal) determines whether sufficiently reduced phase noise can be obtained, and the re-actuation of most of the phase frequency detectors is repeated before sufficiently reduced phase noise is obtained. The oscillator XI connects the two integrated circuits IC1 and IC2 in parallel, and the output signals of the IC1 and IC2 are respectively combined by the loop filter 3 10 via the resistors 51 and 52, and the combined composite control command signal VLF is applied to the above. The voltage controlled oscillator 4 10 0 is output, and such a configuration is the same as that of the above-described oscillator A1 (FIG. 6). Here, the voltage controlled oscillator 410 is an example of an oscillating mechanism. The oscillator XI is different from the oscillator A1 described above in that each of the 1C1 and IC2 has a lock for detecting whether the phases of the two input signals (FN and FR) input to the respective phase frequency detectors 131 and 132 are locked. Phase detection -24 - 1288530 (21) Circuit 1 6 1 , 1 62 (an example of a lock detection mechanism)', further, detecting whether the amplitude of the AC component in the composite control command signal VLF is below a predetermined potential The amplitude detecting circuit 9 (an example of the amplitude detecting mechanism) respectively sets the frequency setting signal to the 1C 1 and IC 2 according to the detection results of the phase locking detecting circuits 1 6 1 and 1 62 and the amplitude detecting circuit 9 respectively. And an actuation control circuit 7 (an example of the first and second re-actuation mechanisms) that resets the signals (ie, the re-actuation signals to the phase frequency detectors 131, 132). Further, the oscillator X1, between each of the phase lock detecting circuits 1 61, 1 62 and the actuation control circuit 7, has only the phase lock detection circuit 161, 1 62 from all (the two) phase lock ON signals When it is (indicating that the signals have been interlocked), all the phase-locked ON detecting circuits 8 that output the ON signals (hereinafter referred to as all the phase-locked ON signals) are output to the actuation control circuit 7. The phase lock detection circuit 1 6 1 , 1 6 2 includes a general frequency synthesizer IC. The detection method differs according to 1C, for example, when the phase difference between the two input signals FN and FR is continuous for a predetermined period (for example, 5 cycles), and is less than a predetermined phase difference time (for example, 15 ns) (or less than a predetermined phase angle). When the phase is locked, the phase-locked ON signal output is ON, and in other cases, the output is OFF. All of the phase-locked ON detection circuits 8 have integrated signals and DC constants that combine the output signals of all (both) phase-locked detection circuits 1 6 1 and 1 62 via the resistance elements 8 1 , 82 , and 19 . A comparator 20 that presses the output signal of the power supply 18. Thus, only when the phase-locked ON signals of all (both) phase-locked detection circuits 161, 162 are ON, the potential of the synthesized signal -2588530 (22) is higher than the output potential of the DC constant-voltage power supply 18. The output of the comparator 20 is turned ON as a state in which no phase-locked on signal is detected by any of the phase-locked ON detecting circuits, for example, in each of the phase frequency detectors 1 3 1 and 1 3 2 When the phase shift in the opposite direction occurs (2 input FN, phase shift between FRs), the phase frequency detectors 1 3 1 and 1 3 2 perform phase offset correction control in the opposite direction. A state that does not converge toward the direction in which the phase lock is ON. In such a state, the phase noise of the RF output cannot be sufficiently reduced. Here, when the number of phase frequency detectors in parallel operation is relatively small (for example, at a certain degree), a phase frequency detector is in a state in which the phase-locked ON signal is not detected, and the phase in the RF output is The noise has a big impact. Therefore, it is desirable to repeat the re-actuation (reset) before all phase frequency detectors are in the phase-locked ON state. However, when the number of phase frequency detectors is large, since the influence of one phase frequency detector on phase noise is small, even if not all phase frequency detectors are in a phase-locked ON state, as long as the predetermined number is exceeded When the phase frequency detector is in the phase-locked ON state, repeated phase re-actuation can completely reduce the phase noise. On the other hand, the amplitude detecting circuit 9 is a circuit-connected resistive element 25 that detects the amplitude potential (the recess depth of the VLF in FIGS. 8 and 9) of the AC component contained therein from the combined control command signal VLF, 26. Capacitor elements 27, 30, diodes 28, 29, and a comparator 23 for inputting a signal indicating the extracted AC amplitude potential and an output signal of the DC constant voltage source 24 -26-1288530 (23). Thus, the output of the comparator 23 is ON only when the signal indicating the amplitude potential of the AC component of the composite control command signal VLF is higher than the output potential of the DC constant voltage source 24. Here, the output potential of the DC constant voltage power supply 24 is set to be equal to the output potential of the amplitude detecting circuit 9 when the RF output of the best phase noise is obtained, based on the number of phase frequency detectors operating in parallel. A little higher potential can be. Next, the processing procedure of the actuation and reactivation of the IC 1 and IC 2 by the actuation control circuit 7 when the oscillator X1 is powered on will be described with reference to the flowchart of Fig. 16. Hereinafter, S1, S2, ... indicate the number of the processing sequence (step). First, after the power is turned on, the control circuit 7 is actuated to wait for a predetermined time (for example, 100 ms) (S1), and then for IC1. Actuation processing of IC2 (S2). In the actuation processing, the frequency setting processing (S21) of setting the target frequency (required frequency) for setting the RF output to IC1 and IC2 is sequentially performed by the actuation control circuit 7, and the actuation of the IC1 and IC2 is outputted (already The counter reset processing (S 22) of the reset signal (latching signal) of resetting (re-actuating) is performed. After the target frequency is set, the frequency division ratios corresponding to the set frequency are set to the frequency dividers 111, 121, 112, and 122 in IC1 and IC2. Then, the control circuit 7 is actuated, and after waiting for a predetermined time (for example, 10 0 ms) (S3), the output signals (S4, S5) of both the phase lock on detection circuit 8 and the amplitude detection circuit 9 are collated, when there is no When it is detected that both circuits 8 and 9 are ON (at least one of them is in the OFF state), 1288530 (24) returns to S 2, and the IC 1 and IC 2 are respectively subjected to actuation processing (ie, processing). Thus, the processing of the phase frequency detectors 1 3 1 , 1 32 to S5 is actuated again, and before the ON signals are output from both circuits 8 and 9 within a predetermined time after actuation (or reset) . Usually, after a reset process of several times to ten times or less, the ON signal is output from both circuits 8 and 9, and the normal operation is performed, and the number output from the above two circuits 8 and 9 is also checked. It becomes an OFF signal (S4, S5), and if a number is detected, the reset processing (S2) is executed again. After the above resetting process, when the normal operation is completed, the output of the phase detectors 1 1 and 1 3 2 after the phase noise is sufficiently reduced as shown in FIG. 13 is obtained, and the signal can be sufficiently reduced. RF output (output of voltage controlled oscillator 410). Although not shown in Fig. 16, when the case where the two circuits 8 and 9 are not detected after the reset processing (S2) has been determined for the upper limit number, it is also conceivable to perform predetermined error processing. Hereinafter, the content of the frequency setting process (S2 1 ) by the actuation control circuit will be described using the flowchart of FIG. In the frequency setting process (S2 1 ), the set frequency of each of the 1C 1 and IC 2 is first actuated, and the set frequency exceeding the upper limit frequency (higher than the frequency range) of the adjustable range of the power supply control 410 is set (S31). . Thus, the frequency dividing controllers 151, 152 corresponding to the set frequency are re-actuated in the frequency dividers 111, 121, 112, 122. The S2 (10 0ms repetition, detection line. In the ON signal OFF end can be bit frequency phase miscellaneous repeat pre-ON ON Luo 7 way 7, the first setting of the oscillator, by the fixed (with the same under 1288530 (25)) Then, after waiting for a predetermined time (for example, lms) (S32), the set frequency of each of IC1 and IC2 is set to a second setting that is less than the lower limit frequency (lower than the frequency range) of the adjustable range of the power supply control oscillator 410. Frequency (S33) Further, after waiting for a predetermined time (for example, lms) (S 3 4 ), the set frequency of each of IC1 and IC2 is again set to the first set frequency (S35). Then, waiting for a predetermined time (for example, lms) (S 3 6 ), after setting the set frequency of each 1C 1 and IC 2 to the target frequency (required frequency) of the RF output signal (S 3 7 ), wait for a predetermined time (for example, 1 ms), and then end the frequency. For example, when the adjustable range of the voltage controlled oscillator 410 is 5990~6010MHz, the first set frequency is set to 6025 MHz, the second set frequency is set to 5 975 MHz, and finally set to a predetermined target frequency within the adjustable range ( E.g. 6000MH z). Again, the processing of S31 to S3 8 is an example of the processing of the frequency division ratio setting means. Such frequency setting processing (frequency division ratio setting processing) is performed by all the phase lock ON detecting circuits described above. Before the phase ON detection (S4 of Fig. 16) is executed, the frequency of the RF output signal can be prevented from being erroneously phase-locked by adjusting the frequency to the target frequency after locking the upper and lower limits of the voltage controlled oscillator 4 10 0. In the example shown in Fig. 17, the first set frequency (the set frequency exceeding the upper limit frequency) is set first, but the second set frequency may be set first. -29- 1288530 ( 26) In the example of Fig. 17, the setting of the first set frequency is performed twice (S31 and S35), and the second processing (S35 and S36) may be omitted. Fig. 18 is a view showing the second embodiment. A block diagram of a schematic configuration of the oscillator X2 of the second embodiment of the present invention. The oscillator X2, instead of the oscillator X1, synthesizes the output of the control command signal VLF to a voltage controlled oscillator 410, but has Same as IC1 and IC2 a number (ie, the same number of phase frequency detectors 13 1 and 1 32) loop filter and a voltage controlled oscillator (oscillation mechanism), each of 1C 1 , IC2 and their corresponding loop filters 311, 312 and voltage control The oscillators 411 and 412 respectively form an independent feedback closed loop and then operate in parallel. Further, the mixer 5 (an example of an external output synthesizing mechanism) outputs the combined output signals RF1 and RF2 of the voltage controlled oscillators 411 and 412. The RF output is output to the outside. Thus, by using the configuration in which the output of the majority of the voltage controlled oscillators 411, 412 is combined and output to the outside, the effect of reducing the phase noise can be obtained in the same manner as the first embodiment (the oscillator X 1 ) of the present invention. That is, since the pulse signals themselves of the output signals RF1 and RF2 of the voltage controlled oscillators 411 and 412 are respectively locked with the REF (reference signal), the signal potential of the synthesized signal is the voltage sum. On the other hand, due to the respective voltage controlled oscillators 411, 412. The output signal RF1, RF2 phase jitter or phase noise is random, and after it is combined with 1288530 (27), it is sometimes added, sometimes offset. Therefore, the phase jitter and phase noise in the synthesized signal of the output signals RF 1 and RF 2 are the average power sum. As a result, the SN ratio is increased and the phase noise of the RF output is reduced (improved). In theory, two parallel improvements can improve 3dB. Further, the oscillator X2 is configured to determine whether the phase noise is sufficiently reduced by the phase-locked signals of the two input signals (FN and FR) in the plurality of phase frequency detectors, and obtain sufficiently reduced phase noise. Previously, the reactivation of most phase frequency detectors was repeated. Specifically, as with the oscillator X1 (FIG. 15), the phase-locked detection circuits 1 6 1 and 1 62 for each of the phase frequency detectors 1 3 1 and 1 3 2 are all phase-locked ON detection. The measuring circuit 8 and the actuation control circuit 7 for frequency setting and resetting the output of each of 1C1 and IC2. The operation of the actuation control circuit 7 is the same as that of the actuation control circuit 7 of the oscillator X1 shown in Figs. 16 and 17 (except for the processing of S 5), and the description thereof is omitted here. The oscillator X2, after being reset by the reset control circuit 7, enters the normal operation, and can always obtain the phase frequency detectors 1 3 1 and 1 3 2 after the phase noise is sufficiently reduced as shown in FIG. Output, enter the RF output (mixer output) after the phase noise is sufficiently reduced. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of an oscillator A according to a first embodiment of the present invention; FIG. 2 is a timing chart showing signal processing of an oscillator A; -31 - 1288530 (28) FIG. FIG. 4 is a timing chart showing the signal processing of the oscillator B; FIG. 5 is a timing chart showing the signal processing of the oscillator B; and FIG. 6 is a view showing the oscillator A of the first embodiment of the present invention. Figure 1 shows the timing diagram of the signal processing of the oscillator A1; Figure 8 shows the timing diagram of the signal processing of the oscillator A1 when the phase difference between the input signals is small; Figure 9 shows Timing diagram of signal processing of oscillator A1 when the phase difference between input signals is large; Figure 1 shows the spectrum of phase noise in known oscillator B; Figure 1 shows the phase frequency including two phases. Spectrogram of phase noise in the oscillator connected in parallel with the detector; Figure 1 2 shows the spectrum of the phase noise in the oscillator including three phase frequency detectors in parallel; Figure 13 shows the four phase frequencies Frequency of phase noise in the oscillator connected in parallel with the detector Figure 14 is a frequency spectrum diagram showing phase noise when the phase noise is insufficiently reduced in an oscillator including four phase frequency detectors in parallel; Figure 15 is a diagram showing the oscillator XI of the first embodiment of the present invention. Figure 16 shows the flow chart of the actuation and re-actuation of the phase frequency detector in the oscillator X1; Figure 17 shows the processing flow of the frequency setting process in the oscillator XI -32- (29) 1288530; and FIG. 18 is a schematic block diagram of the oscillator X2 of the second embodiment of the present invention. Main component comparison table 150 Controller 100 Micro processing unit 130 Phase frequency detector 140 Charge pump 300 Loop filter 400 Voltage controlled oscillator 170 RF output terminal 160 REF input terminal 120 Frequency divider 110 Divider 10 MPU 13 1 Phase Frequency detector 14 1 charge pump 111 frequency divider 12 1 frequency divider 132 phase frequency detector 15 1 controller 152 controller 2 1 D flip-flop 22 D flip-flop
-33- 1288530 (30) 4 10 壓控振盪器 3 10 迴路濾波器 122 分頻器 112 分頻器 132 相位頻率偵測器 142 充電泵 5 1 電阻 52 電阻 61 電阻 62 電阻 7 1 電容 72 電容 16 1 鎖相偵測電路 162 鎖相偵測電路 9 振幅偵測電路 7 致動控制電路 8 全部鎖相ON偵測電路 81 、 82 、 19 電阻元件 18 電流恆壓電源 25、26 電阻元件 27、30 電容元件 28、29 二極體 23、20 比較器 24 直流恆壓電源-33- 1288530 (30) 4 10 Voltage Controlled Oscillator 3 10 Loop Filter 122 Divider 112 Divider 132 Phase Frequency Detector 142 Charge Pump 5 1 Resistor 52 Resistor 61 Resistor 62 Resistor 7 1 Capacitor 72 Capacitor 16 1 phase lock detection circuit 162 phase lock detection circuit 9 amplitude detection circuit 7 actuation control circuit 8 all phase lock ON detection circuit 81, 82, 19 resistance element 18 current constant voltage power supply 25, 26 resistance element 27, 30 Capacitance Element 28, 29 Diode 23, 20 Comparator 24 DC Constant Voltage Power Supply
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