JP4064245B2 - CMOS integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
This invention , C The present invention relates to a MOS integrated circuit.
[0002]
[Prior art]
In the CMOS integrated circuit, for example, as shown in Non-Patent Document 1, a CMOS inverter circuit is used. In this CMOS integrated circuit, when the input terminal of the logic signal is in an open state, the potential becomes unstable, so that the state of the internal logic circuit becomes indefinite and cannot be controlled. In the intermediate potential state, a through current flows through the CMOS inverter circuit, resulting in an increase in current consumption.
[0003]
Therefore, conventionally, the potential does not become unstable even if a pull-up or pull-down resistor is externally connected to the input terminal of the CMOS integrated circuit and the input terminal of the logic signal becomes open. I am doing so. There is also an example in which a pull-up or pull-down resistance element is built in a CMOS integrated circuit in advance.
[0004]
[Non-Patent Document 1]
Basics of MOS integrated circuits (Modern Sciences, p. 14)
[0005]
[Problems to be solved by the invention]
However, when a pull-up or pull-down resistor is externally attached, external parts are required, and the occupied area of the board increases due to the arrangement, and there is a problem of cost increase due to an increase in assembly process. .
[0006]
In addition, when a pull-up resistance element or a pull-down resistance element is built in a CMOS integrated circuit, a high resistance of about several MΩ is required to satisfy the low current consumption required for the system. Increase in size is inevitable. In particular, when a plurality of input terminals for logic signals are required, there is a problem that the chip area is remarkably increased and the cost is increased.
[0007]
The present invention has been made in view of the above. A pull-down circuit and a pull-up circuit that can perform pull-up and pull-down without increasing the chip size. The road An object of the present invention is to obtain a CMOS integrated circuit that does not require a built-in external component resistor.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is applied. CMOS integrated circuit Always outputs a constant current when power is applied First and second Constant current circuit and gate electrode are connected in common, and source electrode is connected to ground First and second Consists of N-channel transistors The above Gate electrode and Of the first N-channel transistor A terminal commonly connected to the drain electrode is First Connected to the current outflow end of the constant current circuit, The drain electrode of the second N-channel transistor But , Logic signal input terminal of CMOS logic circuit and The gate electrode of the third N-channel transistor whose source electrode is grounded When , A current mirror circuit connected to the connection line of A connection terminal between the drain electrode of the third N-channel transistor and the current outflow end of the second constant current circuit is connected to an input end of a CMOS inverter circuit which is a first stage circuit of an internal logic circuit. It is characterized by that.
[0009]
According to the present invention, in the current mirror circuit, the gate electrode and Of the first N-channel transistor Connect the drain electrode to the common terminal First A constant current is supplied from the constant current circuit. First Since the N-channel transistor is turned on, Second N-channel transistors operate in a non-saturated state. As a result, when the logic signal input terminal is open That is, the voltage level applied to the logic signal input terminal is different from the voltage level of the power supply. in case of, Second Although there is no current supply source for the N-channel transistor, the logic signal input terminal in the open state is drawn to the level of the ground potential, so that the operation equivalent to the case of using the pull-down resistor is performed. Done. As a result, the third N-channel transistor responds correctly and turns off, and the input terminal of the CMOS inverter circuit, which is the first stage circuit of the internal logic circuit, is set to the voltage level of the power supply, thereby preventing the occurrence of a through current. Ru .
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of a pull-down circuit, a pull-up circuit, and a CMOS integrated circuit according to the present invention are explained in detail below with reference to the accompanying drawings.
[0011]
Embodiment 1 FIG.
1 is a circuit diagram showing a configuration of a CMOS integrated circuit according to Embodiment 1 of the present invention. First, with reference to FIG. 7 and FIG. 8, a measure generally adopted for a case where the logic signal input terminal of the CMOS integrated circuit is in an open state will be described. FIG. 7 is a circuit diagram showing a configuration example of a CMOS integrated circuit used to facilitate understanding of the present invention (when an external pull-down resistor is required). FIG. 8 is a circuit diagram showing a configuration example of a CMOS integrated circuit used for facilitating understanding of the present invention (when a pull-down resistor element is incorporated).
[0012]
In the CMOS integrated circuit 7 shown in FIG. 7, a first-stage CMOS inverter circuit 72 and a next-stage CMOS inverter circuit 73 provided on the logic signal input terminal 71 side are shown as examples of internal logic circuits. The CMOS inverter circuit 72 includes a P-channel transistor 72a and an N-channel transistor 72b. The CMOS inverter circuit 73 includes a P-channel transistor 73a and an N-channel transistor 73b.
[0013]
The P-channel transistor 72a and the N-channel transistor 72b have their gate electrodes and drain electrodes connected in common, the source electrode of the P-channel transistor 72a is connected to the power supply (VDD), and the source electrode of the N-channel transistor 72b is connected to the ground. ing. The commonly connected gate electrodes are connected to the logic signal input terminal 71.
[0014]
The P-channel transistor 73a and the N-channel transistor 73b have their gate electrodes and drain electrodes commonly connected, the source electrode of the P-channel transistor 73a is connected to the power supply (VDD), and the source electrode of the N-channel transistor 73b is connected to the ground. ing. The commonly connected gate electrodes are connected to the commonly connected drain electrodes of the P-channel transistor 72a and the N-channel transistor 72b. A drain electrode commonly connected to the P-channel transistor 73a and the N-channel transistor 73b serves as an output terminal to the subsequent logic circuit.
[0015]
In the above configuration, in the CMOS inverter circuit 72, when the potential VA of the commonly connected gate electrodes is at a high level (hereinafter referred to as “H level”), the P-channel transistor 72a performs an off operation, and the N-channel transistor Since 72b is turned on, the potential VB of the drain electrodes connected in common becomes low level (hereinafter referred to as “L level”).
[0016]
When the commonly connected gate electrode potential VA is at the L level, the P channel transistor 72a is turned on and the N channel transistor 72b is turned off. Becomes H level. A similar operation is also performed in the CMOS inverter circuit 73.
[0017]
When the logic signal input terminal 71 is placed in the open state, the potential VA of the commonly connected gate electrodes becomes unstable in the CMOS inverter circuit 72, so that the P-channel transistor 72a and the N-channel transistor 72b are arbitrarily turned on. Operation and off operation occur, and control becomes impossible. Further, when the logic signal input terminal 71 is placed in the intermediate potential state, both the P-channel transistor 72a and the N-channel transistor 72b are turned on, a through current flows, and the current consumption increases.
[0018]
Therefore, in order to determine the potential even when the logic signal input terminal 71 is in the open state, for example, as shown in FIG. 7, outside the CMOS integrated circuit 7, between the logic signal input terminal 71 and the ground, A pull-down resistor 74 is connected. Alternatively, although not shown, a pull-up resistor is connected between the logic signal input terminal 71 and the power supply. Alternatively, for example, as shown in FIG. 8, a pull-down resistor element 84 is connected between the logic signal input terminal 71 and the ground inside the CMOS integrated circuit 8. Alternatively, although not shown, a pull-up resistor element is connected between the logic signal input terminal 71 and the power supply.
[0019]
However, in the system using the resistor of the external component, the external component is required, and the assembly process is increased in addition to the increase in the occupied area of the board due to the arrangement. In addition, when a resistance element is built in, a high resistance is necessary, and thus an increase in chip size is inevitable. In view of this, the present invention realizes a CMOS integrated circuit that incorporates a pull-down circuit or pull-up circuit that can perform pull-up and pull-down without increasing the chip size, and eliminates the need for an external component resistor. Hereinafter, description will be made with reference to FIG.
[0020]
In FIG. 1, in the CMOS integrated circuit 1, a first-stage CMOS inverter circuit 15 and a next-stage CMOS inverter circuit 16 provided on the logic signal input terminal 10 side are shown as examples of internal logic circuits. The CMOS inverter circuit 15 includes a P channel transistor 15a and an N channel transistor 15b. The CMOS inverter circuit 16 includes a P-channel transistor 16a and an N-channel transistor 16b.
[0021]
The P-channel transistor 15a and the N-channel transistor 15b have their gate electrodes and drain electrodes commonly connected, the source electrode of the P-channel transistor 15a is connected to the power supply (VDD), and the source electrode of the N-channel transistor 15b is connected to the ground. ing. The commonly connected gate electrodes are connected to the logic signal input terminal 10.
[0022]
In the P-channel transistor 16a and the N-channel transistor 16b, the gate electrode and the drain electrode are commonly connected, the source electrode of the P-channel transistor 16a is connected to the power supply (VDD), and the source electrode of the N-channel transistor 16b is connected to the ground. ing. The commonly connected gate electrodes are connected to the commonly connected drain electrodes of the P channel transistor 15a and the N channel transistor 15b. A drain electrode commonly connected to the P-channel transistor 16a and the N-channel transistor 16b serves as an output terminal to the subsequent logic circuit.
[0023]
A pull-down circuit 1a is provided. The pull-down circuit 1 a includes a constant current circuit 11 and a current mirror circuit 14 composed of N-channel transistors 12 and 13.
[0024]
One end of the constant current circuit 11 is connected to a power source (VDD), and a constant current is constantly output from the other end. In the current mirror circuit 14, the N-channel transistors 12 and 13 have a gate electrode connected in common and a source electrode connected in common to ground (GND). The drain electrode of the N-channel transistor 12 is connected to the gate electrode and is connected to the other end (current outflow end) of the constant current circuit 11 as one terminal. The drain electrode of the N-channel transistor 13 is connected to the connection line between the logic signal input terminal 10 and the commonly connected gate electrode which is the input end of the CMOS inverter circuit 15 as the other terminal.
[0025]
Next, the operation of the CMOS integrated circuit 1 according to the first embodiment will be described with reference to FIG. In the pull-down circuit 1 a, the constant current circuit 11 operates together with power supply and constantly supplies the set constant current to the current mirror circuit 14. As a result, in the current mirror circuit 14, the N-channel transistor 12 is turned on, the N-channel transistor 13 is activated in the non-saturated region, and the source-drain voltage is at the ground (GND) level.
[0026]
When a current supply source is connected to the logic signal input terminal 10, a current determined by the size ratio of the N channel transistors 12 and 13 flows through the N channel transistor 13 in a direction that is drawn from the logic signal input terminal 10. When the logic signal input terminal 10 is in an open state, there is no current supply source. However, since the N-channel transistor 13 is in an operation state in a non-saturated region, the logic signal input terminal 10 is at the ground (GND) level. Be drawn.
[0027]
Therefore, even if the logic signal input terminal 10 is placed in the open state, the potential VA of the commonly connected gate electrode which is the input terminal of the CMOS inverter circuit 15 becomes L level. VB becomes H level. The output Vo of the CMOS inverter circuit 16 at the next stage becomes L level. The above operation is the same as when the pull-down resistor shown in FIG. 7 or FIG. 8 is used.
[0028]
When the logic signal input terminal 10 is not in an open state and an external circuit is connected and an L level signal is applied, the same operation as described above is performed, so that the output Vo of the CMOS inverter circuit 16 becomes the L level. .
[0029]
When an H level signal is applied to the logic signal input terminal 10 from an external circuit, the N-channel transistor 13 performs an operation of drawing a constant current from the logic signal input terminal 10 as described above. If the magnitude of the constant current is set to a minute current that does not affect the current supply capability of the external circuit, the drain voltage of the N-channel transistor 13 and the commonly connected gate electrode that is the input terminal of the CMOS inverter circuit 15 Can be set to the same H level as that of the logic signal input terminal 10.
[0030]
Therefore, when an H level signal is applied to the logic signal input terminal 10, the potential VB of the drain electrode connected in common, which is the output terminal of the CMOS inverter circuit 15, becomes L level, and the CMOS inverter circuit in the next stage The output Vo of 16 becomes H level. That is, normal operation can be performed without any trouble.
[0031]
As described above, according to the first embodiment, the pull-down circuit is realized by a circuit including the constant current circuit and the current mirror circuit without using the pull-down resistor shown in FIG. 7 or FIG. This eliminates the need for a resistor and can reduce the cost. Further, since an equivalent function can be realized by arranging only a few transistors without incorporating a pull-down resistor element, the cost can be similarly reduced.
[0032]
Embodiment 2. FIG.
FIG. 2 is a circuit diagram showing a configuration of a CMOS integrated circuit according to the second embodiment of the present invention. In FIG. 2, the same reference numerals are given to components that are the same as or equivalent to the configuration shown in FIG. 1. Here, the description will be focused on the portion related to the second embodiment.
[0033]
As shown in FIG. 2, in the CMOS integrated circuit 2 according to the second embodiment, a pull-up circuit 2a is provided instead of the pull-down circuit 1a shown in FIG. The pull-up circuit 2 a includes a constant current circuit 21 and a current mirror circuit 24 composed of P-channel transistors 22 and 23.
[0034]
One end of the constant current circuit 21 is connected to the ground (GND), and a constant current is always drawn from the other end. In the current mirror circuit 24, the P-channel transistors 22 and 23 have gate electrodes connected in common and source electrodes connected in common to a power supply (VDD). The drain electrode of the P-channel transistor 22 is connected to the gate electrode and to the other end (current inflow end) of the constant current circuit 21 as one terminal. The drain electrode of the P-channel transistor 23 is connected to the connection line between the logic signal input terminal 10 and the commonly connected gate electrode which is the input end of the CMOS inverter circuit 15 as the other terminal.
[0035]
Next, the operation of the CMOS integrated circuit 2 according to the second embodiment will be described with reference to FIG. In the pull-up circuit 2 a, the constant current circuit 21 operates along with the application of power and performs an operation of constantly drawing the set constant current from the current mirror circuit 24. As a result, in the current mirror circuit 24, the P-channel transistor 22 is turned on, the P-channel transistor 23 is activated in the non-saturated region, and the source-drain voltage is at the power supply (VDD) level.
[0036]
When a current sink is connected to the logic signal input terminal 10, a current determined by the size ratio of the P channel transistors 22 and 23 flows through the P channel transistor 23 in a direction that flows into the logic signal input terminal 10. When the logic signal input terminal 10 is in an open state, there is no current sink, but since the P-channel transistor 23 is in an operation state in a non-saturation region, the logic signal input terminal 10 is at the power supply (VDD) level. Be drawn.
[0037]
Therefore, even if the logic signal input terminal 10 is placed in the open state, the potential VA of the commonly connected gate electrode which is the input terminal of the CMOS inverter circuit 15 becomes H level. VB becomes L level. The output Vo of the next stage CMOS inverter circuit 16 becomes H level. Although the above operation is not shown, it is the same as when a pull-up resistor is used.
[0038]
When the logic signal input terminal 10 is not in an open state and an external circuit is connected and an H level signal is applied, the same operation as described above is performed, so that the output Vo of the CMOS inverter circuit 16 becomes an H level. .
[0039]
When an L level signal is applied to the logic signal input terminal 10 from an external circuit, the P-channel transistor 23 performs an operation of flowing a constant current into the logic signal input terminal 10 as described above. If the magnitude of the constant current is set to a minute current that does not affect the current sink capability of the external circuit, the drain voltage of the P-channel transistor 23 and the commonly connected gate electrode that is the input terminal of the CMOS inverter circuit 15 Can be set to the same L level as that of the logic signal input terminal 10.
[0040]
Therefore, when an L level signal is applied to the logic signal input terminal 10, the potential VB of the drain electrode connected in common which is the output terminal of the CMOS inverter circuit 15 becomes H level, and the CMOS inverter circuit in the next stage The output Vo of 16 becomes L level. That is, normal operation can be performed without any trouble.
[0041]
As described above, according to the second embodiment, since the pull-up circuit is realized by a circuit constituted by a constant current circuit and a current mirror circuit without using a pull-up resistor, a resistor as an external component is not required. Cost reduction. Further, since an equivalent function can be realized by arranging only a few transistors without incorporating a pull-up resistor element, the cost can be similarly reduced.
[0042]
Embodiment 3 FIG.
FIG. 3 is a circuit diagram showing a configuration of a CMOS integrated circuit according to Embodiment 3 of the present invention. In FIG. 3, the same reference numerals are given to components that are the same as or equivalent to the configuration shown in FIG. 1. Here, the description will be focused on the portion related to the third embodiment.
[0043]
As shown in FIG. 3, in the CMOS integrated circuit 3 according to the third embodiment, a series circuit of a constant current circuit 31 and an N-channel transistor 32 is provided in parallel on the input side of the first-stage CMOS inverter circuit 15. In other words, the constant current circuit 31 has one end connected to the power supply (VDD) and the other end (current outflow end) connected to the drain electrode of the N-channel transistor 32. The source electrode of the N channel transistor 32 is connected to the ground (GND).
[0044]
The gate electrode of the N-channel transistor 32 is connected to the logic signal input terminal 10 and the drain electrode of the N-channel transistor 13 which is the other terminal of the current mirror circuit 14 in the pull-down circuit 1a. Further, the connection end of the drain electrode of the N-channel transistor 32 and the other end (current outflow end) of the constant current circuit 31 is connected to a commonly connected gate electrode which is an input end of the CMOS inverter circuit 15.
[0045]
Next, the operation of the CMOS integrated circuit 3 according to the third embodiment will be described with reference to FIG. When an L level signal is applied to the logic signal input terminal 10 from an external circuit, the N channel transistor 32 is turned off, so that the potential VB of the drain electrode of the N channel transistor 32 is set to the potential of the power supply (VDD). Thus, the output Vo of the CMOS inverter circuit 15 becomes L level.
[0046]
When an H level signal is applied to the logic signal input terminal 10 from an external circuit, the N channel transistor 32 is turned on, so that the potential VB of the drain electrode of the N channel transistor 32 becomes the ground potential. The output Vo of the CMOS inverter circuit 15 becomes H level. That is, normal operation is performed without any trouble.
[0047]
Here, in the CMOS integrated circuit 1 shown in FIG. 1, when the H level voltage VA applied from the external circuit to the logic signal input terminal 10 is different from the voltage of the power supply (VDD), a through current is generated in the CMOS inverter circuit 15. There is a possibility of flowing.
[0048]
On the other hand, in the CMOS integrated circuit 3 shown in FIG. 3, even when the H level voltage VA applied to the logic signal input terminal 10 from the external circuit is different from the voltage of the power supply (VDD), the input terminal of the internal logic circuit. Since an N channel transistor 32 responds correctly and the input terminal of the CMOS inverter circuit 15 is set to the voltage level of the power supply (VDD), the generation of a through current can be prevented.
[0049]
As described above, according to the third embodiment, even when the H level voltage applied from the external circuit to the logic signal input terminal is different from the voltage of the power supply, normal operation can be performed without causing any through current. As a result, power consumption can be reduced and the design of the interface with the outside becomes easy.
[0050]
Embodiment 4 FIG.
4 is a circuit diagram showing a configuration of a CMOS integrated circuit according to Embodiment 4 of the present invention. In FIG. 4, the same reference numerals are given to components that are the same as or equivalent to the configuration shown in FIG. 2. Here, the description will be focused on the portion related to the fourth embodiment.
[0051]
As shown in FIG. 4, in the CMOS integrated circuit 4 according to the fourth embodiment, a series circuit of a P-channel transistor 42 and a constant current circuit 41 is provided in parallel on the input side of the first-stage CMOS inverter circuit 15. That is, the constant current circuit 41 has one end connected to the ground (GND) and the other end (current inflow end) connected to the drain electrode of the P-channel transistor 42. The source electrode of the P-channel transistor 42 is connected to the power supply (VDD).
[0052]
The gate electrode of the P-channel transistor 42 is connected to the logic signal input terminal 10 and the drain electrode of the P-channel transistor 23 which is the other terminal of the current mirror circuit 24 in the pull-up circuit 2a. Further, the connection end of the drain electrode of the P-channel transistor 42 and the other end (current inflow end) of the constant current circuit 41 is connected to the commonly connected gate electrode which is the input end of the CMOS inverter circuit 15.
[0053]
Next, the operation of the CMOS integrated circuit 4 according to the fourth embodiment will be described with reference to FIG. When an H level signal is applied to the logic signal input terminal 10 from an external circuit, the P-channel transistor 42 performs an off operation. Since the potential VB of the drain electrode of the P-channel transistor 42 is drawn to the ground (GND) potential by the constant current circuit 41, the output Vo of the CMOS inverter circuit 15 becomes H level.
[0054]
When an L level signal is applied to the logic signal input terminal 10 from an external circuit, the P channel transistor 42 is turned on, so that the potential VB of the drain electrode of the P channel transistor 42 is the power supply (VDD). The voltage Vo becomes the potential, and the output Vo of the CMOS inverter circuit 15 becomes L level. That is, normal operation is performed without any trouble.
[0055]
Here, in the CMOS integrated circuit 2 shown in FIG. 2, when the L level voltage VA applied from the external circuit to the logic signal input terminal 10 is different from the ground potential of the CMOS integrated circuit 2, the CMOS inverter circuit 15 is penetrated. Current may flow.
[0056]
On the other hand, in the CMOS integrated circuit 4 shown in FIG. 4, even when the L level voltage VA applied to the logic signal input terminal 10 from the external circuit is different from the ground potential of the CMOS integrated circuit 4, the input of the internal logic circuit is performed. Since the P-channel transistor 42 which is the end responds correctly and the input end of the CMOS inverter circuit 15 is set to the ground potential level of the CMOS integrated circuit 4, the generation of a through current can be prevented.
[0057]
As described above, according to the fourth embodiment, even when the L level voltage applied from the external circuit to the logic signal input terminal is different from the ground potential of the CMOS integrated circuit, the through current is the same as in the third embodiment. Therefore, the normal operation can be performed without any trouble, so that the power consumption can be reduced and the interface design with the outside becomes easy.
[0058]
Embodiment 5. FIG.
FIG. 5 is a circuit diagram showing a configuration of a CMOS integrated circuit according to the fifth embodiment of the present invention. In FIG. 5, the same reference numerals are given to components that are the same as or equivalent to the configuration shown in FIG. 3. Here, the description will be focused on the portion related to the fifth embodiment.
[0059]
As shown in FIG. 5, in the CMOS integrated circuit 5 according to the fifth embodiment, in the configuration shown in FIG. 3, an N-channel transistor which is the other terminal of the current mirror circuit 14 in the logic signal input terminal 10 and the pull-down circuit 1a. An N-channel transistor 51 is provided between the 13 drain electrodes.
[0060]
That is, the N-channel transistor 51 has a gate electrode and a drain electrode commonly connected to the logic signal input terminal 10, and a source electrode connected to the other terminal of the current mirror circuit 14 in the pull-down circuit 1a and an input terminal of the CMOS inverter circuit 15. It is connected to the.
[0061]
Next, the operation of the CMOS integrated circuit 5 according to the fifth embodiment will be described with reference to FIG. When an L level signal is applied from the external circuit to the logic signal input terminal 10, the N channel transistor 51 is turned off, but the potential VA of the gate electrode of the N channel transistor 32 is set to the ground potential by the pull-down circuit 1a. It is drawn. Therefore, the N channel transistor 32 performs an off operation, and the output Vo of the CMOS inverter circuit 15 becomes H level.
[0062]
When an H level signal is applied to the logic signal input terminal 10 from an external circuit, the N channel transistor 51 is turned on, so that the potential VA of the gate electrode of the N channel transistor 32 becomes H level. Therefore, the N-channel transistor 32 is turned on, and the output Vo of the CMOS inverter circuit 15 becomes L level. That is, normal operation is performed without any trouble.
[0063]
Here, when the H level voltage applied to the logic signal input terminal from the external circuit is different from the voltage of the power supply, in the CMOS integrated circuit 3 shown in FIG. 3, the input voltage of the logic signal input terminal 10 is an N-channel transistor. Since the voltage is directly applied to the 32 gate electrodes, the H level of the input voltage is determined by the threshold voltage Vth of the N-channel transistor 32. This threshold voltage Vth can be adjusted by manipulating the size of the N-channel transistor 32. However, the adjustment range is limited only by the size adjustment of the N-channel transistor 32.
[0064]
On the other hand, in the fifth embodiment, the N channel transistor 51 is inserted, the H level of the voltage input to the logic signal input terminal 10 is the threshold voltage Vth of the N channel transistor 32, and the threshold voltage Vth of the N channel transistor 51 is Since the configuration is determined by adding, the adjustment range can be widened, and the design becomes easy.
[0065]
As described above, according to the fifth embodiment, when the H level voltage applied from the external circuit to the logic signal input terminal is different from the voltage of the power supply, the adjustment range can be widened. The voltage range can be handled flexibly.
[0066]
Embodiment 6 FIG.
FIG. 6 is a circuit diagram showing a configuration of a CMOS integrated circuit according to the sixth embodiment of the present invention. In FIG. 6, the same reference numerals are given to components that are the same as or equivalent to the configuration illustrated in FIG. 4. Here, the description will be focused on the portion related to the sixth embodiment.
[0067]
As shown in FIG. 6, in the CMOS integrated circuit 6 according to the sixth embodiment, in the configuration shown in FIG. 4, the P-channel which is the other terminal of the current mirror circuit 24 in the logic signal input terminal 10 and the pull-up circuit 2a. A P-channel transistor 61 is provided between the drain electrode of the transistor 23.
[0068]
That is, the P-channel transistor 61 has a gate electrode and a drain electrode commonly connected to the logic signal input terminal 10, and a source electrode connected to the other terminal of the current mirror circuit 24 in the pull-up circuit 2a and an input terminal of the CMOS inverter circuit 15. And connected to.
[0069]
Next, the operation of the CMOS integrated circuit 6 according to the sixth embodiment will be described with reference to FIG. When an H level signal is applied to the logic signal input terminal 10 from an external circuit, the P channel transistor 61 is turned off, but the potential VA of the date electrode of the P channel transistor 42 is supplied by the pull-up circuit 2a. (VDD) potential. Therefore, the P channel transistor 42 is turned off, and the output Vo of the CMOS inverter circuit 15 becomes L level.
[0070]
When an L level signal is applied to the logic signal input terminal 10 from an external circuit, the P channel transistor 61 is turned on, so that the potential VA of the gate electrode of the P channel transistor 42 is at the L level. Therefore, the P-channel transistor 42 is turned on, and the output Vo of the CMOS inverter circuit 15 becomes H level. That is, normal operation is performed without any trouble.
[0071]
Here, when the L level voltage VA applied to the logic signal input terminal 10 from the external circuit is different from the ground potential of the CMOS integrated circuit 6, the CMOS integrated circuit 4 shown in FIG. Since the input voltage is directly applied to the gate electrode of the P-channel transistor 42, the L level of the input voltage is determined by the threshold voltage Vth of the P-channel transistor 42. This threshold voltage Vth can be adjusted by manipulating the size of the P-channel transistor 42. However, the adjustment range is limited only by the size adjustment of the P-channel transistor 42.
[0072]
On the other hand, in the sixth embodiment, the P channel transistor 61 is inserted, the L level of the voltage input to the logic signal input terminal 10 is equal to the threshold voltage Vth of the P channel transistor 42, and the threshold voltage Vth of the P channel transistor 61 is Since the configuration is determined by adding, the adjustment range can be widened, and the design becomes easy.
[0073]
Thus, according to the sixth embodiment, the adjustment range can be widened when the L level voltage applied from the external circuit to the logic signal input terminal is different from the ground potential of the CMOS integrated circuit. The L-level voltage range can be flexibly handled.
[0074]
【The invention's effect】
As explained above, according to the present invention, Built in CMOS integrated circuit Pull down circuit Increase chip size Consists of a constant current circuit that always outputs a constant current when power is applied without using a pull-down resistor, and a current mirror circuit that turns on by the constant current circuit and draws the potential of the logic signal input terminal to the ground potential. did. Also, Built in CMOS integrated circuit Pull-up circuit Increase chip size Consists of a constant current circuit that constantly draws a constant current when power is applied, without using a pull-up resistor, and a current mirror circuit that turns on by the constant current circuit and draws the potential of the logic signal input terminal to the power supply potential. did. Therefore, CMOS integrated circuit Then Since it is possible to eliminate the need for external pull-down and pull-up resistors, costs can be reduced. Further, since an equivalent function can be realized by arranging only a few transistors without incorporating a pull-down or pull-up resistance element, the cost can be reduced in the same manner.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a CMOS integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a CMOS integrated circuit according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a CMOS integrated circuit according to a third embodiment of the present invention.
FIG. 4 is a circuit diagram showing a configuration of a CMOS integrated circuit according to a fourth embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of a CMOS integrated circuit according to a fifth embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a CMOS integrated circuit according to a sixth embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration example of a CMOS integrated circuit used for facilitating understanding of the present invention (when an external pull-down resistor is required).
FIG. 8 is a circuit diagram showing a configuration example of a CMOS integrated circuit used for facilitating understanding of the present invention (when a pull-down resistor element is incorporated);
[Explanation of symbols]
1-6 CMOS integrated circuit, 1a pull-down circuit, 2a pull-up circuit, 10 logic signal input terminal, 11, 21, 31, 41 constant current circuit, 12, 13, 32 N-channel transistor, 14, 24 current mirror circuit, 15 , 16 CMOS inverter circuit, 22, 23, 42 P-channel transistor.

Claims (4)

First and second constant current circuits that constantly output a constant current when power is applied;
Is connected the gate electrode is common, is constituted by the first and second N-channel transistor having a source electrode are commonly grounded, terminals connected to the drain electrode of the gate electrode and the first N-channel transistor in common A drain terminal of the second N-channel transistor connected to a current outflow end of the first constant current circuit; a logic signal input terminal of the CMOS logic circuit; and a third N-channel transistor whose source electrode is grounded. a gate electrode is connected to a connection line and a current mirror circuit,
A connection terminal between a drain electrode of the third N-channel transistor and a current outflow end of the second constant current circuit is connected to an input end of a CMOS inverter circuit which is a first stage circuit of an internal logic circuit. CMOS integrated circuit . First and second constant current circuits that constantly draw a constant current when power is applied;
Is connected the gate electrode is common, it is constituted by first and second P-channel transistor having a source electrode connected to a common power source, and connecting the drain electrode of the gate electrode and the first P-channel transistor in common A terminal is connected to the current inflow end of the first constant current circuit, a drain electrode of the second P-channel transistor is connected to a logic signal input terminal of the CMOS logic circuit, and a source electrode is connected to a power source. and a current mirror circuit connected to the gate electrode of the P-channel transistor, the connection line,
A connection terminal between a drain electrode of the third P-channel transistor and a current inflow end of the second constant current circuit is connected to an input end of a CMOS inverter circuit which is a first stage circuit of an internal logic circuit. CMOS integrated circuit . A gate electrode and a drain electrode are commonly connected to the logic signal input terminal, and a source electrode is connected to a drain electrode of the second N-channel transistor and a gate electrode of the third N-channel transistor . N-channel transistor,
The CMOS integrated circuit according to claim 1, further comprising: A gate electrode and a drain electrode are commonly connected to the logic signal input terminal, and a source electrode is connected to a drain electrode of the second P-channel transistor and a gate electrode of the third P-channel transistor . P-channel transistor,
The CMOS integrated circuit according to claim 2, further comprising:

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