JP4055980B2 - デジタル回路試験装置 - Google Patents

デジタル回路試験装置 Download PDF

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Publication number
JP4055980B2
JP4055980B2 JP2001348717A JP2001348717A JP4055980B2 JP 4055980 B2 JP4055980 B2 JP 4055980B2 JP 2001348717 A JP2001348717 A JP 2001348717A JP 2001348717 A JP2001348717 A JP 2001348717A JP 4055980 B2 JP4055980 B2 JP 4055980B2
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Japan
Prior art keywords
scan
data
shift
input
test
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Expired - Fee Related
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JP2001348717A
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Japanese (ja)
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JP2002243805A (ja
JP2002243805A5 (enExample
Inventor
ジェフ・リアリック
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アバゴ・テクノロジーズ・ジェネラル・アイピー（シンガポール）プライベート・リミテッド
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2001348717A 2000-11-14 2001-11-14 デジタル回路試験装置 Expired - Fee Related JP4055980B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US713517 1996-09-13
US09/713,517 US6715105B1 (en) 2000-11-14 2000-11-14 Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port

Publications (3)

Publication Number Publication Date
JP2002243805A JP2002243805A (ja) 2002-08-28
JP2002243805A5 JP2002243805A5 (enExample) 2005-07-14
JP4055980B2 true JP4055980B2 (ja) 2008-03-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001348717A Expired - Fee Related JP4055980B2 (ja) 2000-11-14 2001-11-14 デジタル回路試験装置

Country Status (2)

Country Link
US (1) US6715105B1 (enExample)
JP (1) JP4055980B2 (enExample)

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US7376875B2 (en) * 2005-07-14 2008-05-20 International Business Machines Corporation Method of improving logical built-in self test (LBIST) AC fault isolations
US7461309B2 (en) * 2005-12-20 2008-12-02 Kabushiki Kaisha Toshiba Systems and methods for providing output data in an LBIST system having a limited number of output ports
US20070189175A1 (en) * 2006-02-14 2007-08-16 Finisar Corporation Capture timing and negotiation data with repeat counts in a networking diagnostic component
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JP2002243805A (ja) 2002-08-28
US6715105B1 (en) 2004-03-30

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