JP4051187B2 - Multi-chip module sealing structure - Google Patents

Multi-chip module sealing structure Download PDF

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Publication number
JP4051187B2
JP4051187B2 JP2001252272A JP2001252272A JP4051187B2 JP 4051187 B2 JP4051187 B2 JP 4051187B2 JP 2001252272 A JP2001252272 A JP 2001252272A JP 2001252272 A JP2001252272 A JP 2001252272A JP 4051187 B2 JP4051187 B2 JP 4051187B2
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JP
Japan
Prior art keywords
frame
sealing structure
wiring board
heat sink
chip module
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JP2001252272A
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Japanese (ja)
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JP2003068969A (en
Inventor
孝市 高橋
宏一 古谷野
明弘 安田
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Hitachi Ltd
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Hitachi Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

Abstract

PROBLEM TO BE SOLVED: To provide a multi-chip module sealing structure which is superior in cooling performance and sealing reliability. SOLUTION: A semiconductor device 2 is mounted on a wiring board 1, the top surface of the wiring board 1 is fixed by soldering 8 to the undersurfaces of first frames 5 of which each thermal expansion coefficient conforms to that of the wiring board 1. Each of the upper parts of the first frames 5 is extended outside of the edges of the wiring board 1, the lower part of the air-cooling heat sink 7 and the top surfaces of the second frames 10 are fastened by bolts 9 through the intermediary of an O-ring between a large air-cooling heat sink 7 covering the frames 5 sufficiently and the first frames 5, and through the intermediary of plastic pieces 6 between the inner middle stages of second frames 10 of which each thermal expansion coefficient conforms to that of the air-cooling heat sink 7 and the outer middle stage of the first frames 5.

Description

【0001】
【発明の属する技術分野】
本発明は、マルチチップモジュールの封止冷却機構に係り、特に、高性能な半導体デバイスを搭載した電子計算機等に用いるマルチチップモジュールの封止構造に関する。
【0002】
【従来の技術】
電子計算機の演算処理速度の高速化、記憶容量の増加等に伴って半導体デバイスの高速化、高集積化が成されている。しかし、その反面で半導体デバイスの消費電力の増加に伴うチップの発熱が、半導体デバイスの安定動作上の信頼性問題と絡んで問題となっている。特に、多数の半導体チップを高密度配線基板の上に搭載するマルチチップモジュールにおいては、この廃熱問題、すなわち、マルチチップモジュールの冷却構造が大きな課題として取上げられる。
【0003】
一方、半導体デバイスの対環境信頼性やモジュールとしての冷却性能を長期にわたって保持するためには、半導体デバイス、冷却構造をマルチチップモジュール内部に閉じ込める、封止機構も重要な技術課題である。
【0004】
マルチチップモジュールに関する、このように重要な封止構造の例を以下に述べる。“MCM−D/C Application for high Performance Module”,Proceeding of 1996 International Conference on Multi−chip Modules, p69に図4に示すような封止構造が開示されている。
【0005】
多数の半導体デバイス402がアルミナセラミックから成る配線基板401に搭載されている。配線基板401の裏面には入出力ピン403が設けられ、高熱伝導性の材料から成るキャップ板405が、配線基板401を覆うように被せられており、配線基板401の周縁部ではんだ固着408することでモジュール内を気密封止している。半導体デバイス402とキャップ板405の間には個々の半導体デバイス402に対応して熱伝導性コンパウンド404と呼ばれる熱伝導手段が設けられていて、半導体デバイス402の発熱をキャップ板405に伝える。キャップ板405の上面には、空冷ヒートシンク407が取付けられており、キャップ板405を経た半導体デバイス402の発熱を放熱している。
【0006】
さらに別の例として、特開2000−349211号公報には図5に示すようなマルチチップモジュールの封止構造が開示されている。
図5は多数の半導体デバイス502がセラミック等の配線基板501に搭載されている。配線基板501は半導体デバイス502の熱膨張率と整合した熱膨張率を有する材料である。配線基板501の裏面には入出力ピン503が設けられている。
【0007】
配線基板501の熱膨張率と整合する熱膨張率を有する材料である鉄−ニッケル合金から成る枠体505は、下面を配線基板501の半導体デバイス502が搭載された面と相互にはんだ固着508されている。
【0008】
枠体505の上方は配線基板501の外側に広がり、枠体505の上面はOリング溝を設けたフランジ面となっている。空冷ヒートシンク507の周縁部の上下面はフランジ面に成っており、このフランジ下面と枠体505の上面のOリング溝との間に弾性に優れたゴムOリング511を介す。
【0009】
また、空冷ヒートシンク507の周縁部の上面には相対すべりに優れたプラスチック506を介し、上部枠体510の内側中段でプラスチック506の上面を押さえ、上部枠体510の下方と枠体505との間をボルト509にて締結することでゴムOリング511を潰して気密封止を行う。
【0010】
上部枠体510の内側中段の側面と空冷ヒートシンク507の外周側面との間には組立精度と熱膨張差分を考慮した隙間を設け、枠体505の上面と空冷ヒートシンク507の周縁部の下面は、ゴムOリング511による気密性を保ちながら接触を避けるように微少の隙間を設けている。空冷ヒートシンク507と半導体デバイス502の間には、個々の半導体デバイス502に対応して熱伝導性コンパウンド504が設けられており、半導体デバイス502の発熱を空冷ヒートシンク507に伝える。
【0011】
【発明が解決しようとする課題】
上記のようなマルチチップモジュールの封止構造では、(1)封止部接続信頼性、(2)冷却性能の観点に立つと以下のような問題があった。
“MCM−D/C Application for high Performance Module”,Proceeding of 1996 International Conference on Multi−chip Modules, p69に記載された図4の構造では、冷却性能を確保するためにキャップ板やヒートシンクに熱伝導性の高い金属、例えばアルミニウムや銅等を採用している。
【0012】
一方、配線基板は、微細な多層配線を施すためにアルミナセラミックス等のセラミックスを採用している。キャップ板やヒートシンクに用いるアルミニウムや銅は、セラミックスの熱膨張率よりも大きく不整合なため、モジュール全体の発熱量の増加や配線基板サイズの大型化が進むと、キャップ板やヒートシンクと配線基板間の熱膨張差が大きくなる。前記構造は、キャップ板と配線基板をはんだを介して固着しているため、この間の熱膨張差が大きくなると水平方向の変形がはんだ固着部で拘束され、大きなストレスが発生する。この結果、配線基板のセラミックスやはんだ部が破壊する恐れがあり、封止接続の信頼性の確保が困難となる。
【0013】
また、上記のはんだ固着によって、水平方向の変形が拘束されると、バイメタル効果でモジュールは垂直方向の曲げ変形が起き、結果としてキャップと配線基板の間隔が大きく変化する。すなわち、キャップと半導体デバイスとの間に塗布された熱伝導性コンパウンドの厚さの増加や剥離の恐れがあり、冷却性能の信頼性の確保が困難となる。
【0014】
この点を改善する封止部構造として、特開2000−349211号公報で開示された構造がある。図5の構造は、配線基板の熱膨張率と非整合な空冷ヒートシンクと配線基板の熱膨張率に整合した枠体や上部枠体との間にOリングや摺動性のよいプラスチックを介すことで、空冷ヒートシンクと枠体や上部枠体との熱膨張差による水平方向の変形を拘束させずに封止することができる。このため、枠体と配線基板のはんだ固着部に発生するストレスが大幅に低減され、封止接続信頼性を確保することができる。
【0015】
また、垂直方向の曲げ変形も発生しないため、熱伝導性コンパウンドの厚さの増加や剥離による冷却性能の低下という問題もない。しかし、上記の構造は、枠体の内側に空冷ヒートシンクを設けているため、空冷ヒートシンクの冷却フィンのエリアが必然的に枠体の内枠サイズよりも小さくなり、冷却性能の低下を招いている。このため、モジュール全体の発熱量の増加に伴い、上記の構造の空冷ヒートシンクではモジュールの冷却性能を確保することが困難になる。
【0016】
本発明の目的は、上記従来技術の問題点を改善して(1)封止接続信頼性の向上と(2)冷却性能に優れたマルチチップモジュールの封止構造を提供することにある。
【0017】
【課題を解決するための手段】
上記目的を達成するため、本発明では、複数の半導体デバイスを搭載した配線基板の周縁部に第一の枠体を設け、この第一の枠体を覆うように大型で広い冷却領域をもつ高冷却性能の蓋体を設け、第二の枠体と蓋体の間に摺動性に優れた部材や弾性変形量の大きい部材を介して第一の枠体を締結する手段から成る。
【0018】
【発明の実施の形態】
以下、本発明による各実施例を、図1、図2、図3を用いて具体的に説明する。
〔実施例1〕
図1は本発明の第1の実施例の構成を示すマルチチップモジュールの封止構造の断面図である。図1は多数の半導体デバイス2がセラミック等の配線基板1に搭載されている。配線基板1は半導体デバイス2の熱膨張率と整合した熱膨張率を有する。配線基板1の裏面には入出力ピン3が設けられている。
【0019】
配線基板1の熱膨張率と整合する熱膨張率で鉄−ニッケル合金から成る第一の枠体5の下面が配線基板1の半導体デバイス2が搭載された面ではんだ固着8されている。
【0020】
第一の枠体5の上方は配線基板1の外側に広がっており、第一の枠体5の上面はOリング溝を設けたフランジ面となっている。
【0021】
空冷ヒートシンク7の周縁部の下面はフランジ面に成っており、このフランジ面と第一の枠体5の上面に設けたOリング溝との間に弾性に優れたゴムOリング11を介す。
【0022】
また、第二の枠体10は、空冷ヒートシンク7の熱膨張率に整合させた熱膨張率を有し、第二の枠体10の内側中段と第一の枠体5の外側中段に相対すべりに優れたプラスチック6を介し、プラスチック6の下面を第二の枠体10で押し上げながら、空冷ヒートシンク7の下方と第二の枠体10との間をボルト9にて締結することでゴムOリング11を潰して気密封止する。
【0023】
第二の枠体10の内側中段の側面と第一の枠体5の外周側面との間には組立精度と熱膨張差分を考慮した隙間を設け、また第一の枠体5の上面と空冷ヒートシンク7の周縁部の下面は、ゴムOリング11によって気密性を保ちながら接触を避けるように微少の隙間を設けて、空冷ヒートシンク7と第二の枠体10が第一の枠体5や配線基板1と水平方向の相対的な熱変形を拘束しないようにすることでモジュールの垂直方向の変形を抑える。
【0024】
空冷ヒートシンク7と半導体デバイス2の間には、個々の半導体デバイス2に対応して熱伝導性コンパウンド4が設けられており、モジュール垂直方向の変形を抑えることで、熱伝導性コンパウンド4の厚さを一定に保ち安定した冷却性能を得ることができる。また、モジュール封止用のボルト9を第二の枠体10の下面から締結し、空冷ヒートシンクの上面すべてに冷却のためのフィンを設けることで、大型ヒートシンクによる高冷却性能が確保できる。また、前述のように空冷ヒートシンク7や第二の枠体10と第一の枠体5や配線基板1の間に生じる熱変形を拘束させない構造のため、第一の枠体5とセラミックの配線基板1のはんだ固着8部に発生するストレスを低減することができ、高封止部接続信頼性を確保できる。
【0025】
図2は本発明の第2の実施例に係るマルチチップモジュールの封止構造の断面図である。この第2の実施例は、モジュール封止用のボルト9を空冷ヒートシンク4の周縁部の上面に設けて締結している事以外実施例1と同じである。
〔実施例3〕
以下、本発明に係る実施例を、図3を用いて説明する。
【0026】
図3は本発明の第3の実施例に係るマルチチップモジュールの封止構造の断面図である。この第3の実施例は、第一の枠体5の外側中段にOリング溝を設け、第一の枠体5と第二の枠体10にゴムOリング11を介在させている事以外実施例1と同じである。すなわち、図1のプラスチック6の代りにゴムOリング11を用いたものである。
【0027】
【発明の効果】
本発明によれば、高発熱半導体デバイスの高封止接続信頼性と高冷却性能を可能とするマルチチップモジュールの封止構造を実現した。
【図面の簡単な説明】
【図1】本発明の第一の実施例を示すマルチチップモジュールの封止構造の断面図である。
【図2】本発明の第二の実施例を示すマルチチップモジュールの封止構造の断面図である。
【図3】本発明の第三の実施例を示すマルチチップモジュールの封止構造の断面図である。
【図4】従来技術によるマルチチップモジュールの封止構造の断面図である。
【図5】従来技術によるマルチチップモジュールの封止構造の断面図である。
【符号の説明】
1、401、501・・・配線基板
2、402、502・・・半導体デバイス
3、403、503・・・入出力ピン
4、404、504・・・熱伝導性コンパウンド
5・・・・・・・・・・・第一の枠体
6、506・・・・・・・プラスチック
7、407、507・・・空冷ヒートシンク
8、408、508・・・はんだ固着
9、509・・・・・・・ボルト
10・・・・・・・・・・第二の枠体
11、511・・・・・・ゴムOリング
405・・・・・・・・・キャップ板
505・・・・・・・・・枠体
510・・・・・・・・・上部枠体
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sealing cooling mechanism for a multichip module, and more particularly to a sealing structure for a multichip module used in an electronic computer or the like equipped with a high-performance semiconductor device.
[0002]
[Prior art]
With the increase in the processing speed of electronic computers and the increase in storage capacity, semiconductor devices have been increased in speed and integration. However, on the other hand, heat generation of the chip accompanying an increase in power consumption of the semiconductor device is a problem in connection with a reliability problem in stable operation of the semiconductor device. In particular, in a multi-chip module in which a large number of semiconductor chips are mounted on a high-density wiring board, this waste heat problem, that is, the cooling structure of the multi-chip module is taken up as a big problem.
[0003]
On the other hand, in order to maintain the reliability of the semiconductor device with respect to the environment and the cooling performance as a module over a long period of time, a sealing mechanism for confining the semiconductor device and the cooling structure inside the multichip module is also an important technical issue.
[0004]
Examples of such important sealing structures for multi-chip modules are described below. A sealing structure as shown in FIG. 4 is disclosed in “MCM-D / C Application for high Performance Module”, Proceeding of 1996 International Conference on Multi-chip Modules, p69.
[0005]
A large number of semiconductor devices 402 are mounted on a wiring board 401 made of alumina ceramic. Input / output pins 403 are provided on the back surface of the wiring board 401, and a cap plate 405 made of a material having high thermal conductivity is covered so as to cover the wiring board 401, and solder fixing 408 is performed at the peripheral edge of the wiring board 401. Thus, the inside of the module is hermetically sealed. Between the semiconductor device 402 and the cap plate 405, heat conduction means called a heat conductive compound 404 is provided corresponding to each semiconductor device 402, and heat generated by the semiconductor device 402 is transmitted to the cap plate 405. An air-cooled heat sink 407 is attached to the upper surface of the cap plate 405 to dissipate heat generated by the semiconductor device 402 via the cap plate 405.
[0006]
As yet another example, Japanese Patent Laid-Open No. 2000-349211 discloses a multi-chip module sealing structure as shown in FIG.
In FIG. 5, a large number of semiconductor devices 502 are mounted on a wiring substrate 501 such as ceramic. The wiring substrate 501 is a material having a thermal expansion coefficient that matches the thermal expansion coefficient of the semiconductor device 502. Input / output pins 503 are provided on the back surface of the wiring board 501.
[0007]
A frame body 505 made of an iron-nickel alloy, which is a material having a thermal expansion coefficient that matches the thermal expansion coefficient of the wiring board 501, is solder-bonded 508 to the surface of the wiring board 501 on which the semiconductor device 502 is mounted. ing.
[0008]
The upper part of the frame body 505 extends to the outside of the wiring board 501, and the upper surface of the frame body 505 is a flange surface provided with an O-ring groove. The upper and lower surfaces of the peripheral edge of the air-cooled heat sink 507 are flange surfaces, and a rubber O-ring 511 having excellent elasticity is interposed between the flange lower surface and the O-ring groove on the upper surface of the frame 505.
[0009]
In addition, the upper surface of the peripheral portion of the air-cooled heat sink 507 is interposed with a plastic 506 excellent in relative sliding, and the upper surface of the plastic 506 is pressed at the inner middle stage of the upper frame 510 so that the space between the lower portion of the upper frame 510 and the frame 505 Are tightened with bolts 509 to crush the rubber O-ring 511 and perform hermetic sealing.
[0010]
A gap in consideration of assembly accuracy and thermal expansion difference is provided between the inner middle side surface of the upper frame 510 and the outer peripheral side surface of the air cooling heat sink 507, and the upper surface of the frame body 505 and the lower surface of the peripheral edge of the air cooling heat sink 507 are A minute gap is provided so as to avoid contact while maintaining airtightness by the rubber O-ring 511. Between the air-cooled heat sink 507 and the semiconductor device 502, a thermally conductive compound 504 is provided corresponding to each semiconductor device 502, and heat generated by the semiconductor device 502 is transmitted to the air-cooled heat sink 507.
[0011]
[Problems to be solved by the invention]
The sealing structure of the multichip module as described above has the following problems in terms of (1) sealing part connection reliability and (2) cooling performance.
In the structure of FIG. 4 described in “MCM-D / C Application for high Performance Module”, Proceeding of 1996 International Conference on Multi-chip Modules, p69, a cap plate and a heat sink are used to ensure cooling performance. High metals such as aluminum and copper are used.
[0012]
On the other hand, the wiring board employs ceramics such as alumina ceramics in order to provide fine multilayer wiring. Aluminum and copper used for cap plates and heat sinks are mismatched to a greater extent than the thermal expansion coefficient of ceramics, so if the amount of heat generated by the entire module increases or the size of the wiring board increases, the space between the cap board or heat sink and the wiring board increases. The difference in thermal expansion increases. In the structure, since the cap plate and the wiring board are fixed via solder, when the difference in thermal expansion between them increases, horizontal deformation is restrained by the solder fixing portion, and a large stress is generated. As a result, the ceramics or solder portion of the wiring board may be destroyed, and it becomes difficult to ensure the reliability of the sealing connection.
[0013]
Further, when horizontal deformation is constrained by the above-described solder fixation, the module undergoes vertical bending deformation due to the bimetal effect, and as a result, the gap between the cap and the wiring board changes greatly. That is, the thickness of the thermally conductive compound applied between the cap and the semiconductor device may increase or peel off, making it difficult to ensure the reliability of the cooling performance.
[0014]
As a sealing portion structure for improving this point, there is a structure disclosed in Japanese Patent Laid-Open No. 2000-349211. In the structure of FIG. 5, an O-ring or a plastic with good slidability is interposed between an air-cooled heat sink that does not match the thermal expansion coefficient of the wiring board and a frame or upper frame that matches the thermal expansion coefficient of the wiring board. Thus, it is possible to seal without restraining the deformation in the horizontal direction due to the difference in thermal expansion between the air-cooled heat sink and the frame or upper frame. For this reason, the stress which generate | occur | produces in the solder fixed part of a frame and a wiring board is reduced significantly, and sealing connection reliability can be ensured.
[0015]
Further, since no vertical bending deformation occurs, there is no problem of an increase in the thickness of the heat conductive compound and a decrease in cooling performance due to peeling. However, in the above structure, since the air cooling heat sink is provided inside the frame, the area of the cooling fin of the air cooling heat sink is inevitably smaller than the inner frame size of the frame, leading to a decrease in cooling performance. . For this reason, with the increase in the amount of heat generated in the entire module, it becomes difficult to ensure the cooling performance of the module with the air-cooled heat sink having the above structure.
[0016]
An object of the present invention is to provide a multichip module sealing structure that improves the problems of the prior art described above and (1) improves sealing connection reliability and (2) has excellent cooling performance.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a first frame is provided on the peripheral edge of a wiring board on which a plurality of semiconductor devices are mounted, and a large and wide cooling region is provided so as to cover the first frame. A cooling body cover is provided, and the first frame is fastened between the second frame and the cover through a member having excellent slidability and a member having a large amount of elastic deformation.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, each embodiment according to the present invention will be specifically described with reference to FIGS. 1, 2, and 3.
[Example 1]
FIG. 1 is a cross-sectional view of a multi-chip module sealing structure showing the configuration of the first embodiment of the present invention. In FIG. 1, a large number of semiconductor devices 2 are mounted on a wiring substrate 1 such as ceramic. The wiring substrate 1 has a thermal expansion coefficient that matches that of the semiconductor device 2. Input / output pins 3 are provided on the back surface of the wiring board 1.
[0019]
The lower surface of the first frame 5 made of an iron-nickel alloy has a thermal expansion coefficient that matches the thermal expansion coefficient of the wiring board 1 and is soldered 8 to the surface on which the semiconductor device 2 of the wiring board 1 is mounted.
[0020]
The upper part of the first frame 5 extends to the outside of the wiring board 1, and the upper surface of the first frame 5 is a flange surface provided with an O-ring groove.
[0021]
The lower surface of the peripheral portion of the air-cooled heat sink 7 is a flange surface, and a rubber O-ring 11 having excellent elasticity is interposed between the flange surface and an O-ring groove provided on the upper surface of the first frame 5.
[0022]
The second frame 10 has a coefficient of thermal expansion matched to the coefficient of thermal expansion of the air-cooled heat sink 7, and slides relative to the inner middle stage of the second frame 10 and the outer middle stage of the first frame 5. The rubber O-ring is fastened with a bolt 9 between the lower part of the air-cooling heat sink 7 and the second frame 10 while the lower surface of the plastic 6 is pushed up by the second frame 10 through the plastic 6 excellent in 11 is crushed and hermetically sealed.
[0023]
A gap in consideration of assembly accuracy and thermal expansion difference is provided between the inner middle side surface of the second frame 10 and the outer peripheral side surface of the first frame 5, and the upper surface of the first frame 5 is air-cooled. The lower surface of the peripheral portion of the heat sink 7 is provided with a minute gap so as to avoid contact while maintaining airtightness by the rubber O-ring 11, so that the air-cooled heat sink 7 and the second frame 10 are connected to the first frame 5 and the wiring. By not restraining the relative thermal deformation in the horizontal direction with respect to the substrate 1, the vertical deformation of the module is suppressed.
[0024]
Between the air-cooled heat sink 7 and the semiconductor device 2, a thermally conductive compound 4 is provided corresponding to each semiconductor device 2, and the thickness of the thermally conductive compound 4 is suppressed by suppressing deformation in the module vertical direction. Can be kept constant and stable cooling performance can be obtained. Further, by fastening the module sealing bolt 9 from the lower surface of the second frame 10 and providing cooling fins on the entire upper surface of the air-cooling heat sink 7 , high cooling performance by the large heat sink can be ensured. Further, since the structure does not restrain the thermal deformation generated between the air-cooled heat sink 7 or the second frame 10 and the first frame 5 or the wiring board 1 as described above, the first frame 5 and the ceramic wiring It is possible to reduce the stress generated at 8 parts of the solder fixing of the substrate 1 and to secure high sealing part connection reliability.
[0025]
FIG. 2 is a sectional view of a sealing structure for a multichip module according to a second embodiment of the present invention. The second embodiment is the same as the first embodiment except that a module sealing bolt 9 is provided on the upper surface of the peripheral edge of the air-cooled heat sink 4 and fastened.
Example 3
Hereinafter, an embodiment according to the present invention will be described with reference to FIG.
[0026]
FIG. 3 is a cross-sectional view of a sealing structure for a multichip module according to a third embodiment of the present invention. This third embodiment is implemented except that an O-ring groove is provided in the outer middle stage of the first frame 5 and the rubber O-ring 11 is interposed between the first frame 5 and the second frame 10. Same as Example 1. That is, a rubber O-ring 11 is used instead of the plastic 6 in FIG.
[0027]
【The invention's effect】
According to the present invention, a multi-chip module sealing structure that enables high sealing connection reliability and high cooling performance of a high heat-generating semiconductor device has been realized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a multichip module sealing structure according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a multichip module sealing structure showing a second embodiment of the present invention.
FIG. 3 is a cross-sectional view of a sealing structure of a multichip module showing a third embodiment of the present invention.
FIG. 4 is a cross-sectional view of a conventional multichip module sealing structure.
FIG. 5 is a cross-sectional view of a conventional multichip module sealing structure.
[Explanation of symbols]
1, 401, 501... Wiring board 2, 402, 502... Semiconductor device 3, 403, 503... Input / output pins 4, 404, 504. ... First frame 6, 506 ... Plastic 7, 407, 507 ... Air-cooled heat sink 8, 408, 508 ... Solder fixing 9, 509 ... · Bolt 10 ········· Second frame 11, 511 ··· Rubber O-ring 405 ··········· Cap plate 505 ··· .... Frame body 510 ... Upper frame body

Claims (5)

複数の半導体デバイスが一面に搭載され他面に入出力ピンが配された配線基板と、前記半導体デバイスの発熱を外部へ排出させるための熱伝導手段と、前記配線基板の周縁部上面にはんだ固着され上部が該配線基板の外側に広がって中段を有する第一の枠体と、前記半導体デバイスおよび前記第一の枠体の全面を覆うように設けられた熱伝導性の蓋体と、前記蓋体の周縁部下面に設けられ内側に中段を有する第二の枠体と、前記蓋体と前記第一の枠体の上面との間に弾性に優れた部材を介すると共に前記第二の枠体の内側中段と前記第一の枠体の外側中段との間に摺動性又は弾性に優れた部材を介して締結する手段とから構成されたマルチチップモジュールの封止構造であって、前記蓋体の外形サイズを前記半導体デバイスの搭載エリアよりも広く設けることを特徴とするマルチチップモジュールの封止構造。A wiring board in which a plurality of semiconductor devices are mounted on one side and input / output pins are arranged on the other side, heat conduction means for discharging heat generated by the semiconductor device to the outside, and solder fixing to the upper surface of the peripheral edge of the wiring board A first frame body having an upper portion extending outside the wiring substrate and having a middle stage; a thermally conductive lid body provided to cover the entire surface of the semiconductor device and the first frame body; and the lid A second frame body provided on the lower surface of the peripheral edge of the body and having a middle step on the inside ; and a member having excellent elasticity between the lid body and the upper surface of the first frame body, and the second frame body a sealing structure of a multi-chip module is composed of a unit, for fastening through the superior member sliding properties or elasticity between the inner middle and the outer middle of the first frame of the The outer size of the lid is the mounting area of the semiconductor device. Sealing structure of a multi-chip module, characterized in that also provided widely. 前記蓋体が空冷ヒートシンクであることを特徴とする請求項1記載のマルチチップモジュールの封止構造。  The multi-chip module sealing structure according to claim 1, wherein the lid is an air-cooled heat sink. 前記蓋体が熱伝導手段と成し、前記蓋体の外側に空冷ヒートシンクを取り付けることを特徴とする請求項1記載のマルチチップモジュールの封止構造。  2. The sealing structure for a multi-chip module according to claim 1, wherein the lid body constitutes heat conduction means, and an air-cooled heat sink is attached to the outside of the lid body. 前記第二の枠体および前記蓋体と前記第一の枠体との間に介する前記弾性に優れた部材は、少なくともゴムを含む弾性的に変形をする材料であることを特徴とする請求項1記載のマルチチップモジュールの封止構造。The member having excellent elasticity interposed between the second frame body and the lid body and the first frame body is an elastically deformable material including at least rubber. The sealing structure of the multichip module of 1. 前記第二の枠体と前記第一の枠体との間に介する前記摺動性に優れた部材は、少なくともプラスチックを含む相対すべりを可能とする部材であることを特徴とする請求項1記載のマルチチップモジュールの封止構造。 2. The member having excellent slidability interposed between the second frame and the first frame is a member capable of relative sliding including at least plastic. Multi-chip module sealing structure.
JP2001252272A 2001-08-23 2001-08-23 Multi-chip module sealing structure Expired - Fee Related JP4051187B2 (en)

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