JP4048731B2 - Image data transfer apparatus and image display processing system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image display processing system for data constituting an image expressed on a plane in a raster scan type display device such as a CRT (Cathode Ray Tube), and more particularly to an image data transfer device for transferring image data of a specific area, and The present invention relates to an image display processing system.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a two-dimensional image data processing apparatus using a raster scan type display device such as a CRT, one disclosed in, for example, Japanese Patent Laid-Open No. 60-214392 is known. As shown in FIG. 19, the image display processing system includes a display controller 101 for image display processing in order to reduce the burden on the central processing unit (CPU) 102. The image data processing circuit 110 inside the display controller 101 is a static image data or a moving image data stored in a video RAM (hereinafter referred to as VRAM) 104 corresponding to the scanning speed of the screen of the CRT display device 105. Is output via the interface 111 and a synchronization signal SYNC necessary for scanning an image is output to the CRT display device 105.
[0003]
The still image and moving image data in this case is composed of a 2, 4 or 8-bit color code that specifies the color of the dot on the display screen, and the image data processing circuit 110 outputs the read color code to the color palette 112. To do. The color palette 112 converts the read color code into RGB (red, green, blue) signals and supplies them to the CRT display device.
[0004]
Further, the image data processing circuit 110 writes the image data supplied from the CPU 102 via the interface 113 to the VRAM 104 during a non-display period (such as a vertical blanking period) of the screen. Further, when accessing the VRAM 104 (during writing and reading), the signal S1 is supplied to the command processing circuit 115 to notify that it is being accessed. The command processing circuit 115 performs processing corresponding to various commands supplied from the CPU 102 via the interface 113.
[0005]
In the image display processing system having the above-described configuration, each bit of the color code of the dot to be transferred can be performed without moving the rectangular area including the still image in a short time without using the CPU, or when the color code is transferred. And a logical operation between each bit of the color code of the transfer destination dot and write the result to the storage area of the VRAM 104 corresponding to the transfer destination dot, and the color code of each dot of the transfer source area Among them, the transparent color code is not transferred, and a transparent process (transparent process) for transferring only the other color codes can be performed. In addition, this system includes a dot unit transfer mode in which a color code is transferred in units of dots and a byte unit transfer mode in which a color code is transferred in units of bytes.
[0006]
[Problems to be solved by the invention]
However, the above-described conventional image display processing system cannot execute predetermined logical operation processing and transparency processing while realizing high-speed transfer. In particular, due to the remarkable improvement in image processing technology and the accompanying rapid increase in the amount of image data transferred, there is no need for fine image processing such as high-speed transfer and setting of pixels to an arbitrary number of bits in the above-described devices. It has become difficult to respond.
[0007]
The present invention has been made in view of such problems, and can perform image processing and transfer data control more efficiently, and can arbitrarily set the number of bits of pixels and effectively use a memory. An object of the present invention is to provide an image data transfer device and an image display processing system that can perform the above-described processing.
[0008]
[Means for Solving the Problems]
The image data transfer device according to the present invention is configured to store the image data of the transfer source region and the image data of the transfer destination region stored in the image data storage device on the basis of the parameters relating to the designated transfer source region and transfer destination region. In the image data transfer apparatus that transfers to the transfer destination area after arithmetic processing, the image data is image data in which one pixel is composed of one or a plurality of bits, and the transfer source area and transfer of the image data storage apparatus An address counter for reading out image data in units of blocks larger than image data of one pixel from the destination area; data storage means for storing image data in units of blocks read from the image data storage device; and The calculation processing is performed by aligning the image data with the image data in the transfer destination area within the block. And a transfer start block address for each scan line including the transfer source area and the transfer destination area, based on the parameters relating to the designated transfer source area and transfer destination area and the number of bits per pixel. Address calculating means for calculating a transfer end block address and setting it in the address counter, and the transfer source area Source mask data to mask Mask areas other than the transfer destination area Destination mask data Mask calculating means for aligning the block in the block between the transfer source area and the transfer destination area, and the address counter is configured such that the upper address of the data storage means is the first address and the lower address is the first address. The first address is fixed, the second address is continuously changed, and the transfer start block including the transfer start block address is continuously transferred to the transfer end block including the transfer end block address. Transfer image data, and based on the transfer image start bit address and transfer image end bit address in each block The source mask data and the destination mask data And the mask calculation means Based on the destination mask data, the source mask data and the destination mask data are The transfer source area and the transfer destination area are used for alignment within the block.
[0009]
In addition, an image display processing system according to the present invention includes an image data storage device that stores image data, and a central processing that outputs parameters relating to a transfer source region and a transfer destination region of the image data stored in the image data storage device. And processing the image data of the transfer source area and the image data of the transfer destination area stored in the image data storage device based on the parameters relating to the transfer source area and the transfer destination area output from the central processing unit In the image display processing system comprising: an image data transfer device that transfers the image data to the transfer destination area; and an image display device that displays the image data stored in the image data storage device. Image data composed of one or a plurality of bits, and the central processing unit includes bits constituting one pixel. The image data transfer device transfers the image data in block units larger than the image data of 1 pixel, and the image data in the transfer source region and the image data in the transfer destination region After performing the arithmetic processing by performing alignment in the block, the data is stored in the image data storage device, and is based on the parameters relating to the designated transfer source area and transfer destination area and the number of bits per pixel. A transfer start block address and a transfer end block address are calculated for each scanning line including the transfer source area and the transfer destination area, the upper address of the image data storage device is the first address, and the lower address is the second address. The first address is fixed, the second address is continuously changed, and the transfer start block address is changed. The image data is continuously transferred from a transfer start block including a transfer end block to a transfer end block including the transfer end block address, and the transfer source is based on the transfer image start bit address and the transfer image end bit address in each block. region Source mask data to mask Mask areas other than the transfer destination area Destination mask data As well as The source mask data and the destination mask data on the basis of the destination mask data The transfer source area and the transfer destination area are used for alignment in the block by using.
[0010]
According to the present invention, the image data in the transfer area stored in the image data storage device is processed based on the parameters relating to the designated transfer source and transfer destination areas (hereinafter referred to as “transfer area” only in this paragraph). When transferring, assuming that the image data is image data in which one pixel is composed of one or a plurality of bits, the image data is transferred in block units larger than the image data of one pixel, and the image data is transferred within the block in the transfer area. The image data can be transferred at high speed by performing the alignment process and performing the arithmetic processing.
[0011]
In the present invention, since one pixel is composed of one or a plurality of bits, one pixel can be expressed with an arbitrary number of bits, and an arbitrary number of colors can be set. And the memory can be used effectively.
[0012]
According to the present invention, the transfer start and transfer end blocks for each scanning line including the transfer source area and the transfer destination area based on the parameters relating to the designated transfer source area and transfer destination area and the number of bits per pixel. By calculating the address and continuously transferring the image data from the transfer start block to the transfer end block, the image data can be transferred at high speed. Furthermore, in the present invention, when a mask pattern for masking other than the transfer area is generated based on the start and end bit addresses of the transfer image in each block, and the alignment within the block is performed in the transfer area, the number of bits of the pixel Even if it is configured, it is possible to perform arithmetic processing by matching the positions of the data of the transfer source and the transfer destination stored at an arbitrary position.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of an image display processing system according to the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram for explaining the basic configuration of an image display processing system according to an embodiment of the present invention.
This image display processing system transfers a local memory 4 composed of a DRAM (Dynamic Random Access Memory) or the like for storing image data to be displayed, and an arbitrary rectangular area of the image data stored in the local memory 4. The CPU 1 that outputs various parameters, the image data transfer device 2 that transfers the image data of the rectangular area on the local memory 4 based on the parameters given from the CPU 1, the image data transfer device 2 and the local memory 4 A memory controller 3 that controls access to image data and a display device 5 such as a CRT display or a liquid crystal display that displays image data in the screen area of the local memory 4. .
[0014]
Among these, the outline of the function of the image data transfer apparatus 2 is shown in FIG. The image data transfer device 2 includes transfer source data (hereinafter referred to as source data) S stored in a non-display area or display area on the local memory 4 and transfer destination data (hereinafter referred to as source data) stored in the display area. (Referred to as destination data.) The CPU 1 receives parameters defining the rectangular areas of D, and parameters defining the rectangular areas of the arbitrary pattern data P stored in the non-display area added to the source data S from the CPU 1. Source, destination, and pattern data are fetched from the local memory 4, a predetermined raster calculation process is performed between these data, and a process of writing to the destination area is executed.
[0015]
Here, the source data S and the destination data D are monochrome data or color data in which one pixel is composed of one or a plurality of bits. Here, the number of bits constituting one pixel is called BPP (bit per pixel).
[0016]
Hereinafter, the image data transfer apparatus 2 will be described in detail.
FIG. 3 is a block diagram showing a detailed configuration of the image data transfer apparatus 2.
Parameters specifying the destination area, source area, and pattern area sent from the CPU 1 are supplied to the destination address calculation circuit 12, the source address calculation circuit 13, and the pattern address calculation circuit 14 via the interface 11, respectively. In these address calculation circuits 12, 13, and 14, a start address (FBSPi) indicating the start of transfer on the local memory 4 in the destination area, source area, and pattern area and an end address indicating the end of transfer (one scan line). FBEPi). The values are passed to the destination address counter 15, the source address counter 16, and the pattern address counter 17, respectively.
[0017]
Further, the image data transfer device 2 includes three SRAMs (Static Random Access Memory) for temporarily storing the image data transferred from the local memory 4, that is, a destination SRAM 18, a source SRAM 19, and a pattern SRAM 20. ing. Each address counter 15, 16, and 17 hierarchizes the local memory 4 in units of sectors, blocks, and bytes, and outputs the addresses of sectors to be transferred to the respective SRAMs 18, 19, and 20. As a result, data for one sector is transferred to the SRAMs 18, 19, and 20 in units of blocks.
[0018]
Since the transfer start pixel and the transfer end pixel are not always the beginning and end of the block, the block at the start and end of transfer may contain data other than the pixel data to be transferred. Each address counter 15, 16, 17 generates mask data for masking these data, and supplies the mask data to the mask operation circuit 23. The mask calculation circuit 23 reads out data from each of the SRAMs 18, 19, and 20 based on the input mask data, and executes a calculation for sending the data to the raster calculation circuit 21. The raster calculation circuit 21 reads sector data from each SRAM 18, 19, 20 in units of blocks, reads the calculation result from the mask calculation circuit 23, performs raster calculation, and stores the calculation result in the output FIFO 22. The data stored in the FIFO 22 is transferred to the destination area of the local memory 4 at a predetermined timing. The controller 24 controls each circuit in accordance with a control command from the CPU 1.
[0019]
FIG. 4 is a flowchart showing a processing flow of the image data transfer apparatus 2.
First, Y = YS is loaded as an initial value of the transfer scan line Y set in each address calculation circuit 12, 13, and 14 (S1). Next, the start address (FBSPi) and end address (FBEPi) of the scan line are calculated by the address calculation circuits 12, 13, and 14 (S2), and the values are passed to the address counters 15, 16, and 17, respectively. It is. Destination data D, source data S, and pattern data P for one sector are transferred from the local memory 4 to the SRAMs 18, 19, and 20 in accordance with the addresses generated by the address counters 15, 16, and 17, respectively (S3, S4). ). After transfer to the SRAMs 18, 19, and 20, data is read from the SRAMs 18, 19, and 20 in units of blocks. The read data is subjected to raster calculation by the raster calculation circuit 21 according to the calculation result by the mask calculation circuit 23 and stored in the output FIFO 22 (S5).
[0020]
If the processing of the sector data stored in the source SRAM 19 is completed (S7), the next sector data is transferred (S4). When the processing of the sector data stored in the destination SRAM 18 is completed, the data stored in the output FIFO 22 is written to the local memory 4 after the raster operation is completed (S8), and new sector data is stored in the destination. The data is transferred to the SRAM 18 (S3). If the processing of the sector data stored in the pattern SRAM 20 is completed (S7), the next sector data is transferred (S4).
[0021]
The above processing is repeated, and when processing of data for one line is completed (S9), Y is updated (S10), and the processing for the next line is started. Then, when the processing of the last line is finished, the processing of the rectangular area is finished (S11).
[0022]
Next, a more specific operation of the image data transfer device 2 will be described.
FIG. 5A is a diagram showing in more detail a rectangular (display) area of image data including a transfer rectangular area. This rectangular area corresponds to the screen area for the destination data D, the screen area or the off-screen area for the source data S, and the off-screen area for the pattern data P. As for source data, a transfer image of color data is shown. Each parameter displayed here is given from the CPU 1 to the image data transfer apparatus 2 as described above, and is as follows.
[0023]
BASE: Data representing the coordinate value on the local memory 4 corresponding to the reference position of the rectangular area including the transfer rectangular area (usually, the position of the upper leftmost pixel of the area) in bits. It may indicate the base point of the screen area, or it may indicate the base point of the off-screen area.
PTCH: Data representing the width of one line of a rectangular area including a transfer rectangular area in the number of bits.
XS: Data representing the transfer start X coordinate value of the transfer rectangular area in pixels.
YS: Data representing the transfer start Y coordinate value of the transfer rectangular area as a scan line.
XEXT: Data representing the width in the X direction of the transfer rectangular area in the number of pixels.
YEXT: Data representing the width of the transfer rectangular area in the Y direction by the number of scan lines.
[0024]
XDIR: Data indicating whether the transfer is performed from the positive or negative direction of X. 0 is positive (rightward) and 1 is negative (leftward). That is, as shown in FIG. 6, when XDIR is 0, XS is the left end of the transfer rectangular area, and X is updated in the positive direction from XS. When XDIR is 1, XS is the right end of the transfer rectangular area, and X is updated in the negative direction from XS.
[0025]
YDIR: Data indicating whether the transfer is performed from the positive or negative direction of Y. Positive (downward) when 0 and negative (upward) when 1. That is, as shown in FIG. 6, when YDIR is 0, YS becomes the upper end of the transfer rectangular area, and Y is updated from YS in the positive direction. When YDIR is 1, YS becomes the lower end of the transfer rectangular area, and Y is updated in a negative direction from YS.
[0026]
Here, the start address (FBSPi) and end address (FBEPi) in the i-th line when given by the scan line Y = i are given by the following equations when XDIR = 0.
[0027]
[Expression 1]
FBSPi = BASE + i × PTCH + XS × BPP
FBEPi = BASE + i × PTCH + (XS + XEXT) × BPP-1
[0028]
When XDIR = 1, it is given by the following equation.
[0029]
[Expression 2]
FBSPi = BASE + i × PTCH + (XS + 1) × BPP-1
FBEPi = BASE + i × PTCH + (XS−XEXT + 1) × BPP
[0030]
FIG. 5B is a diagram showing the start address (FBSPi) and the end address (FBEPi) at Y = i when BASE = 0, as continuous data on the local memory 4.
[0031]
As described above, the start address and the end address calculated by the destination address calculation circuit 12, the source address calculation circuit 13, and the pattern address calculation circuit 14 are the destination address counter 15, the source address counter 16, and the pattern address counter 17, respectively. Is set for each scan line.
[0032]
Each of the address counters 15, 16, and 17 hierarchizes the local memory 4, and performs an interface between the image data transfer device 2 and the local memory 4 for each series of continuous data units via the memory controller 3. Transfer data efficiently. For this reason, the address is decomposed as follows.
[0033]
That is, each of the address counters 15, 16, and 17 converts the received start address (FBSPi) and end address (FBEPi) into sector address k bits and block address m bits from the upper side as shown in FIG. And bit address 8 * 2 ⁿ The local memory 4 is hierarchized by breaking it into bits. The address for designating the entire bit data is k + m + 8 * 2 as shown in FIG. ⁿ = W bits, and the capacity of the local memory 4 is 2 at maximum ^W / 8 bytes. In other words, the local memory 4 is 2 ^k It consists of 1 sector, 1 sector is 2 ^m Consists of blocks. 1 block is 2 ⁿ Consists of bytes. The example of FIG. 7A is an example where m = 3 and n = 1.
[0034]
Number of bytes in one block 2 ⁿ The byte is equal to the data bus width of the local memory 4. That is, 2 is obtained by one access to the local memory 4. ⁿ Data for one byte (one block) can be transferred. Access to local memory 4 is 2 ⁿ It is continuously performed in units of bytes (one block). 2 ⁿ Byte (1 block) data transfer is at least once and at most 2 ^m In the maximum case, data for one sector is continuously transferred. The data bus width of each of the SRAMs 18 to 20 is equal to the bus width of the local memory 4 2 ⁿ It is a byte and the address is m bits. This is equal to the size of data for one sector.
[0035]
As shown in FIG. 7B, higher-speed data transfer is performed by page mode transmission in which the upper address of the local memory 4 is a row address, the lower address is a column address, the row address is fixed, and only the column address is changed continuously. Is realized.
[0036]
FIG. 8 is a diagram showing a basic configuration of the address counters 15 to 17.
The start address (FBSP) is loaded into the start address register 30. At the same time, the FBSP passes through the address update circuit 31 to the upper k bits (FBSP [k + m + 8 * 2 ⁿ −1: m + 8 * 2 ⁿ ]) In the sector address register 32, the central m bits (FBSP [m + 8 * 2 ⁿ -1: 8 * 2 ⁿ ]) In the block address register 33, the lower 8 * 2 ⁿ Bit (FBSP [8 * 2 ⁿ : 0]) are loaded into the bit address register 34, respectively. The end address (FBEP) is loaded into the end address register 35.
[0037]
Prior to fetching data for one sector, first, a sector indicating the address of the sector of the local memory 4 stored in the register 32 in order to transfer the data in the local memory 4 to the destination SRAM 18, the source SRAM 19, and the pattern SRAM 20. An address (SEC) is output to the memory controller 3, and the block indicating the number of blocks to be transferred (BLKCNT) in the sector and the address of the first block to be transferred in the sector (address where the block in the sector starts) A start address (BLKSTR) is calculated by the intra-sector block arithmetic circuit 45 and the like and sent to the memory controller 3. The intra-sector block calculation circuit 45 also calculates a block end address (BLKEND) indicating an address at which the block in the sector ends, in addition to the number of blocks (BLKCNT) and the block start address (BLKSTR) described above.
[0038]
In the calculation by the intra-sector block arithmetic circuit 45, the sector start flag (SECSTRF) that is the output of the sector start comparator 37, the sector end flag (SECENDF) that is the output of the sector end comparator 36, and the start address register 30 are stored. Block start address (FBSP [m + -1: 8 * 2 ⁿ ]), The block end address (FBEP [m + 8 * 2) stored in the end address register 35. ⁿ -1: 8 * 2 ⁿ ]) And XDIR indicating the X direction of transfer are input and used.
[0039]
The sector start comparator 37 receives the sector address (FBSP [k + m + 8 * 2] of the start address from the start address register 30. ⁿ −1: m + 8 * 2 ⁿ ]) And the sector address (SEC) from the sector address register 32, the output data (SECSTRF) is set to 1 when they are equal, and is set to 0 when they are not equal. The sector end comparator 36 compares the sector address (FBEP [k + m + W-1: m + W]) of the end address from the end address register 35 with the sector address (SEC) from the sector address register 32, and outputs an output if they are equal. Data (SECENDF) is set to 1, and is set to 0 when they are not equal.
[0040]
FIG. 9 is a diagram for explaining sector data stored in the sector address register 32.
For example, when XDIR = 0 is defined and SECSTRF and SECENDF are 0, the sector address stored in the sector address register 32 is the first sector of the line constituting the rectangular area as shown in FIG. It turns out that it is not the last sector. In this case, the number of blocks in the sector (BLKCNT) is 2 ^m The block start address (BLKSTR) is 0 and the end address (BLKEND) is 2. ^m-1 It becomes.
[0041]
When SECSTRF is 1 and SECENDF is 0, it can be seen from FIG. 4B that the sector stored in the sector address register 32 is the first sector of the line constituting the rectangular area. In this case, the number of blocks in the sector is 2 ^m -FBSP [m + 8 * 2 ⁿ -1: 8 * 2 ⁿ And the block start address is FBSP [m + 8 * 2 ⁿ -1: 8 * 2 ⁿ ], End address is 2 ^m-1 It becomes.
[0042]
Also, when SECSTRF is 0 and SECENDF is 1, it can be seen from FIG. 5C that the sector stored in the sector address register 32 is the last sector of the line constituting the rectangular area. In this case, the number of blocks in the sector is FBEP [m + 8 * 2 ⁿ -1: 8 * 2 ⁿ ] +1, the start address of the block is 0 and the end address is FBEP [m + 8 * 2 ⁿ -1: 8 * 2 ⁿ ].
[0043]
Further, when both SECSTRF and SECENDF are 1, it can be seen from FIG. 4D that the sector stored in the sector address register 32 is the first sector and the last sector of the line constituting the rectangular area. In this case, the number of blocks is FBEP [m + 8 * 2 ⁿ -1: 8 * 2 ⁿ ] -FBSP [m + 8 * 2 ⁿ -1: 8 * 2 ⁿ ] +1, and the start address of the block is FBSP [m + 8 * 2 ⁿ -1: 8 * 2 ⁿ ] End address is FBEP [m + 8 * 2 ⁿ -1: 8 * 2 ⁿ ]. The above results and the respective cases when XDIR = 1 are summarized in a table as shown in FIG.
[0044]
The block start comparator 39 receives the block address (FBSP [m + 8 * 2] of the start address register 30. ⁿ -1: 8 * 2 ⁿ ]) And the block address (BLK) stored in the block address register 33 are compared, and if equal, the output data (BLKSTRF) is output as 1, and if not equal, 0 is output. Further, the block end comparator 38 receives the block address (FBEP [m + 8 * 2] of the end address register 35. ⁿ -1: 8 * 2 ⁿ ]) And the block address (BLK) stored in the block address register 33 are compared, and if equal, the output data (BLKENDF) is output as 1, and if not equal, 0 is output.
[0045]
Based on the outputs SECENDF, SECSTRF, BLKENDF, and BLKSTRF of the above-described comparators 36 to 39, the start mask calculation circuit 46 calculates a start mask (STRMSK), and the end mask calculation circuit 47 calculates an end mask (ENDMSK). As shown in FIG. 12, the start and end masks are both continuous 8 * 2 consisting of 0 or 1 data. ⁿ It is a bit pattern, and one bit of each mask corresponds to one bit of data read from each SRAM 18, 19, 20 and 8 * 2 ⁿ The bit pattern corresponds to one block of data.
[0046]
The mask logical product operation circuit 48 receives the start and end masks, which are output data from the start and end mask operation circuits 46 and 47, and calculates the logical product data (AMSK), thereby starting address (FBSP). 1 is assigned to a bit existing between the address and the end address (FBEP), and 0 is assigned to the other bit as a flag.
[0047]
In this mask calculation, in addition to the output of the sector start comparator 37 (SECSTRF) and the output of the sector end comparator 36 (SECENDF), the output of the block start comparator 39 (BLKSTRF) and the output of the block end comparator 38 (BLKENDF) Is used. The block start comparator 39 is a block address FBSP [m + 8 * 2] of the start address (FBSP) of the start address register 30. ⁿ -1: 8 * 2 ⁿ ] And the value BLK of the block address register 33, BLKSTRF = 1 if they are equal, and BLKSTRF = 0 if they are not equal. The block end comparator 38 receives the block address FBEP [m + 8 * 2] of the end address (FBEP) of the end address register 35. ⁿ -1: 8 * 2 ⁿ ] And the value BLK of the block address register 33, BLKENDF = 1 if they are equal, and BLKENDF = 0 if they are not equal.
[0048]
The calculation of the start mask (STRMSK) in the start mask calculation circuit 46 is, for example, as shown in FIG. 12, when XDIR = 0 and the FBSP is in the block, that is, when both SECSTRF and BLKSTRF are 1. 8 * 2 ⁿ Binary pattern (8 * 2) where all bits are 1 ⁿ -1 binary representation) is shifted to the left by the number indicated by the bit address (BIT) in the bit address register 34, and zeros are filled from the right. The intra-block start address calculation circuit 49 calculates an address (BITSTR) in the bit pattern at which the mask at this time starts.
[0049]
Similarly, when XDIR = 1 and FBSP is in the block, that is, when both SECSTRF and BLKSTRF are 1, the calculation of the start mask (STRMSK) is 8 * 2. ⁿ Binary pattern (8 * 2) where all bits are 1 ⁿ -1 (binary representation) 8 * 2 ⁿ This is done by shifting to the right by -1-BIT and padding with zeros from the left. The intra-block start address calculation circuit 49 calculates an address (BITSTR) in the bit pattern at which the mask at this time starts. A calculation example of the above shift is shown in FIG.
[0050]
On the other hand, as shown in FIG. 14, the calculation of the end mask in the end mask calculation circuit 47 is 8 * when XDIR = 0 and FBEP is in the block, that is, when both SECENDF and BLKENDF are 1. 2 ⁿ Binary pattern (8 * 2) where all bits are 1 ⁿ -1 (binary representation) 8 * 2 ⁿ -1-FBEP [8 * 2 ⁿ -1: 0] (FBEP [8 * 2 ⁿ -1: 0] is performed by shifting right by the number of FBEP bit addresses) and padding with zeros from the left.
[0051]
Similarly, when XDIR = 1 and FBEP is in a block, that is, when both SEKENDF and BLKENDF are 1, the calculation of the end mask is 8 * 2. ⁿ Binary pattern (8 * 2) where all bits are 1 ⁿ -1 binary representation) to FBEP [8 * 2 ⁿ -1: 0] is shifted to the left, and zeros are padded from the right. Each mask calculated in this way is sent to the mask arithmetic circuit 23 for each block.
[0052]
The address update circuit 31 recognizes the output sector address (SEC) from the sector address register 32 and the output block address (BLK) from the block address register 33 as a series of values, and in the end address register 35 according to an instruction from the controller 24. The address is incremented in increments of BLK until it matches the value of, and the sector address (SEC) and block address (BLK) are updated. In this case, whether the value matches the value in the end address register 35 is detected by the end flag circuit 51 when both SECENDF and BLKENDF are 1.
[0053]
Next, the mask calculation circuit 23 in the image data transfer apparatus 2 will be described.
The mask operation circuit 23 mainly receives mask data AMSK (hereinafter referred to as DSTMSK, SRCMSK, PATMSK, respectively) and blocks sent from the address counters 15, 16, and 17, respectively. Based on the internal start address BYTSTR (hereinafter referred to as DBYTSTR, SBYTSTR, and PBYTSTR), calculations for controlling the data transfer of the image display device 5 are performed. Each start address represents an address at which the mask at that time starts.
[0054]
As shown in FIG. 15, each start address (FBSP) of the destination, source, and pattern points to an arbitrary address of the bit data in the local memory 4. Based on these addresses, the mask arithmetic circuit 23 controls the transfer so that the destination, source, and pattern bits correspond one-on-one from the transfer start bit at the time of data transfer.
[0055]
FIG. 16 is a block diagram showing the internal configuration of the mask arithmetic circuit 23. As shown in FIG.
The mask operation circuit 23 reads out the data from each of the SRAMs 18, 19, and 20 until the sector data of any one of the destination, the source, and the pattern transferred from the local memory 4 to the SRAMs 18 to 20, respectively, is lost. Calculate to output to.
[0056]
First, as shown in FIG. 17A, DSTMSK from the destination address counter 15, SRCMSK from the source address counter 16, and PATMSK from the pattern address counter 17 are input to the mask operation circuit 23, and each mask is inputted. It passes through the selectors 53, 54, 55 and is stored in the respective registers 56, 57, 58. On the other hand, the bit start addresses DBITSTR, SBITSTR, PBITSTR in each block from the address counters 15, 16, 17 pass through the address selectors 60, 61, 62 to the subtractors 63, 64, 65, 66 in the subsequent stage. Entered.
[0057]
The subtractor 63 calculates an address difference (SRCSFT) within one block where the masking of DSTMSK and SRCMSK starts and outputs it to the register 67. Similarly, the subtractor 65 calculates an address difference (PATSFT) within one block where the DSATMSK and PATMSK masks start and outputs the calculated difference to the register 69. The shifters 71 and 72 input the address differences SRCSFT, PATSFT and XDIR output from the subtractors 63 and 65 and stored in the registers 67 and 69, the shifter 71 receives the source mask data SRCMSK, and the shifter 72 receives the pattern mask data PATMSK. Each shifts until the start of the mask matches DSTMSK. The shift at this time is possible in both positive and negative directions with respect to DSTMSK. The result is output from the shifters 71 and 72 to the logic operation circuit 73 as adjusted mask data (SRCADJ, PATADJ), respectively. As shown in FIG. 5A, the logical operation circuit 73 inputs DSTMSK in addition to these mask data and calculates a logical product to determine bits to be processed in DSTMSK.
[0058]
At the same time, the subtracters 64 and 66 calculate the shift numbers (SRCREV and PATREV) corresponding to the shifts in the direction opposite to the direction shifted by the shifters 71 and 72 based on the address differences SRCSFT and PATSFT, and output them to the registers 68 and 70. . The shifters 74 and 75 receive the shift numbers SRCREV and PATREV stored from the registers 68 and 70, respectively, and shift the output mask data (PRCMSK) from the logical operation circuit 73 by the shift numbers to mask (SRCRMV, PATRMV). And is output to the source mask logic operation circuit 77 and the pattern mask logic operation circuit 79, respectively. The masks SRCRMV and PATRMV indicate portions of the source mask SRCMSK and the pattern mask PATMSK that contribute to the calculation of the destination mask DSTMSK.
[0059]
As shown in FIGS. 17C and 17D, the source mask logic operation circuit 77 and the pattern mask logic operation circuit 79 perform masks corresponding to the masks SRCRMV and PATRMV from the source mask SRCMSK and the pattern mask PATMSK, respectively. Calculate the removal. As a result, the masks (SRCUDT, PATUDT) removed and output are updated as SRCMSK and PATMSK to be calculated next, and these are stored in the registers 57 and 58 through the source mask selector 54 and the pattern mask selector 55, respectively. Is done. Both logical operation circuits 77 and 79 output signals (SRCZR and PATZR) indicating that the mask has become zero to the controller 24 when it is determined that there is no mask. Upon receiving the signals SRCZR and PATZR, the controller 24 performs control so that new one block of mask data is stored in the registers 57 and 58 through the source and pattern mask selectors 54 and 55.
[0060]
At this time, the controller 24 instructs the source and pattern address counters 16 and 17 to update the block, and the mask data for one new block output from the address counters 16 and 17 is stored in the registers 57 and 58. Stored in At the same time that the mask data is stored in the registers 57 and 58, new start addresses SBITSTR and PBITSTR are input from the address counters 16 and 17 to the source and pattern address selectors 61 and 62, and then the mask start addresses (SSTAD, PSTAD) is output to the subtracters 63 to 66 as described above.
[0061]
The updated source and pattern masks (SRCMSK, PATMSK) are input to the source priority encoder (SPRIENC) 81 and the pattern priority encoder (PPRIENC) 80, respectively, and addresses SXUDT and PXUDT at which the mask starts are calculated. If the updated mask is not zero, the source and pattern address selectors 61 and 62 use the previously calculated addresses SXUDT and PXUDT as the mask start addresses SSTAD and PSTAD, SSTAD to the subtracters 63 and 64, and PSTAD Output to the subtracters 65 and 66, respectively.
[0062]
On the other hand, as shown in FIG. 17B, the destination mask logic operation circuit 76 performs processing for removing a portion of the input destination mask data DSTMSK that coincides with PRCMSK from the logic operation circuit 73. The removed mask DSTUDT that is the output is updated as DSTMSK to be calculated next, and is stored in the register 56 through the destination mask selector 53. The logic operation circuit 76 also outputs a signal DSTZR indicating that the mask has become zero to the controller 24 when it is determined that the mask does not exist. Upon receiving this signal DSTZR, the controller 24 causes the destination address counter 15 to update the block and output mask data for a new block. This mask data is input to the destination mask selector 53 and stored in the register 56.
[0063]
This updated destination mask DSTMSK is input to a destination priority encoder (DPRIENC) 82, where an address DXUDT at which the mask starts is calculated. If the updated mask is not zero, the destination address selector 60 outputs the previously calculated address DXUDT to the subtracters 63 to 66 as the mask start address DSTAD.
[0064]
In the above mask calculation processing process, for example, when the source mask becomes zero and the update of all blocks in one sector transferred from the local memory 4 to the source SRAM 19 is completed, the controller 24 Is transferred to the source SRAM 19. When the destination mask becomes zero and the update of all the blocks in one sector transferred from the local memory 4 to the destination SRAM 18 is completed, the controller 24 waits for the raster operation by the raster operation circuit 21 to end. Then, the updated destination data stored in the output FIFO 22 is written to the local memory 4 and the next sector data is transferred to the destination SRAM 18. Further, when the pattern mask becomes zero and the update of all blocks in one sector transferred from the local memory 4 to the pattern SRAM 20 is completed, the controller 24 controls to transfer the next sector data to the pattern SRAM 20. I do.
[0065]
At this time, the logic operation circuit 78 calculates a mask (SRCPRC) indicating a part contributing to PRCMSK in the byte pattern of the source data. This mask SRCPRC can be obtained by the following calculation. That is, if the SRCPRC bit is zero, it does not contribute to PRCMSK. However, if it is assumed that the SRCPRC bit of 1 contributes to PRCMSK, SRCPRC = SRCMSK & SRCRMV can be obtained. This is used for the calculation of the enable flag in the subsequent raster operation circuit 21.
[0066]
Next, the raster operation circuit 21 in the image data transfer device 2 will be briefly described. FIG. 18 is a diagram showing an internal configuration of the raster operation circuit 21. The raster operation circuit 21 performs raster operation on the data read from the destination SRAM 18, 18, and 20 of the pattern. .
[0067]
The raster arithmetic circuit 21 mainly shifts the data for one block from the source SRAM 19 in units of bit data, the SB shifter 150 for shifting the data for one block, and the PB for shifting data for one block from the pattern SRAM 20 in units of the bit data. Shifter 151, 8 * 2 to execute 1-bit raster operation ⁿ (= N) 1-bit raster operation circuits 1521 to 152N, 8 * 2 for storing the result of raster operation ⁿ Each register 1541 to 154N and the like.
[0068]
First, 8 * 2 read from the destination SRAM 18 ⁿ The bit destination data is input to the corresponding 1-bit raster arithmetic circuits 1521 to 152n. 8 * 2 read from source SRAM 19 ⁿ The bit source data is shifted bit by bit by the SB shifter 150 by an amount equal to the address difference SRCSFT in one block, which is the shift data calculated by the mask arithmetic circuit 23, and is made to correspond to the destination data. Similarly, 8 * 2 read from the pattern SRAM 20 ⁿ The bit pattern data is also shifted bit by bit by the PB shifter 151 by an amount equal to the PATSFT calculated by the mask operation circuit 23, and is made to correspond to the destination data. The 1-bit raster operation circuits 1521 to 152N perform raster operation on these destinations, sources, and pattern data using the designated code ROPCMD, and store the results in the registers 1541 to 154N. At this time, the registers 1541 to 154N receive the PRCMSK calculated by the mask arithmetic circuit 23 and store only the data for which the PRCMSK becomes 1.
[0069]
The output FIFO 22 following the raster operation circuit 21 writes the result stored in the registers 1541 to 154N into its own memory (not shown) when the raster operation of all the bit data in one block is completed. . When all the data for one destination sector has been written to the memory in the output FIFO 22, the data for one sector is continuously output to the memory controller 3, and the data is written to the local memory 4. Is doing the transfer.
[0070]
【The invention's effect】
As described above, according to the present invention, when the image data of the transfer area stored in the image data storage device is processed and transferred based on the designated transfer source and transfer destination area transfer parameters, Assuming that the data is image data composed of one or a plurality of bits in one pixel, the image data is transferred in units of blocks larger than the image data of one pixel, and alignment processing is performed in the block in the transfer area. By executing the above, it is possible to transfer image data at a high speed, and since image data is composed of one or more bits, one pixel can be expressed by an arbitrary number of bits. In addition, an arbitrary number of colors can be set, and the memory can be used effectively.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining a basic configuration of an image display processing system according to an embodiment of the present invention.
FIG. 2 is a diagram schematically illustrating a function of an image data transfer apparatus in the system.
FIG. 3 is a block diagram showing a detailed configuration of the apparatus.
FIG. 4 is a flowchart showing the operation of the apparatus.
FIG. 5 is a diagram showing in more detail a rectangular (display) area of image data including a transfer rectangular area in the apparatus.
FIG. 6 is a diagram schematically showing XDIR and YDIR of a transfer rectangular area in the apparatus.
FIG. 7 is a diagram showing a configuration of image data constructed in a local memory in the apparatus.
FIG. 8 is a diagram showing a basic configuration inside an address counter in the apparatus.
FIG. 9 is a diagram for explaining sector data stored in a sector address register in the counter.
FIG. 10 is a diagram showing sector data stored in a sector address register in the counter.
FIG. 11 is a diagram for explaining a configuration of each data at the time of mask calculation processing in the counter.
FIG. 12 is a diagram for explaining a procedure for generating each data during a mask calculation process in the counter.
FIG. 13 is a diagram for explaining a result of mask calculation processing in the counter.
FIG. 14 is a diagram for explaining a result of mask calculation processing in the counter.
FIG. 15 is a diagram showing a configuration in a local memory of each start address of destination, source, and pattern in the same apparatus.
FIG. 16 is a block diagram showing an internal configuration of a mask arithmetic circuit in the same device.
FIG. 17 is a diagram for explaining processing of each data in the mask arithmetic circuit in the same device.
FIG. 18 is a diagram showing an internal configuration of a raster arithmetic circuit in the same device.
FIG. 19 is a block diagram illustrating a configuration of a conventional image display processing system.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Image data transfer apparatus, 3 ... Memory controller, 4 ... Local memory, 5 ... Display apparatus, 11 ... Interface, 12 ... Destination address calculation circuit, 13 ... Source address calculation circuit, 14 ... Pattern address calculation Circuits 15 ... Destination address counter 16 ... Source address counter 17 ... Pattern address counter 18 ... Destination SRAM 19 ... Source SRAM 20 ... Pattern SRAM 21 ... Raster arithmetic circuit 22 ... Output FIFO 23 ... Mask arithmetic circuit, 24... Controller.

Claims (2)

The image data in the transfer source area and the image data in the transfer destination area stored in the image data storage device are calculated based on the parameters relating to the designated transfer source area and transfer destination area, and then transferred to the transfer destination area. In the image data transfer device to
The image data is image data in which one pixel is composed of one or a plurality of bits,
An address counter that reads out image data in block units larger than 1-pixel image data from the transfer source area and transfer destination area of the image data storage device;
Data storage means for storing block-unit image data read from the image data storage device;
Arithmetic means for performing the arithmetic processing by aligning the image data of the transfer source area and the image data of the transfer destination area in a block;
Based on the parameters related to the designated transfer source area and transfer destination area and the number of bits per pixel, the transfer start block address and transfer end block address are calculated for each scanning line including the transfer source area and the transfer destination area. Address calculating means for setting the address counter;
A mask operation means for aligning in the block between the transfer source region to a region other than the source mask data and the transfer destination region for masking the non-use destination mask data for masking said transfer source area destination region With
The address counter has a higher address of the data storage means as a first address, a lower address as a second address, the first address is fixed, the second address is continuously changed, and a transfer start block The image data is continuously transferred from a transfer start block including an address to a transfer end block including the transfer end block address, and further, the source based on a transfer image start bit address and a transfer image end bit address in each block Generating mask data and the destination mask data ;
The mask calculation means performs alignment in the block between the transfer source area and the transfer destination area using the source mask data and the destination mask data with reference to the destination mask data. An image data transfer device. An image data storage device for storing image data;
A central processing unit for outputting parameters relating to a transfer source area and a transfer destination area of image data stored in the image data storage device;
After the arithmetic processing of the image data of the transfer source area and the image data of the transfer destination area stored in the image data storage device based on the parameters relating to the transfer source area and the transfer destination area output from the central processing unit, An image data transfer device for transferring to the transfer destination area;
In an image display processing system comprising an image display device for displaying image data stored in the image data storage device,
The image data is image data in which one pixel is composed of one or a plurality of bits,
The central processing unit outputs the number of bits constituting one pixel to the image data transfer device,
The image data transfer device includes:
After transferring the image data in block units larger than the image data of 1 pixel, and performing the arithmetic processing by performing alignment within the block with the image data of the transfer source area and the image data of the transfer destination area, Storing in the image data storage device;
Based on the parameters related to the designated transfer source area and transfer destination area and the number of bits per pixel, the transfer start block address and transfer end block address are calculated for each scanning line including the transfer source area and the transfer destination area. And
The upper address of the image data storage device is a first address, the lower address is a second address, the first address is fixed, the second address is continuously changed, and the transfer start block address is included. Transferring the image data continuously from the transfer start block to the transfer end block including the transfer end block address;
To generate a destination mask data for masking an area other than the source mask data and the transfer destination region for masking other than the transfer source area based on the transfer image start bit address and transfer the image end bit address of said each block, the The image display is characterized in that the transfer source area and the transfer destination area are aligned in a block using the source mask data and the destination mask data on the basis of the destination mask data. Processing system.

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