JP4040600B2 - 2x2 switch and 4x4 switch - Google Patents

Description

  The present invention relates to a multi-input multi-output switch that switches an input signal to an arbitrary output for output, and more particularly to a multi-input multi-output switch that switches a signal path by turning on / off a field effect transistor (FET) or the like. Related to switches and 4x4 switches.

The multi-input multi-output switch is used for switching a signal path in a network node. A conventional n-input n-output switch is composed of n 1-input n-output switches, n n-input 1-output switches, and n ² connection means for connecting these switches to each other. FIG. 19 shows this conventional example described in “Patent Document 1” below.

  Single-pole n-throw (SPnT) switches using FETs are widely used in these multi-input multi-output switches because of their characteristics of wide bandwidth, low power consumption and high-speed switching speed. A conventional example described in “Patent Document 2” below as a 2 × 2 switch is shown in FIG.

This conventional 2 × 2 switch includes SPDT (single pole double throw) switches 9 ₁₁ , 9 ₁₂ , 9 ₂₁ , 9 ₂₂ at input terminals 1 ₁₁ , 1 ₁₂ and output terminals 2 ₁₁ , 2 ₁₂ , respectively. The SPDT switches are connected by _four interconnection transmission lines 5 _{1 to} 5 ₄ , thereby operating as a switch matrix. Each SPDT switch _{9 11,} 9 _12, 9 _{21, 9 22,} has a series shunt FET configuration, for example, in the case of the SPDT switch _{9 11} includes a series FET 3 ₁₁ and the shunt _{FET 3 11S} and series FET 3 ₁₂ It consists of shunt FET3 _12S .

  The operation of this 2 × 2 switch is as follows.

A signal input from the input terminal 1 _{11 is} input to the SPDT switch 9 ₁₁ , and is transmitted to the transmission line 5 _1, which is a connection path to one output side SPDT switch 9 ₂₁ , or to the other output side SPDT switch 9 ₂₂ . is output to the transmission line 5 ₂ Kano either a connection path.

Similarly, the signal input from the input terminal _{1 12} is inputted to the SPDT switch _{9 12,} the transmission line ₃ or a connection path to one of the output-side SPDT switch _{9 21} or other output side SPDT switch 9, a connection route to ₂₂ is output to one of the transmission line 5 _4.

In SPDT switch _{9 21} is controlled to output either a signal from the transmission line _{5 1} or the transmission line ₃ to the output terminal _211, the SPDT switch _{9 22,} the transmission line _{5 2} or transmission lines It is controlled to output either one of the signal to the output terminal 2 ₁₂ from 5 _4.

Here, the gate bias of the FET in the SPDT switch _{9 11} and _{9 21,} series FET 3 ₁₁ of the SPDT switch _{9 11,} a shunt _{FFT3 12S} series FET 3 ₂₁ of the SPDT switch _{9 12,} shunt _{FET 3 22S} and a control terminal ₆₁ from the series FET 3 ₁₂ of the SPDT switch _{9 11,} a shunt _{FET 3 11S} series FET 3 ₂₂ of the SPDT switch _{9 12,} which is to be applied to the common from each shunt _{FET 3 21S} and the control terminal _{6 2.} The output terminal _{2 11, 2 12} are connected to the SPDT switch _{9 21, 9} Similarly, FFT in _22, two control terminals _{6 1} ', _{6 2'} has a configuration capable of applying a gate bias from Yes.

The switch of the series shunt FET configuration controls the series FET to be ON and the shunt FET to be OFF when passing, and controls the series FET to be OFF and the shunt FET to be ON when the switch is cut off. Therefore, in the conventional example shown in FIG. 20, by applying a complementary voltage to the control terminals 6 ₁ , 6 ₁ ′ and 6 ₂ , 6 ₂ ′, (input terminal 1 ₁₁ to output terminal 2 ₁₁ , input terminal 1 ₁₂ to output terminal 2 ₁₂ ) and (input terminal 1 ₁₁ to output terminal 2 ₁₂ , input terminal 1 ₁₂ to output terminal 2 ₁₁ ) can be switched.

  If this FET switch is enlarged and an SPnT switch is constructed, the n-input n-output switch shown in FIG. 19 can be constructed. However, these conventional examples have the following problems.

First, since the signal passing path is connected to the ground by the shunt FETs 3 _11S , 3 _12S , 3 _21S , 3 _22S , a base band signal having a logic level other than 0V is allowed to pass, It is a problem that cannot be shifted.

Second, since n SPnT switches are arranged for both input and output, the circuit scale increases, and the number of control line crossings increases, resulting in degradation of isolation characteristics. Is a point. This conventional configuration also causes a problem that the potential of the FET in the OFF path can be given only from the outside. For example, in the case of a passing state (input terminal 1 ₁₁ to output terminal 2 ₁₁ , input terminal 1 ₁₂ to output terminal 2 ₁₂ ), the potential on the transmission line side such as FETs 3 ₁₂ and 3 _{22 in the} OFF path is shunt FET 3 _12S or 3 Equipotential to ground via _22S . Therefore, in the absence of the shunt FET, either keep connected to ground at high resistance and the like, or can not be given a potential other than to keep applying a bias to the transmission line 5 ₂ or 5 ₃ from the outside, This increases the insertion loss due to the resistance. If the potential of these transmission lines is set in a floating state without setting the potential, the isolation characteristic is deteriorated. When the shunt FET is applied, the first problem remains.

  Thirdly, if the SPDT, which is the smallest unit switch, is made larger than this, it is impossible to make the gate bias common in the series shunt FET configuration, so gate bias control for each series / shunt FET. Wires and control terminals are required, resulting in degradation of isolation characteristics due to an increase in the number of wiring intersections, and an increase in circuit scale and mounting difficulty due to an increase in the number of control terminals. is there.

  Fourthly, when a switch is configured by MESFET or HEMT using a compound semiconductor such as GaAs, the problem is that the positive power supply operation is difficult.

What is important in the characteristics of the switch is the insertion loss of the ON path and the isolation of the OFF path. Of these, the insertion loss mainly depends on the ON resistance (R _ON ) of the FET used, and the isolation mainly depends on the OFF capacitance (Coff) of the FET. For this reason, MESFETs and HEMTs using compound semiconductors such as GaAs that can reduce Ron and Coff are frequently used as high-frequency switch devices.

  However, since MESFETs and HEMTs are generally depletion (normally on) type FETs, the threshold voltage (Vth) is a negative voltage. Therefore, when the drain and source potentials are automatically set to 0V by the shunt FET as in the conventional example, the FET is in the ON state when the gate bias is 0V, and is lower than Vth to turn the FET in the OFF state. A negative voltage is required, and a negative voltage generating circuit is required for the control circuit. In particular, in a portable terminal, since the negative voltage generation circuit occupies a large area for mounting, a positive power supply operation of the FET switch is strongly desired.

Japanese Patent Laid-Open No. 9-9912 Japanese Patent Laid-Open No. 6-232604

  An object of the present invention is to solve the above-mentioned conventional problems, and to provide a switch capable of passing a baseband signal having a logic level other than 0V DC level and capable of positive power supply operation with a simple configuration. is there.

In order to achieve the above object, in claim 1 of the present invention, two input terminals, first and second two single-pole double-throw switches, two output terminals, and a first 2 Two connection means, and two terminals other than the common terminal of the first single-pole double-throw switch and two terminals other than the common terminal of the second single-pole double-throw switch, The second single-pole double-throw switch is common to two terminals other than the common terminal of the first single-pole double-throw switch arranged opposite to each other at a predetermined interval. Terminals facing each other with two terminals other than the terminals are connected by the first two connecting means, respectively, and the two input terminals are the first and second single-pole double throws. Each connected to a common terminal on the switch,
One end of the second two connection means is connected to the two output terminals, and the other end is connected to the first two connection means. One of the second connection means is connected to the second output means. A 2 × 2 switch having a configuration intersecting with the first connection means not connected to the connection means is defined.

  According to a second aspect of the present invention, in the 2 × 2 switch according to the first aspect, a 2 × 2 switch having a configuration in which the two input terminals and the two output terminals are interchanged is defined.

  According to a third aspect of the present invention, in the 2 × 2 switch according to the first or second aspect, the single-pole double-throw switch defines a 2 × 2 switch formed of a micro mechanical switch.

  According to a fourth aspect of the present invention, in the 2 × 2 switch according to the first or second aspect, the drain or source of the single-pole double-throw switch is connected to a common terminal and the other is common. It defines a 2 × 2 switch composed of at least two FETs respectively connected to two terminals other than the terminals.

In claim 5, four input terminals, four single-pole four-throw switches, four output terminals, first four connection means, second four connection means, and both ends And four four single-pole four-throw switches each comprising a first and a second switch pair each consisting of two single-pole four-throw switches. The single-pole four-throw switch that forms the switch pair is arranged such that four terminal sides other than the common terminal face each other at a predetermined interval, and the single-pole four-throw switch of the first switch pair The four terminals that are not the common terminals facing each other are connected to each other by the first four connection means, and the four terminals that are not the common terminals facing each other of the single-pole four-throw switch of the second switch pair are connected. Are connected to each other by the second four connecting means. The four input terminals are respectively connected to the common terminals of the four single-pole four-throw switches, and a connection point that is one end of both ends of the third four connection means is Two connection points connected to the four output terminals, respectively, except for the connection points connected to the four output terminals of each of the third connection means, of the first four connection means It defines a 4 × 4 switch configured to be connected to one different connection means and one different connection means of the second four connection means .

In claim 6, in the 4 × 4 switch according to claim 5,
The four input terminals and the four output terminals define a 4 × 4 switch having a configuration arranged on each side of a square arrangement forming the 4 × 4 switch.

In claim 7, in the 4 × 4 switch according to claim 6,
A 4 × 4 switch in which a low-loss transmission line having a wide line width is connected between the input terminal and the switch, between the output terminal and the switch, or between the input and output terminals and the switch. It is .

In Claim 8, 4 * 4 switch in any one of Claim 5 thru | or 7 WHEREIN: The 4 * 4 switch of the structure which carried out the arrangement | positioning which replaced the said 4 input terminal and the said 4 output terminal. It stipulates.

According to a ninth aspect of the present invention, in the 4 × 4 switch according to any one of the fifth to eighth aspects, the single-pole four-throw switch defines a 4 × 4 switch configured by a micro mechanical switch .

According to Claim 10, in the 4 × 4 switch according to any one of Claims 5 to 8 , the single-pole four-throw switch has one of its drain and source connected to a common terminal and the other common to each other. It defines a 4 × 4 switch composed of at least four FETs connected to four terminals other than the terminals .

In the eleventh aspect, in the 4 × 4 switch according to any one of the fifth to tenth aspects, one set or two sets of first resistors each including four resistors and at least one control terminal Each of the four resistors belonging to each set has one end connected to the control terminal and the other end at least one of the four input terminals or the four output terminals. 4 × 4 switch is specified.

In claim 12, in 4 × 4 switch mounting serial to claim 11, wherein the set or four resistors belonging to at least one set of two sets in, 4 × arrangement is replaced by four inductors It specifies four switches.

In a thirteenth aspect of the present invention, the 4 × 4 switch according to any one of the fifth to twelfth aspects further includes four capacitors, and the four capacitors are connected in series to the four input terminals, respectively. It defines a 4x4 switch with a connected configuration .

In the fourteenth aspect of the present invention, the 4 × 4 switch according to any one of the eleventh and twelfth aspects further includes eight capacitors, and the four input terminals and the four output terminals respectively include the capacitors. It defines a 4 × 4 switch having a configuration in which eight capacitors are connected in series .

  The 2 × 2 switch and the 4 × 4 switch according to the present invention are each composed of half the number of conventional examples, that is, two SPDT switches and four SP4T switches, and each SPDT switch and SP4T switch. Is composed of series FETs, and further has a main feature that a resistor or an inductor is connected to each input terminal or output terminal.

  For this reason, since the potentials of the source / drain of all FETs in the switch can be made the same as the potential of the input terminal, a baseband signal having a logic level other than the DC level of 0V can be passed as it is. Further, if a capacitor is connected in series to the input terminal, a level shift function can be added by applying a bias from either one of the input / output terminals. Therefore, it greatly contributes to the small size and high performance of Ethernet (registered trademark) switches and routers. Further, since positive power supply operation is possible, it is possible to contribute to miniaturization and high performance of the wireless communication terminal.

[First Embodiment]
FIG. 1 is a diagram showing a 2 × 2 switch according to the first embodiment of the present invention. This 2 × 2 switch has two input terminals 1 ₁ , 1 ₂ , two SPDT switches 9 ₁ , 9 ₂ , and four connection means 13 ₁₁ , 13 ₁₂ , 13 ₂₁ , 13 _22. Output terminals 2 ₁ and 2 ₂ . SPDT switch ₉ 1, _{9 2} are the same configuration, when the SPDT switch _{9 1,} two _{FET 3 11, 3 12,} formed of the two resistors ₄ 11 connected to the gate of the _{FET, 4 12} The Here, the input terminals 1 ₁ and 1 ₂ are connected to the common terminal of the SPDT switch, and one of the sources or drains of the FETs 3 ₁₁ , 3 ₁₂ is connected to the common terminal to constitute an SPDT switch. The connecting means 13 ₂₂ and connection means 13 _12, as can be arranged to face the input and output terminals to each other and intersecting at the intersection 11. These connecting means can be composed of wires, wirings, or the like. The resistance values of the resistors 4 ₁₁ and 4 ₁₂ are set to a very large value compared to the characteristic impedance of the input / output. One end of each of the resistors 4 ₁₁ and 4 ₂₁ and the resistors 4 ₁₂ and 4 ₂₂ is The control terminals 6 ₁ and 6 ₂ are connected to each other. Preferably, the resistance values of the resistors 4 ₁₁ , 4 ₂₁ , 4 ₁₂ , and 4 ₂₂ are set to the same value. The difference between the left and right embodiments in FIG. 1 is that the input / output terminals are replaced.

FET 3 ₁₁ and _{3 21} gate bias of the control terminal _61, the gate bias FET 3 _{12 3 22} is applied to the common respectively from the control terminal _{6 2.} Therefore, by applying complementary voltages to the control terminals ₆₁ and _{6 2,} FET 3 ₁₁ and _{3 21} was ON or OFF at the same time, it is possible to simultaneously OFF or ON FET 3 ₁₂ and _{3 22.} Therefore, (the input terminal _{1 1} transmission line _{5 12,} the input terminal _{1 2} from the transmission line _{5 22)} or, 2 × 2 (input terminal _{1 1} from the transmission line _{5 11,} the transmission from the input terminal _{1 2} line _{5 21)} Switch matrix operation can be realized.

FIG. 2 shows a simplified equivalent circuit during the switching operation of FIG. 2A on the left side shows a passing state from (input terminal 11 ₁ to output terminal 2 ₁ , input terminal 1 ₂ to output terminal 2 ₂ ), and FIG. 2B on the right side shows (input terminal 1 ₁ 1 to output terminal 2 ₂ and input terminal 12 ₂ to output terminal 2 ₁ ), the ON-state FET is indicated by Ron, and the OFF-state FET is indicated by Coff.

  As described above, all signal passing paths are not connected to the ground because the shunt FET is not used. Therefore, a baseband signal having a logic level other than 0V can be passed. Furthermore, since the input / output terminals are connected in a DC manner via a resistor Ron, the source / drain of all FETs are automatically set to the same potential as the input / output terminals, and the FETs are completely connected. In addition to realizing the ON / OFF operation, a signal having an arbitrary DC level can be automatically passed as it is.

Compared with the conventional example shown in FIG. 20, the number of required SPDT switches and the number of required control lines are halved, and the circuit can be downsized and highly isolated. Furthermore, in the 2 × 2 switch of the present embodiment, since the signal passes through only one FET, in order to achieve the same insertion loss as the conventional example shown in FIG. Two times can be applied. Therefore, since the required gate width of each FET can be halved, the circuit can be further miniaturized.
[Second Embodiment]
FIG. 3 is a diagram showing a 2 × 2 switch according to the second embodiment of the present invention. This embodiment is a modification of the first embodiment illustrated in FIG. 1, and is equal in length to the interconnection transmission lines 5 ₁₁ , 5 ₁₂ , 5 ₂₁ , 5 ₂₂ in order to facilitate high-frequency operation. The point that applied is different. Here, the length of the transmission line is preferably set to 1/36 or less of the wavelength in the line as described with reference to FIG.

  Hereinafter, the operation of the second embodiment will be described focusing on the difference from the first embodiment.

Since the first transmission line 5 ₁₂ and the second transmission line 5 ₂₂ crosses the wiring intersection portion 1 _1, can be arranged opposite each other in the same manner as input and output terminals of the first embodiment It has become. Such cross is for example, an overlay structure sandwiching a dielectric or an insulator, a first transmission line 5 ₁₂ and an air bridge wiring in the wiring intersection portion 11 ₁ one of the second transmission line 5 ₂₂ This can be realized.

Moreover, since the transmission lines 5 ₁₁ , 5 ₁₂ , 5 ₂₁ , and 5 ₂₂ for interconnection are equal in length, it is possible to make the insertion loss and the signal passing time (passing phase) uniform in all two switching states. It has become.

Here, (the input terminal _{1 1} from the output terminal _{2 1,} from the input terminal _{1 2} output terminal _{2 2)} When the passage state of the first transmission line _{5 12} and the second transmission line _{5 22} and each FET 3 ₁₂ when ₃ to ₂₂ open (open) state in the drain or source terminal of, when (output terminal _{2 2} from the input terminal _{1 1,} from the input terminal _{1 second} output terminal _{2 1)} of the passing state of the first transmission line _{5 11} And the second transmission line 5 ₂₁ are open at the drain or source ends of the FETs 3 ₁₁ and 3 ₂₁ , respectively, so that the length of these transmission lines is not negligible compared to the wavelength of the operating frequency band. If this is the case, the switch characteristics will deteriorate as an open stub.

This situation is simulated in FIG. The horizontal axis is the length of the first and second transmission lines (5 ₁₁ , 5 ₁₂ , 5 ₂₁ , 5 ₂₂ ) for interconnection (wavelength in the line), and the vertical axis is when the transmission line length is zero The deterioration amount of insertion loss, reflection loss, and isolation are plotted. From this figure, it can be seen that as the transmission line becomes longer, the effect of the open stub appears gradually, the insertion loss increases, and the reflection loss decreases. On the other hand, isolation is improved by turning over the reduction in reflection loss. For example, when the length of the transmission line is set to 1/36 or less of the in-line wavelength, the deterioration of the reflection loss can be suppressed to 3.5 dB, and the deterioration of the insertion loss can be suppressed to 0.12 dB or less.

Note that the present invention is not limited to the second embodiment illustrated in FIG. 3 and may have a configuration in which the input / output terminals are replaced.
[Third Embodiment]
5 and 6 are diagrams showing a 2 × 2 switch according to the third embodiment of the present invention.
This embodiment provides an embodiment different from the second embodiment illustrated in FIG. The 2 × 2 switch of the present embodiment will be described focusing on differences from the second embodiment illustrated in FIG.

The 2 × 2 switch according to the present embodiment is composed of _two SPDT switches 9 ₁ and 9 ₂ each having two input terminals and two output terminals, and two terminals other than the common terminal facing each other. Yes. SPDT switch ₉ 1, _{9 2} are the same configuration, when the SPDT switch _{9 1,} two _{FET 3 11, 3 12,} formed of the two resistors ₄ 11 connected to the gate of the _{FET, 4 12} The Here, one of the sources or drains of the FETs 3 ₁₁ and 3 ₁₂ is connected to the common terminal to constitute an SPDT switch. The resistance values of the resistors 4 ₁₁ and 4 ₁₂ are set to a very large value as compared with the characteristic impedance of the input / output, and one ends of the resistors 4 ₁₁ and 4 ₂₁ and the resistors 4 ₁₂ and 4 ₂₂ are The control terminals 6 ₁₁ and 6 ₁₂ are respectively connected. Preferably, the resistance values of the resistors 4 ₁₁ , 4 ₂₁ , 4 ₁₂ , and 4 ₂₂ are set to be the same.

In the embodiment shown in FIG. 5, the drain or source terminal sides of the FETs 3 ₁₁ and 3 ₁₂ , 3 ₂₁ and 3 _{22 in} the SPDT switches 9 ₁ and 9 ₂ are arranged facing each other at a predetermined interval, FET 3 _{11 3} and ₂₂ drain or source terminal of the drain or source terminal of the FET 3 ₁₂ and _{3 21,} respectively in addition to the connection together, to intersect the drain or source terminal of the FET 3 ₁₂ and _{3 21,} FET 3 ₁₁ the most important feature 3 ₂₂ of the drain and the source terminal the input terminal 1 ₁ and an input terminal 1 ₂ and that it has connected the. Note that the intersection allows the input / output terminals to be arranged to face each other. A wire, wiring, or the like can be applied to these connections. This embodiment differs from the second embodiment illustrated in FIG. 3, it is possible to shorten the connection length between the SPDT switch 9 _1, 9 _2, more broadband / high frequency switching operation, and The circuit can be reduced in size.

In the 2 × 2 switch of the embodiment shown in FIG. 6, in order to facilitate high-frequency operation, the drain or source terminal of the FETs 3 ₁₁ and 3 _{22 and} the drain or source terminal of the FETs 3 ₁₂ and 3 ₂₁ are respectively connected to the transmission line. 5 _{31, 5 32,} in addition to connecting to each other a transmission line _{5 41, 5 42,} intersects the transmission line _{5 41} by the transmission line _{5 5,} it is connected to the output terminal _{2 1,} and, A low-loss transmission line with a wide conductor width is applied to the input / output transmission lines 12 ₁₁ , 12 ₁₂ , 12 ₁₂ , and 12 ₂₂ , and these input / output transmission lines are connected to input / output terminals that are disposed directly opposite to each other. The main feature is that it is bent so that it can be connected. The gate resistor and the gate bias control line are not shown. In FIG. 6, black circles indicate connection portions, and square portions 11 that are gray with dots indicate intersection portions that are not connected.

  Thereby, it is possible to achieve a layout that can be easily mounted on a package with a configuration in which an increase in insertion loss due to the routing of the input / output transmission line is minimized.

Note that the present invention is not limited to the embodiments illustrated in FIGS. 5 and 6 and may have a configuration in which the input / output terminals are interchanged with each other.
[Fourth Embodiment]
7 to 10 are diagrams showing a 2 × 2 switch according to the fourth embodiment of the present invention. The 2 × 2 switch of this embodiment is a resistor 4 ₅₁ , 4 connected to the input terminal side of the 2 × 2 switch of the second and third embodiments illustrated in FIG. 3, FIG. 5 and FIG. ₅₂ etc. and the control terminal 6 ₃ has a added configure, following explanation will be focused on the difference between the second and third embodiments.

2 × 2 switch of the embodiment shown in FIG. 7, the 2 × 2 switch illustrated in FIG. 3, the resistor 4 _51, 4 to connect the ₅₂ end of the control terminal 6 _3, enter the other end, respectively terminals 1 It is formed by connecting _{one, 1 2.} The resistance values of the resistors 4 ₅₁ and 4 ₅₂ are sufficiently larger than the input / output characteristic impedance, and are preferably set to the same value. Thus, it is possible to apply the same bias voltage to all of the _{FET 3 11,} 3 _12, 3 _{21, 3 22} source and drain from the control terminal _{6 3.} In the present embodiment, connecting the control terminal 6 ₃ via the resistor 4 _51, 4 ₅₂ to the input terminal side, the resistors is no problem even if provided on the output side.

The 2 × 2 switch of the embodiment shown in FIG. 8 is similar to the 2 × 2 switch illustrated in FIG. 3, with one end of the inductors 7 ₁ and 7 ₂ connected to the control terminals 6 ₃₁ and 6 ₃₂ and the other end respectively. The output terminals 2 ₁ and 2 ₂ are connected to each other. The inductances of the inductors 7 ₁ and 7 ₂ are sufficiently large compared to the input / output characteristic impedance in a desired band, and are preferably set to the same value. As a result, the same bias voltage can be applied to the sources and drains of all the FETs 3 ₁₁ , 3 ₁₂ , 3 ₂₁ , and 3 ₂₂ from the control terminals 6 ₃₁ and 6 ₃₂ . Further, when passing a signal including a DC component, the variation in DC level due to the ON resistance of the FET, it also becomes possible to suppress by applying a bias voltage from the control terminal 6 ₃₁ or 6 _32. This is because a voltage drop generated when passing through the FET can be compensated by a bias from the control terminals 6 ₃₁ and 6 ₃₂ . Further, although the inductor is connected to the output terminal side in FIG. 8, it may be connected to the input terminal side.

2 × 2 switch of the embodiment shown in FIG. 9, the 2 × 2 switch illustrated in FIG. 5, the resistor _{4 51, 4 52} one end of and connected to the control terminal _{6 3,} capacitor ₈ and the other end, respectively ₁₁ , connected to _{8 12} constitute further connected a capacitor _{8 11, 8 12} in series with the input terminal ₁ 1, _{1 2.} The resistance values of the resistors 4 ₅₁ and 4 ₅₂ are sufficiently larger than the input / output characteristic impedance, and are preferably set to the same value. Further, the capacitance values of the capacitors 8 ₁₁ and 8 ₁₂ are sufficiently smaller than the input / output characteristic impedance in the signal band used by the impedance, and are preferably set to the same value. If the capacitors 8 ₁₁ and 8 ₁₂ are externally configured by individual components, a capacitor having a large capacitance value can be easily applied, so that a signal having a low frequency component close to direct current can be passed without deterioration. become. Thus, all the _{FET 3} 11 from the control terminal _{6 3,} 3 _12, 3 _{21, 3 22} source and drain at the same time can be applied to the same bias voltage, the level shifting baseband signals to any DC level of Can be output. By applying a voltage of the positive to the control terminal 6 ₃ can output a signal having a positive DC offset voltage, so that it is possible to output a signal having a negative DC offset voltage by applying a negative voltage . Therefore, it is possible to output the input baseband signal by shifting the level of the DC offset voltage to +0.5 V, −0.5 V or the like, for example, in accordance with the interface of the device connected to the subsequent stage. Here, it is possible to use an inductor instead of the resistors 4 ₅₁ , 4 ₅₂ , but in this case, the impedance of the inductor needs to be sufficiently larger than the input / output impedance in the frequency band to be used.

Figure 2 × 2 switch of the embodiment shown in 10, the 2 × 2 switch illustrated in FIG. 6, the one end of the resistor _{4 51, 4 52} and connected to the control terminal _{6 3,} capacitor ₈ and the other end, respectively ₂₁ , _{8 22} and connected to a connection point of the transmission line ₁₂ 21, _{12 22,} further input terminal ₁ 1, _{1 2} and the output terminals ₂ 1, _{2 2} capacitors ₈ 11 in _series, 8 _12, 8 _{21, 8 22} Connected and configured. The resistance values of the resistors 4 ₅₁ and 4 ₅₂ are sufficiently larger than the input / output characteristic impedance, and are preferably set to the same value. Further, the capacitance values of the capacitors 8 ₁₁ , 8 ₁₂ , 8 ₂₁ , and 8 ₂₂ are sufficiently small compared to the input / output characteristic impedance in the signal band used by the impedance, and preferably the same value as each other. Set to If the capacitors 8 ₁₁ , 8 ₁₂ , 8 ₂₁ , and 8 ₂₂ are externally configured with individual components, a capacitor having a large capacitance value can be easily applied, so that a signal having a low frequency component close to DC is also deteriorated. It is possible to pass without. Thus, it is possible to apply all the _{FET 3 11,} 3 _12, 3 _{21, 3 22} same bias voltage to the source and drain from the control terminal _{6 3} independently of external. Therefore, even when a depletion (normally on) type FET whose threshold voltage (Vth) is a negative voltage is used, the potential of the source and drain of the FET can be raised, and a positive power supply operation becomes possible. This enables positive power supply operation even when using MESFETs and HEMTs using compound semiconductors such as GaAs, which have the features of low ON resistance and low OFF capacity, and in particular, miniaturization / high performance of portable terminal devices. Can be planned.

It should be noted that the present invention is not limited to the embodiments illustrated in FIGS. 7 to 10, and the configuration in which the input / output terminals are interchanged with each other, the configuration in which an inductor is used instead of a resistor, A configuration in which resistors and inductors are provided in all terminals may be used.
[Fifth Embodiment]
FIGS. 11A and 11B are diagrams showing a 4 × 4 switch according to the fifth embodiment of the present invention. The 4 × 4 switch shown in FIG. 11A includes four input terminals 1 ₁ to 1 ₄ , four SP4T switches 10 ₁ to 10 ₄ , 16 connection means, and 4 output terminals 2. It is composed of ₂₁ to _24. The SP4T switches 10 ₁ to 10 ₄ all have the same configuration. In the case of the SP4T switch 10 ₁ , the four FETs 3 _{11 to} 3 ₁₄ and four resistors 4 ₁₁ to 4 ₁₄ connected to the gates of these FETs are included. Is done. Here, one of the sources or drains of the FETs 3 _{11 to} 3 ₁₄ is connected to the common terminal to constitute an SP4T switch. Moreover, these connection means can be comprised with a wire or wiring. The resistance value of the resistor _{4 11-4 14} is set to a very large value as compared to the characteristic impedance of the input and output, preferably, the resistance _{4 11-4 14,} 4 _{21-4 24, 4} 31-4 _34, the resistance value of _{4 41-4 44} is set to the same value. FIG. 11B shows that the input / output terminals in FIG. A gate bias control line and a control terminal are not shown.

This 4 × 4 switch is controlled so that one of the FETs in each SP4T is ON and the remaining three are OFF. FIG. 12 is controlled to pass states (input terminal 1 ₁ to output terminal 2 ₄ , input terminal 1 ₂ to output terminal 2 ₃ , input terminal 1 ₃ to output terminal 2 ₂ , input terminal 1 ₄ to output terminal 2 ₁ ). The equivalent circuit is shown in a simplified manner.

As described above, all signal passing paths are not connected to the ground because the shunt FET is not used. Therefore, a baseband signal having a logic level other than 0V can be passed. Furthermore, since the input / output terminals are connected in a DC manner via the resistor Ron, the sources and drains of all the FETs are automatically set to the same potential as the input / output terminals, and the FETs are completely connected. In addition to realizing the ON / OFF operation, a signal having an arbitrary DC level can be automatically passed as it is.
[Sixth Embodiment]
13 and 14 are diagrams showing a 4 × 4 switch according to the sixth embodiment of the present invention. The 4 × 4 switch according to the present embodiment is composed of _four SP4T switches 10 ₁ to 10 ₄ each having four input and output terminals and four terminals other than the common terminals facing each other. . All SP4T switches ₁₀ 1 to 10 ₄ have the same configuration, when the SP4T switches 10 _1, consists of four _{FET 3} 11 and _{to 3 14,} four that are connected to the gates of the FFT resistor _{4 11-4 14} Is done. Here, one of the sources or drains of the FETs 3 _{11 to} 3 ₁₄ is connected as a common terminal to constitute an SP4T switch. The resistance value of the resistor _{4 11-4 14} is set to a very large value as compared to the characteristic impedance of the input and output, preferably, the resistance _{4 11-4 14,} 4 _{21-4 24, 4} 31-4 _34, the resistance value of _{4 41-4 44} is set to the same value. A gate bias control line and a control terminal are not shown. In FIG. 12 and FIG. 13, black circles indicate connection portions, and circles indicated by gray by dots indicate intersection portions that are not connected.

The 4 × 4 switch of the embodiment shown in FIG. 13 includes SP4T switches 10 ₁ and 10 ₄ that form a first switch pair, and SP4T switches 10 ₂ and 10 ₃ that form a second switch pair. the drain or source terminal of the FET is arranged in the oppositely each other at predetermined intervals, the drain or source terminals of the FFT facing each other, a first transmission line _{5 11-5 16} and _{5 21-5 26} respectively in addition to connecting, between the first transmission line _{5 11-5 16 5 21-5 26,} select one by each one place from the first switch pair and a second pair of switches, the second the most main feature that are connected by the transmission line _{5 31-5 34.} For these connections, a wire, wiring, or the like can be applied.

  With such a configuration, the interconnection between the SP4T switches can be made extremely compact and the connection length thereof can be made very short, so that the switch can be reduced in size, reduced in loss, and widened.

Further, by applying the third transmission line _{5 35-5 37,} 4 × 4 has become possible to connect the switch to the output terminal 21 _{to 24} gathered on one side of the.

  Here, the first transmission line and the second and third transmission lines cross each other except at the connection point. Such an intersection may be, for example, an overlay structure with a dielectric or insulator sandwiched therebetween, or one of the first transmission line and the second and third transmission lines as an air bridge wiring at the wiring intersection. Can be realized.

  In the sixth embodiment shown in FIG. 13, since the signal path can be disconnected from the ground by configuring the SP4T switch only with the series FET, a baseband signal having a logic level other than 0V DC level. Can also be passed. Compared with the configuration of the conventional example, the configuration can be such that only one switch through which a signal passes is required, so that the circuit can be reduced in size by reducing the number of required switches. In addition, since the number of required control lines can be greatly reduced by the configuration with only series FETs and the reduction in the number of required switches, high isolation and a reduction in circuit size can be realized. Further, since the required gate width of each FET can be halved, the circuit can be further reduced in size.

The 4 × 4 switch of the embodiment shown in FIG. 14 is a low-loss input / output transmission line 12 _{11 to} 12 _{14 having} a conductor width wider than that of the transmission line for interconnection in the 4 × 4 switch illustrated in FIG. 12 _{21 to} 12 ₂₄ are applied, and these input / output transmission lines are bent so that they can be connected to input / output terminals arranged to face each other directly.

  Thereby, it is possible to achieve a layout that can be easily mounted on a package with a configuration in which an increase in insertion loss due to the routing of the input / output transmission line is minimized.

Note that the present invention is not limited to the embodiment illustrated in FIGS. 13 and 14 and may have a configuration in which the input / output terminals are replaced.
[Seventh embodiment]
15 to 18 are diagrams showing a 4 × 4 switch according to the seventh embodiment of the present invention.

4 × 4 switch of the embodiment, the 4 × 4 switch of the sixth embodiment illustrated in FIG. 14, the resistor 4 ₅₁ has a added configure to 4 _54, and the like, and the control terminal 6 _3, The difference from the sixth embodiment will be mainly described.

Figure 4 × 4 switch embodiment shown in 15, the 4 × 4 switch illustrated in FIG. 14, the resistance _{4 51-4 54} one end of and connected to the control terminal _{6 3,} enter the other end, respectively terminals 1 It is configured by connecting to ₁ to 1 _4. The resistance values of the resistors 4 ₅₁ to 4 ₅₄ are sufficiently larger than the input / output characteristic impedance, and are preferably set to the same value. Thus, it is possible to apply all the _{FET3 11 ~3 14, 3 21 ~3} 24, 3 31 ~3 34, 3 41 ~3 44 same bias voltage to the source / drain from the control terminal _{6 3.}

The 4 × 4 switch of the embodiment shown in FIG. 16 is similar to the 4 × 4 switch illustrated in FIG. 14, with one end of inductors 7 _{1 to} 7 ₄ connected to control terminals 6 _{31 to} 6 ₃₄ and the other end respectively. and it constituted by connecting the output terminals 21 _{to 24.} Note inductance of the inductor 7 _{1-7 4,} its impedance is compared to the characteristic impedance of the input and output in the desired band is sufficiently large value, preferably set to the same value. Thus, is possible to apply all the _{FET3 11 ~3 14, 3 21 ~3} 24, 3 31 ~3 34, 3 41 ~3 44 same bias voltage to the source / drain from the control terminal _{6 31-6 34} it can. Further, when a signal including a DC component is passed, it is possible to suppress a change in DC level caused by the ON resistance of the FET or the like by applying a bias voltage from the control terminals 6 _{31 to} 6 ₃₄ . This voltage drop occurring when passing through the FET, is because it becomes possible to compensate by a bias from the control terminal 6 _3. In FIG. 16, a control terminal is individually provided for each inductor, but this control terminal may be shared by one inductor.

4 × 4 switch embodiment shown in FIG. 17, the 4 × 4 switch illustrated in FIG. 14, the resistance _{4 51-4 54} one end of and connected to the control terminal _{6 3,} capacitor ₈ and the other end, respectively ₁₁ 8 ₁₄ and connected to a connection point between the transmission line _{12 11-12 14} constitute further connected to the capacitor _{8 through} 11 _{8 14} in series with the input terminal ₁ 1 to 1 _4. The resistance values of the resistors 4 ₅₁ to 4 ₅₄ are sufficiently larger than the input / output characteristic impedance, and are preferably set to the same value. Further, the capacitance values of the capacitors 8 ₁₁ to 8 ₁₄ are sufficiently smaller than the input / output characteristic impedance in the signal band used by the impedance, and are preferably set to the same value. If the capacitors 8 ₁₁ to 8 ₁₄ are externally configured with individual components, a capacitor having a large capacitance value can be easily applied, so that a signal having a low frequency component close to direct current can be passed without deterioration. become. Thus, the control terminal _{6 3} All from _{8 11-8 14,} 8 _{21-8 24} source / drain of the same time it is possible to apply a same bias voltage, the level shifting baseband signals to any DC level Can be output. By applying a voltage of the positive to the control terminal 6 ₃ can output a signal having a positive DC offset voltage, so that it is possible to output a signal having a negative DC offset voltage by applying a negative voltage . Therefore, it is possible to output the input baseband signal by shifting the level of the DC offset voltage to +0.5 V, −0.5 V or the like, for example, in accordance with the interface of the device connected to the subsequent stage. In this case also, although the use of inductors in place of the resistor 4 ₅₁ to 4 ₅₄ are possible, in this case it needs to be sufficiently larger than the input and output impedances in the frequency band in which the impedance of the inductor is used is there.

4 × 4 switch embodiment shown in FIG. 18, the 4 × 4 switch illustrated in FIG. 14, one end of the resistor _{4 51-4 54} connected to the control terminal _{6 3,} the other end capacitors _{8 21} - 8 ₂₄ and transmission lines 12 _{21 to} 12 ₂₄ are connected to the connection points, respectively, and capacitors 8 ₁₁ to 8 ₁₄ and 8 ₂₁ to 8 ₂₄ are connected in series to the input terminals 1 ₁ to ₁₂ and the output terminals 2 ₁ to _{2 2.} Are connected and configured. The resistance values of the resistors 4 ₅₁ to 4 ₅₄ are sufficiently larger than the input / output characteristic impedance, and are preferably set to the same value. In addition, the capacitance values of the capacitors 8 ₁₁ to 8 ₁₄ and 8 ₂₁ to 8 ₂₄ are sufficiently smaller than the input / output characteristic impedance in the signal band used by the impedance, and preferably have the same value. Is set. If the capacitors 8 ₁₁ to 8 ₁₄ and 8 ₂₁ to 8 ₂₄ are externally configured by individual components, a capacitor having a large capacitance value can be easily applied, so that a signal having a low frequency component close to DC is also deteriorated. It is possible to pass without. Thus, applying the same bias voltage to all of the _{FET3 11 ~3 14, 3 21 ~3} 24, 3 31 ~3 34, source and drain of 3 _{41-3 44} from the control terminal _{6 3} independently of external be able to. Therefore, even when a depletion (normally on) type FET whose threshold voltage (Vth) is a negative voltage is used, the potential of the source and drain of the FET can be raised, and a positive power supply operation becomes possible. This enables positive power supply operation even when using MESFETs and HEMTs using compound semiconductors such as GaAs, which have the features of low ON resistance and low OFF capacity, and in particular, miniaturization / high performance of portable terminal devices. Can be planned.

It should be noted that the present invention is not limited to the embodiment illustrated in FIGS. 15 to 18, but the configuration in which the input / output terminals are replaced, the configuration in which an inductor is used instead of the resistor, and the resistance is used instead of the inductor, and the input / output terminal. All of these may be provided with resistors and inductors.
[Other embodiments]
The SPDT switch and the SP4T switch in the 2 × 2 switch and the 4 × 4 switch exemplified in this embodiment may be configured by a micro mechanical switch (MEMS: Micro-Electro-Mechanica 1 Switch) instead of the FET. In this case, the loss of the switch and the high isolation can be achieved, although there is a demerit that the control voltage is increased and the switching time is delayed as compared with the configuration using the FET. Further, part or all of the 2 × 2 switch and the 4 × 4 switch exemplified in this embodiment are preferably integrated on a semiconductor substrate. Furthermore, the switch is not limited to the 2 × 2 switch and the 4 × 4 switch exemplified in the present embodiment, and may be a switch with more inputs and more outputs. For example, if an SP8T switch is used as a unit switch and a method similar to the 4 × 4 switch exemplified in the present embodiment is applied, it can be easily analogized that an 8 × 8 switch can be configured.

The circuit block diagram which shows the 2 * 2 switch of 1st Embodiment. FIG. 3 is a simplified equivalent circuit diagram showing two states of the 2 × 2 switch according to the first embodiment. The circuit block diagram which shows the 2 * 2 switch of 2nd Embodiment. The characteristic view by simulation of the 2nd circuit. The circuit block diagram which shows the 2 * 2 switch of 3rd Embodiment. The circuit block diagram which shows the 2 * 2 switch of the modification of 3rd Embodiment. The 2nd circuit block diagram showing the 2x2 switch of a 4th embodiment. The 2nd circuit block diagram which shows the 2 * 2 switch of 4th Embodiment. The 3rd circuit block diagram which shows the 2 * 2 switch of 4th Embodiment. The 4th circuit block diagram which shows the 2 * 2 switch of 4th Embodiment. The circuit block diagram which shows the 4x4 switch of 5th Embodiment. The simple equivalent circuit diagram which shows one passage state of 4x4 switch of 5th Embodiment. The circuit block diagram which shows the 4x4 switch of 6th Embodiment. The circuit block diagram which shows the modification of 4x4 switch of 6th Embodiment. The 1st circuit block diagram which shows the 4x4 switch of 7th Embodiment. The 2nd circuit lineblock diagram showing the 4x4 switch of a 7th embodiment. The 3rd circuit block diagram which shows the 4x4 switch of 7th Embodiment. The 4th circuit block diagram which shows the 4x4 switch of 7th Embodiment. The circuit block diagram which shows the conventional n input n output switch. The circuit block diagram which shows the conventional 2x2 switch.

Explanation of symbols

1 ₁ , 1 ₂ : input terminal 2 ₁ , 2 ₂ : output terminal 3 _{11 to} 3 ₄₄ : FET
4 _{11-4 54:} resistor ₅ 1 _{to 5 4,} 5 _{11-5 34:} transmission line _{61 through 3,} 6 _{31-6 34:} control terminal ₇ 1-7 _4: inductor _{8 21-8 24:} capacitor 9 _{1 to} 9 ₂ : SPDT switch 10 ₁ to 10 ₄ : SP4T switch 11: wiring intersection (crossover)
12 _{11 to} 12 ₂₄ : transmission line for input / output 13 _{11 to} 13 ₂₂ : connection means

Claims (14)

It is composed of two input terminals, first and second single-pole double-throw switches, two output terminals, first two connection means, and second two connection means,
Two terminals other than the common terminal of the first single-pole double-throw switch and two terminals other than the common terminal of the second single-pole double-throw switch are arranged so as to face each other at a predetermined interval.
Two terminals other than the common terminal of the first single-pole double-throw switch arranged opposite to each other and two terminals other than the common terminal of the second single-pole double-throw switch are opposed to each other. Are connected to each other by the first two connecting means,
The two input terminals are connected to common terminals of the first and second single-pole double-throw switches, respectively.
The second two connection means have one end connected to the two output terminals and the other end connected to the first two connection means,
One of said second connecting means, the second 2 × 2 switch that the connection means, characterized in Rukoto such intersects with the first connecting means is not connected. The 2 × 2 switch according to claim 1,
2. A 2 × 2 switch, wherein the two input terminals and the two output terminals are interchanged. The 2 × 2 switch according to claim 1, wherein:
The single-pole double-throw switch is composed of a micro mechanical switch. The 2 × 2 switch according to claim 1, wherein:
The single-pole double-throw switch is composed of at least two FETs, one of which is connected to a common terminal and the other of which is connected to two terminals other than the common terminal. 2x2 switch. Four input terminals, four single-pole four-throw switches, four output terminals, first four connection means, second four connection means, and three connection points including both ends A third four connection means having
  The four single-pole four-throw switches form first and second switch pairs each consisting of two single-pole four-throw switches,
  The single-pole four-throw switch that constitutes the switch pair is arranged such that four terminal sides other than the common terminal face each other at a predetermined interval,
  The four terminals that are not the common terminals facing each other of the single-pole four-throw switch of the first switch pair are connected by the first four connection means, respectively.
  The four terminals that are not the common terminals facing each other of the single-pole four-throw switch of the second switch pair are connected by the second four connection means, respectively.
  The four input terminals are connected to common terminals of the four single-pole four-throw switches, respectively.
  A connection point that is one end of both ends of the third four connection means is connected to the four output terminals, respectively.
  Two connection points excluding connection points connected to the four output terminals of each of the third connection means are different from one connection means of the first four connection means and the second connection point. 4 × 4 switch, characterized in that each of the four connection means is connected to a different connection means. The 4x4 switch according to claim 5,
4. The 4 × 4 switch, wherein the four input terminals and the four output terminals are arranged on each side of a square arrangement forming the 4 × 4 switch. The 4x4 switch according to claim 6,
A low-loss transmission line having a wide line width is connected to any position between the input terminal and the switch, between the output terminal and the switch, or between both the input and output terminals and the switch. 4 switches . The 4 × 4 switch according to any one of claims 5 to 7 ,
4. A 4 × 4 switch characterized in that the four input terminals and the four output terminals are interchanged . The 4 × 4 switch according to any one of claims 5 to 8,
The single-pole four-throw switch is composed of a micro mechanical switch. The 4 × 4 switch according to any one of claims 5 to 8 ,
The single-pole four-throw switch is composed of at least four FETs, one of which is connected to a common terminal and the other of which is connected to four terminals other than the common terminal. 4x4 switch. The 4 × 4 switch according to claim 5, wherein:
1 set or 2 sets of 1st resistance comprised by four resistances, and at least 1 control terminal,
The four resistors belonging to each set have one end connected to the control terminal and the other end connected to at least one of the four input terminals or the four output terminals . 4x4 switch characterized by that. The 4 × 4 switch according to claim 11 ,
4. A 4 × 4 switch , wherein four resistors belonging to at least one of the one or two sets are replaced with four inductors . The 4x4 switch according to any one of claims 5 to 12,
  It also has 4 capacitors,
  4. A 4 × 4 switch, wherein the four capacitors are connected in series to the four input terminals. The 4x4 switch according to any of claims 11 or 12,
It also has 8 capacitors,
4. A 4 × 4 switch , wherein the eight capacitors are connected in series to the four input terminals and the four output terminals, respectively .

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