JP2002208848A - Semiconductor switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize improvement in the on/off ratio and improvement in high- input resistance characteristic without accompanied increase in a circuit scale. SOLUTION: The source of a first FET 11 is connected to an input terminal IN to which a high frequency signal is inputted, the source of a second FET 12 is connected to the drain of the first FET 11, and an output terminal OUT is connected to the drain of the second FET 12. An inductance 13 is connected mutually between the gate of the first FET 11 and the gate of the FET 12. The inductance 13 forms a parallel resonance circuit, together with the parasitic capacitance of the first and second FETs 11 and 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switch circuit using an FET, and more particularly to a semiconductor switch circuit suitable for switching a high frequency signal.

[0002]

2. Description of the Related Art For example, a Schottky type MESFET using a compound semiconductor such as GaAs is used as a semiconductor switch circuit for controlling on / off of a high frequency signal received by an antenna.

FIG. 11 shows a primitive high-frequency switch using one FET. This switch is a FET
51 is the input terminal IN and the drain is the output terminal O
Each of them is connected to a UT, and a gate is connected to a control terminal CONT via a resistor 51. Usually,
Since the source and the drain of the FET have the same structure, the connection between the source and the drain may be reversed.

In this switch, a control terminal CONT
, The gate potential of the FET 50 with respect to the source or drain potential,
If the threshold voltage is set to a value lower than the absolute value of the threshold voltage of 50 (the threshold voltage of the GaAs MESFET is usually negative), it is turned on, and a high-frequency signal supplied to the input terminal IN is output from the output terminal OUT. .

On the other hand, when the gate potential of the FET 50 is set to the same potential as the source or drain potential, the FET 50 is turned off, and the high frequency signal supplied to the input terminal IN is output from the output terminal O.
No output from UT.

The switch shown in FIG. 11 has two problems as described below.

The first problem is that the input signal leaks to the output terminal OUT via the parasitic capacitance in the off state, and the signal transmission amount in the on state and the signal amount in the off state The point is that the on / off ratio, which is the ratio with the transmission amount, cannot be made large.

That is, when the gate potential of the FET 50 is supplied to the gate at the same potential as the source or drain potential or at a potential lower than the absolute value of the threshold voltage with respect to the source and drain potentials, the direct current between the source and drain is reduced. The resistance Rds has a value of approximately several MΩ.

However, the source and drain of the FET 50,
Parasitic capacitances Cds, Cgs, and Cgd as shown exist between the gate and the source and between the gate and the drain, and impedances 1 / ωCds and 1 / ω due to these parasitic capacitances are present.
Since Cgs, 1 / ωCgd (where ω is 2πf, and f is the fundamental frequency of the high frequency signal input to the input terminal IN) is much smaller than the DC resistance Rds, these parasitic capacitances Cds, Cgs, A high-frequency signal input to the input terminal IN leaks to the output terminal OUT via Cgd. For this reason, ON / OFF, which is the ratio of the signal transmission amount when the FET 50 is in the ON state to the signal transmission amount when the FET 50 is in the OFF state, is used.
A large off ratio cannot be obtained.

A second problem is that when a high-frequency signal having a high peak value is input as an input signal, the off-state occurs even though a control signal for turning off the gate is input. It is a point that cannot be maintained. That is, as a condition for keeping the FET 50 in the off state, the voltage amplitude Vp of the input signal is Vp <(Vc− | Vth |) × (C
gd + Cgs) / Cds. Here, Vc is (potential of the path leading to the source / drain of FET 50) −
(The control signal voltage in the OFF state), and Vth is the FET 50
Threshold voltage.

(Vc− | Vth |) × (Cgd + Cgs) / C
When a high voltage exceeding the value of ds is input to the input terminal IN, the input signal causes the DC resistance Rds of the FET 50 to change.
Becomes lower than several MΩ, and the on / off state is switched. That is, the high input resistance is deteriorated.

In order to solve the first problem, conventionally, as shown in FIG. 12, an inductance 52 causing parallel resonance with the parasitic capacitance of the FET 50 at the fundamental frequency of the controlled signal is provided between the source and the drain. Are connected in parallel to each other to cancel the parasitic capacitance and reduce the leakage of the input signal to the output terminal OUT.

Further, in order to solve the first problem, conventionally, as shown in FIG. 13, a transmission path of an input signal (in this case, an output terminal OU to which a drain is connected).
T) and another FET 53 which operates in opposition to the input signal switching FET 50 is connected between the input terminal T) and the ground potential GND.
As a result, leakage of the input signal to the output terminal OUT is reduced by flowing the signal to the ground potential GND. A circuit obtained by combining FIG. 12 and FIG. 13 is also used.

In order to solve the second problem, conventionally, as shown in FIG. 14, FETs 50 are connected in multiple stages (two stages in this example), and the voltage Vc is distributed by the number of stages of the FETs 50. Thus, the voltage applied to one stage of the FET is suppressed.

Further, in order to solve the above-mentioned second problem, conventionally, as shown in FIG. 15, two stages of FETs 50 are connected in series, and the FETs 50 arranged on the input terminal IN side are conventionally connected.
Then, the capacitance 54 is added between the source (input terminal IN) and the gate, and in the FET 50 arranged on the output terminal OUT side, the capacitance 54 is added between the drain (output terminal OUT) and the gate, so that the distribution ratio of the input signal is increased. Change the FET
It has been practiced to suppress the voltage applied per stage.

However, in the conventional device in which individual problems are independently captured and countermeasures are taken as described above, the circuit scale increases if both problems are to be solved.
There is a problem that the cost is increased.

[0017]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor switch circuit having a large on / off ratio and excellent high input resistance. Without significantly increasing the circuit size,
Accordingly, it is an object of the present invention to provide the apparatus without increasing costs.

[0018]

According to the present invention, there is provided a semiconductor switch circuit comprising: an input terminal and an output terminal for a controlled signal; a first FET having one end of a current path connected to the input terminal for the controlled signal; A second FET having one end of the current path connected to the other end of the current path of the first FET, and the other end of the current path connected to the output terminal of the controlled signal; It is characterized by comprising an inductance connected between the gates of the FETs, and a control terminal provided at at least one end of the inductance and supplied with a control signal.

A semiconductor switch circuit according to the present invention includes an input terminal for a controlled signal, first and second output terminals, a first FET having one end of a current path connected to the input terminal for the controlled signal, A second FET having one end of a current path connected to the other end of the current path of the first FET and the other end of the current path connected to a first output terminal of the controlled signal; A first inductance connected between the gates of the second FET, a first control terminal provided at one end of the first inductance, to which a first control signal is supplied, A third FET having one end connected to an input terminal of the current path, one end of a current path connected to the other end of the current path of the third FET, and a current path connected to a second output terminal of the controlled signal. FE to which the other end of is connected
T, a second inductance connected between the gates of the third and fourth FETs, and a second inductance provided at one end of the second inductance and supplied with a second control signal.
And a control terminal.

A semiconductor switch circuit according to the present invention includes an input terminal of a controlled signal, first and second output terminals, a first FET having one end of a current path connected to the input terminal of the controlled signal, A second FET having one end of the current path connected to the other end of the current path of the first FET, and the other end of the current path connected to the first output terminal;
A first inductance connected between the gates of the ET, and a first inductance provided at one end of the first inductance;
A first control terminal to which the control signal is supplied, and a third F terminal having one end of a current path connected to the input terminal of the controlled signal.
ET, a fourth FET having one end of the current path connected to the other end of the current path of the third FET, and the other end of the current path connected to the second output terminal; FE of 4
A second inductance connected between the gates of T, and a second inductance provided at one end of the second inductance;
A second control terminal to which the control signal is supplied, and a fifth FET having one end of a current path connected to the first output terminal.
A sixth FET having one end of the current path connected to the other end of the current path of the fifth FET and the other end of the current path connected to a node of the ground potential; and the fifth and sixth FETs. A third inductance having one end connected to the second control terminal, a seventh FET having one end of a current path connected to the second output terminal, and An eighth FET whose one end of the current path is connected to the other end of the current path of the seventh FET, and the other end of which is connected to the node of the ground potential; and a gate between the seventh and eighth FETs. And a fourth inductance having one end connected to the first control terminal.

[0021] The semiconductor switch circuit of the present invention comprises:
First and second input terminals to which a second controlled signal is supplied, first and second output terminals, and a first FET having one end of a current path connected to the first input terminal; One end of the current path is connected to the other end of the current path of the first FET,
A second output terminal having the other end of the current path connected to the first output terminal;
And a first inductance connected between the gates of the first and second FETs, and a first control provided at one end of the first inductance and supplied with a first control signal. A third FET having one end of a current path connected to the first input terminal and one end of a current path connected to the other end of the current path of the third FET;
FET having the other end of the current path connected to the output terminal of the fourth FET
A second inductance connected between the gates of the third and fourth FETs, and a second control terminal provided at one end of the second inductance and supplied with a second control signal. A fifth FET having one end of a current path connected to the second input terminal, one end of a current path connected to the other end of the current path of the fifth FET, and a current connected to the first output terminal. A sixth FET connected to the other end of the passage, a third inductance connected between the gates of the fifth and sixth FETs, and one end connected to the second control terminal; A seventh FET having one end of a current path connected to an input terminal of the second FET, one end of a current path connected to the other end of the current path of the seventh FET, and another end of the current path connected to the second output terminal. An eighth FET whose end is connected, and a gate of the seventh and eighth FETs. Connected between each other, one end of the first
And a fourth inductance connected to the control terminal.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a semiconductor switch circuit according to a first embodiment of the present invention. This semiconductor switch circuit includes first and second FETs 11, 1
2 and an inductance 13 and a resistor 14. As the first and second FETs 11 and 12, for example, GaAs having a Schottky junction at the gate is used.
A MESFET made of a compound semiconductor such as the above is used. Thus, G having a Schottky junction in the gate
a first and second FETs 11 comprising aAsMESFETs,
12 has a negative threshold voltage of about -1.8 V, for example.

The source of the first FET 11 is connected to an input terminal IN to which a high-frequency signal is input. The first
The source of the second FET 12 is connected to the drain of the FET 11, and the drain of the second FET 12 is connected to the output terminal OUT. The inductance 13 is connected between the gates of the first and second FETs 11 and 12. One end of the inductance 13, that is, the gate of the first FET 11 is connected to the control terminal CONT to which a control signal is input via the resistor 14.

The first and second FETs 11 and 12
Since the source and the drain have the same structure, the connection between the source and the drain may be reversed.

The resistor 14 is provided to prevent a high-frequency signal supplied to the input terminal IN from being transmitted to another circuit via the control terminal CONT.

FIG. 2 shows an equivalent circuit of the semiconductor switch circuit of FIG. In FIG. 2, Rds11 and Rds12 are the DC resistance between the source and the drain of the first and second FETs 11 and 12, Cgs11 and Cgs12 are the parasitic capacitance between the source and gate, and Cdg11 and Cdg12 are the parasitic between the drain and gate. The capacitances Cds11 and Cds12 are parasitic capacitances between the source and the drain, and L is the inductance 14.

Here, the value L of the inductance 13
Are the parasitic capacitance Cdg11 existing between the gate and the drain of the first FET 11 and the second FET 12 under the fundamental frequency included in the input signal supplied to the input terminal IN.
Is set to such a value as to cause parallel resonance together with the parasitic capacitance Cgs12 existing between the gate and the source.

In the semiconductor switch circuit of FIG. 1, a voltage lower than the absolute value of the threshold voltage of the first and second FETs 11 and 12 with respect to the DC potential of the high-frequency signal input to the input terminal IN, for example, When a potential 3 V lower than the DC potential of the high-frequency signal input to the input terminal IN is input to the control terminal CONT as a control signal, the first,
The second FETs 11 and 12 are turned on.

When the first and second FETs 11 and 12 are turned on, the DC resistances Rds11 and Rds12 between the source and drain of the first and second FETs 11 and 12 each have a low value of about several Ω. In this case, the input terminal IN and the output terminal OU
As shown in the equivalent circuit of FIG. 3, the impedance between the DC resistors Rds11 and Rds12 has a value of about several ohms.
And the high-frequency signal input to the input terminal IN is output from the output terminal OUT.

On the other hand, with reference to the DC potential of the high-frequency signal input to the input terminal IN, the first and second FETs 11 and
When a voltage that is not lower than the absolute value of the threshold voltage of No. 12, for example, a signal having the same potential as the DC potential of the high-frequency signal input to the input terminal IN is input to the control terminal CONT as a control signal, the first and second The FETs 11 and 12 are turned off.

In this case, the value of the inductance 13 is set to a value that causes parallel resonance with the parasitic capacitances Cdg11 and Cgs12 under the fundamental frequency included in the high-frequency signal supplied to the input terminal IN. Inductance 1
The parallel resonance impedance of the parallel resonance circuit including the parasitic capacitance 3 and the parasitic capacitances Cdg11 and Cgs12 is theoretically infinite.

Here, the parasitic capacitance Cds11 between the source and the gate is higher than the parasitic capacitance Cds11 between the source and the drain of the first FET 11, and the parasitic capacitance Cds12 between the source and the drain of the second FET 12 is higher. In comparison, it is assumed that the impedance due to the parasitic capacitance Cdg12 between the drain and the gate is higher and the DC resistances Rds11 and Rds12 between the source and the drain are each several tens of KΩ or more.
As a result, the impedance between the input terminal IN and the output terminal OUT depends on the impedance due to the parasitic capacitance Cgs11 between the source and the gate of the first FET 11, the parallel resonance impedance in the parallel resonance circuit, and the second FET.
12 and the impedance due to the parasitic capacitance Cdg12 between the drain and the gate is connected in series.

Here, since the parallel resonance impedance becomes theoretically infinite, the first and second FETs 11, 1
2, the leakage current from the input terminal IN to the output terminal OUT can be reduced. That is, the amount of the input signal leaking to the output terminal OUT can be reduced when the device is off, so that the on / off ratio, which is the ratio of the signal transmission amount in the on state to the signal transmission amount in the off state, is increased. can do.

By the way, in the semiconductor switch circuit of FIG. 1, the impedance Z1 between the input terminal IN and the output terminal OUT when turned off is given by the following equation.

Z1 = 1 / ωCgs11 + ∞ + 1 / ωCdg12 (1) On the other hand, when the inductance 13 is not connected between the gates of the first and second FETs 11 and 12, the input terminal IN and the output terminal at the time of OFF are provided. OUT2 impedance Z2
Is given by the following equation.

Z2 = 1 / ωCgs11 + 1 / ωCgd11 + 1 / ωCdg12 + 1 / ωCgd12 (2) Here, when the ratio Z1 / Z2 between the above equations (1) and (2) is obtained, the following equation (3) is obtained.

Z1 / Z2 = (1 / ωCgs11 + ∞ + 1 / ωCdg12) / (1 / ωCgs11 + 1 / ωCgd11 + 1 / ωCdg12 + 1 / ωCgd12) = ∞ (3) That is, the gates of the first and second FETs 11 and 12 are mutually connected. The impedance ratio between the input and output at the time of off when the inductance 13 is connected between them and when it is not connected is 1: ∞.

However, this is the result of the first approximation,
Actually, the DC resistance component of the inductance 13,
The value of Q of the parallel resonance circuit including the inductance 13 and the parasitic capacitances Cdg11 and Cgs12 decreases due to the influence of the parasitic capacitances Cds11 and Cds12 between the source and the drain of the second FETs 11 and 12, so Does not become infinite.

Incidentally, the high input resistance characteristic described above is as follows.
This corresponds to the maximum input power of the controlled signal that can provide a linear operation in the off state, and is limited on the negative side of the voltage amplitude of the input signal input to the input terminal IN. This is because, when the negative amplitude (peak value) of the input signal increases, the drain potential of the FET due to the capacitance division of the parasitic capacitance and the control terminal CO
The difference between the voltage of the control signal input to NT and the voltage of this FET is
The threshold voltage becomes shallower than the threshold voltage, and the state shifts to the ON state.

Here, the first and second FETs 11,
12, the threshold voltage is -1.8 V and 1 / ωCgs11
= 1 / ωCgd11 = 1 / ωCgs12 = 1 / ωCgd12 = 45
Ω, 1 / ωCds11 = 1 / ωCds12 = 100Ω (however, the fundamental frequency f of the input signal is 5.8 GHz). A GaAs MESFET having a center gate structure is used. The first FET 11 when the voltage amplitude VinL on the negative side of the signal is -4 V
The potential difference Vgd1 between the gate and the drain is given by the following equation (4).

Vgs1 = (1 / ωCgd12 + ∞) / (1 / ωCgs11 + ∞ + 1 / ωCgd12) × VinL−Vc = (45 + ∞) / (45 + ∞ + 45) × VinL−Vc ≒ 1 × (−4V) − (− 3V) =-1V (4) On the other hand, the first FET when the inductance 13 is not connected between the gates of the first and second FETs 11 and 12
The 11 gate-source potential difference Vgs2 is given by the following equation (5).

Vgs2 = (1 / ωCgs11) / (1 / ωCgs11 + 1 / ωCgd11 + 1 / ωCgs12 + 1 / ωCgd12) × VinL−Vc = (1/4) × VinL−Vc = −1V − (− 3V) = + 2V 5) That is, in the semiconductor switch circuit of FIG.
As viewed from the drain of No. 11, the potential of the gate is +1 V,
Since the voltage is sufficiently higher than the threshold voltage -1.8 V of the first FET 11, the first FET 11 can maintain the off state.

On the other hand, when the inductance 13 is not connected, the potential of the gate is -2 V when viewed from the drain of the first FET 11, and this value is lower than the threshold voltage of the first FET 11 -1.8V. It turns on.

That is, according to the semiconductor switch circuit shown in FIG. 1, since the inductance 13 is connected between the gates of the first and second FETs 11 and 12, the input is input to the input terminal IN as compared with the case where the inductance 13 is not connected. Even when the negative value of the voltage amplitude of the high-frequency signal becomes larger, switching from the off state to the on state is prevented. That is, the high input resistance characteristics can be improved.

Next, the ON / OFF state of the semiconductor switch circuit of FIG.
A description will be given of the result obtained by obtaining the effect of improving the off ratio by simulation.

FIG. 4 shows the configuration of a semiconductor switch circuit that has been actually simulated. Two switch circuits having the configuration shown in FIG. 1 are prepared and connected in series between the terminals T1 and T2, a high-frequency signal is input to an intermediate terminal T3, and one of the switches connected between the terminals T1 and T3 A control signal for turning off this switch circuit is input to the control terminal CONT1 of the switch circuit of FIG. 1 and the control terminal CON of the other switch circuit connected between the terminals T2 and T3.
A control signal for turning on this switch circuit is input to T2. As shown in the plan view of FIG. 5A and the sectional view of FIG. 5B, two FETs 11 and 12 constituting each switch circuit have a center gate structure.
aAsMESFET was used.

In FIGS. 5A and 5B, reference numeral 20 denotes Ga.
An As substrate 21 is, for example, an N-type GaAs layer constituting a source, a drain and a channel, and 22 is a gate electrode. The channel width Wg shown in FIG.
4 mm.

FIG. 6 shows that the value of the inductance 13 in the semiconductor switch circuit of FIG. 4 is 1.78 nH (corresponding to the resonance frequency of the parallel resonance circuit when the frequency f of the input high-frequency signal is 5.8 GHz). The circuit of the present invention, the conventional circuit in which the inductance 13 is removed from the semiconductor switch circuit of FIG. 4 and the gates of the two FETs 11 and 12 are connected, and the inductance 13 is removed from the semiconductor switch circuit of FIG. And the channel width Wg of each of the FETs 11 and 12.
Between the terminals T1 and T3 and the terminal T2 in the reference circuit in which
And the gain between T3 and T3.

In FIG. 6, the characteristics a to c are the characteristics of the semiconductor switch circuit in the off state, the characteristics df are the characteristics of the semiconductor switch circuit in the on state, and the characteristics a and d are those of the circuit of the present invention. Characteristics b and e are for the conventional circuit, and characteristics c and f are for the reference circuit.

As is apparent from the figure, when the fundamental frequency f is around 5.8 GHz, the gain between the terminals T1 and T3 is -7 dB (characteristic b) in the case of the conventional circuit. In the circuit (characteristic a), it is -23 dB, and an improvement of 15 dB or more in the off state is achieved.

On the other hand, in the ON state, the fundamental frequency f is 5.
In the vicinity of 8 GHz, the gain between the terminals T2 and T3 is 0.5 dB in the circuit of the present invention (characteristic d).
Good conduction characteristics are obtained.

As described above, the semiconductor switch circuit of FIG. 1 can have a large on / off ratio and excellent high input resistance.

Further, as compared with the conventional circuit shown in FIG. 14, since only the inductance 13 is added, the circuit scale does not increase so much, and there is no possibility that the cost will increase.

FIG. 7 shows a configuration of a semiconductor switch circuit according to a modification of the first embodiment. In the semiconductor switch circuit of FIG. 1, the case where the control terminal CONT is provided only at one end of the inductance 13, that is, only at the gate of the first FET 11, has been described. However, as shown in FIG. Second FE
The control terminals CONT1,
CONT2 is provided, and the same control signal is input to both terminals CONT1 and CONT2, and the first and second FETs 11 and 12 are provided.
May be operated synchronously.

Also in this case, the high-frequency signal is supplied to the control terminal CO.
In order to prevent leakage from NT1 and CONT2, the gates of the first and second FETs 11 and 12 and the control terminal CON
Resistors 14a and 14b are connected between T1 and CONT2.

In the semiconductor switch circuit according to this modification, compared to the semiconductor switch circuit of FIG. 1, a reverse gate leakage current of the FET flows through the inductance 13 so that the gates of the first and second FETs 11 and 12 are separated from each other. Can be further obtained.

FIG. 8 shows a configuration of a semiconductor switch circuit according to the second embodiment of the present invention. In the semiconductor switch circuit according to the second embodiment, as shown in FIG. 1, two switch circuits 31, each comprising two FETs 11, 12, an inductance 13, and a resistor 14,
32 are provided. One switch circuit 31 is connected between the input terminal IN and the first output terminal OUT1,
The other switch circuit 32 is connected between the input terminal IN and the second output terminal OUT2. One switch circuit 31 is controlled by a control signal input to one control terminal CONT1, and the other switch circuit 32 is controlled by an opposite-phase control signal input to the other control terminal CONT2.

That is, the semiconductor switch circuit of FIG.
An input signal input to the input terminal IN is switched and output from the first and second output terminals OUT1 and OUT2.

FIG. 9 shows a configuration of a semiconductor switch circuit according to the third embodiment of the present invention. In the semiconductor switch circuit according to the third embodiment, as in the semiconductor switch circuit according to the second embodiment shown in FIG.
N to the first and second output terminals OUT
1 and OUT2.

In the semiconductor switch circuit of this embodiment, two switch circuits 33 and 34 each including two FETs 11 and 12, an inductance 13 and a resistor 14 are provided.

The switch circuit 33 has a first output terminal O
The switch circuit 34 is connected between the UT1 and the ground potential GND, and the switch circuit 34 is connected between the second output terminal OUT2 and the ground potential GND.

In the semiconductor switch circuit of this embodiment, when a control signal for turning off the switch circuit 31 is input to the control terminal CONT1, the switch is switched according to the control signal input to the control terminal CONT1. The circuit 33 is turned on, and the signal leaking to the first output terminal OUT1 is shunted to the ground potential. Similarly, when a control signal for turning off the switch circuit 32 is input to the control terminal CONT2, the control terminal CONT2
The switch circuit 34 is turned on in response to the control signal input to the second terminal 2, and the signal leaking to the second output terminal OUT2 is shunted to the ground potential.

FIG. 10 shows a configuration of a semiconductor switch circuit according to a fourth embodiment of the present invention. This fourth
The semiconductor switch circuit according to the embodiment is implemented in a switch circuit for a diversity antenna that switches a signal received by two antennas in two directions.

In the semiconductor switch circuit according to the fourth embodiment, as shown in FIG.
4, consisting of 1, 12, an inductance 13 and a resistor 14
The switch circuits 41 to 43 are provided. The switch circuit 41 has a first input terminal IN1 and a first output terminal O
It is connected between UT1. The switch circuit 42 is connected between the first input terminal IN1 and the second output terminal OUT2. The switch circuit 43 has a second input terminal I
It is connected between N2 and the first output terminal OUT1. The switch circuit 44 is connected between the second input terminal IN2 and the second output terminal OUT2.

The switch circuits 41 and 44 are turned on / off in response to a control signal input to the first control terminal CONT1.
Controlled off. The switch circuits 42 and 43 are connected to the second
Is turned on / off in accordance with a control signal input to the control terminal CONT2.

In the semiconductor switch circuit of FIG. 10, the control signal for turning on the switch circuit 41 is the first control signal.
Is input to the control terminal CONT1, the switch circuit 44 is also turned on in response to the control signal input to the control terminal CONT1, and thus is input from the first and second input terminals IN1 and IN2. The two-system antenna signals are output from first and second output terminals OUT1 and OUT2.

On the other hand, when a control signal for turning on the switch circuit 42 is input to the second control terminal CONT2, the switch circuit 43 is also turned on in response to the control signal input to the control terminal CONT2. So that
2 input from the first and second input terminals IN1 and IN2
The system antenna signal is output from the second and first output terminals OUT2 and OUT1, contrary to the above.

In the semiconductor switch circuit having such a configuration, the two FETs 1 of each of the switch circuits 41 to 44 are also provided.
Since the inductance 13 is connected between the gates 1 and 12, the on / off ratio in each of the switch circuits 41 to 44 can be increased, and the input resistance is also excellent. In addition, cost can be suppressed by suppressing an increase in circuit scale.

The present invention is not limited to the above embodiments, and various modifications can be made in the implementation stage without departing from the scope of the invention.

Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements.
For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, at least one of the problems described in the column of the problem to be solved by the invention can be solved and the effects described in the column of the effect of the invention can be solved. In a case where at least one of the effects described above is obtained, a configuration in which this component is deleted can be extracted as an invention.

[0072]

As described above, according to the present invention,
A semiconductor switch circuit having a large on / off ratio and excellent high input resistance characteristics can be manufactured without significantly increasing the circuit scale.
Therefore, it can be provided without increasing the cost.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor switch circuit according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the semiconductor switch circuit of FIG. 1;

FIG. 3 is an equivalent circuit diagram of the semiconductor switch circuit of FIG. 1 in an ON state.

FIG. 4 is a circuit diagram of a semiconductor switch circuit used to simulate the effect of improving the on / off ratio of the semiconductor switch circuit of FIG. 1;

FIG. 5 is a plan view and a cross-sectional view of an FET used in the switch circuit of FIG. 4;

FIG. 6 is a characteristic diagram showing a simulation result of the semiconductor switch circuit of FIG. 4;

FIG. 7 is a circuit diagram showing a configuration of a semiconductor switch circuit according to a modified example of the first embodiment.

FIG. 8 is a circuit diagram showing a configuration of a semiconductor switch circuit according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a semiconductor switch circuit according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a semiconductor switch circuit according to a fourth embodiment of the present invention.

FIG. 11 is a circuit diagram of a primitive high-frequency switch using one FET.

FIG. 12 is a circuit diagram of a conventional semiconductor switch circuit with an improved on / off ratio.

FIG. 13 is a circuit diagram of a conventional semiconductor switch circuit different from FIG. 12 in which an on / off ratio is improved.

FIG. 14 is a circuit diagram of a conventional semiconductor switch circuit with improved high input resistance.

FIG. 15 is a circuit diagram of a conventional semiconductor switch circuit different from FIG. 14 in which high input resistance is improved.

[Explanation of symbols]

 11, 12 ... FET, 13 ... inductance, 14, 14a, 14b ... resistance, 31 to 34, 41 to 44 ... switch circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J055 AX05 AX06 BX17 CX03 DX23 DX83 EX27 EY01 EY05 EY29 EZ14 FX08 FX12 GX01 GX06 GX07

Claims (25)

[Claims] An input terminal and an output terminal for a controlled signal, a first FET having one end of a current path connected to the input terminal of the controlled signal, and a first FET connected to the other end of a current path of the first FET. A second FET having one end connected to the current path and the other end of the current path connected to the output terminal of the controlled signal; an inductance connected between the gates of the first and second FETs; A control terminal provided at at least one end of the inductance and supplied with a control signal. 2. The control terminal according to claim 1, wherein the control terminals are provided at both ends of the inductance.
A semiconductor switch circuit as described in the above. 3. The semiconductor switch circuit according to claim 1, further comprising an element connected between said inductance and said control terminal, said element having a high impedance with respect to said controlled signal. 4. A method according to claim 1, wherein said first and second FETs are lower than an absolute value of a threshold voltage of said first and second FETs with respect to a DC potential in a current path between an input terminal and an output terminal of said controlled signal. And a signal having a binary value consisting of a second value not lower than the absolute value of the threshold voltage is supplied to the control terminal as the control signal.
The semiconductor switch circuit according to any one of the preceding claims. 5. The gate of the first FET and the first FET under a fundamental frequency included in the controlled signal when the control signal takes the first value. Between the other end of the current path and the second F
5. The semiconductor device according to claim 1, wherein a value is set so as to cause parallel resonance between a parasitic capacitance existing between the gate of the ET and one end of the current path of the second FET. 9. The semiconductor switch circuit according to claim 1. 6. The first and second FETs each include:
2. The method according to claim 1, wherein the MESFET is used.
6. The semiconductor switch circuit according to any one of claims 1 to 5. 7. The first and second FETs each include:
6. The semiconductor switch circuit according to claim 1, wherein the semiconductor switch circuit is made of a GaAs MESFET. 8. An input terminal of a controlled signal and first and second output terminals; a first FET having one end of a current path connected to the input terminal of the controlled signal; A second FET having one end of the current path connected to the other end of the current path and the other end of the current path connected to a first output terminal of the controlled signal; a gate of the first and second FETs; A first inductance connected between the first inductance, a first control terminal provided at one end of the first inductance and supplied with a first control signal, and a current path connected to an input terminal of the controlled signal. A third FET having one end connected thereto, one end of a current path connected to the other end of the current path of the third FET, and the other end of the current path connected to a second output terminal of the controlled signal; Between the fourth FET and the gates of the third and fourth FETs. A second inductance that is continued, provided at one end of the second inductance, the semiconductor switching circuit, wherein a second control signal to a second control terminal supplied. 9. A first element which is connected between the first inductance and the first control terminal and has a high impedance with respect to the controlled signal, the second element and the second element. 9. The semiconductor switch circuit according to claim 8, further comprising a second element connected between the control terminal and the second control terminal and having a high impedance with respect to the controlled signal. 10. A control circuit according to claim 6, wherein a reference is made to a DC potential in a current path between an input terminal of the controlled signal and a first or second output terminal. The first and second control signals are binary signals consisting of a first value lower than the absolute value and a second value not lower than the absolute value of the threshold voltage, as the first and second control signals. The semiconductor switch circuit according to claim 8, wherein the semiconductor switch circuit is supplied to a terminal. 11. The first FET operates under a fundamental frequency included in the controlled signal when the first control signal takes the first value.
Between the gate of the first FET and the other end of the current path of the first FET and the parasitic capacitance between the gate of the second FET and one end of the current path of the second FET. And when the second control signal takes the first value, the second inductance is set below the fundamental frequency included in the controlled signal. Between the gate of the third FET and the other end of the current path of the third FET, and between the gate of the fourth FET and one end of the current path of the fourth FET. 10. The semiconductor switch circuit according to claim 8, wherein the value is set so as to cause parallel resonance. 12. The semiconductor switch circuit according to claim 8, wherein each of said first to fourth FETs is constituted by a MESFET. 13. The semiconductor switch circuit according to claim 8, wherein each of said first to fourth FETs comprises a GaAs MESFET. 14. A control signal input terminal and first and second input terminals.
A first FET having one end of a current path connected to the input terminal of the controlled signal, and one end of a current path connected to the other end of the current path of the first FET; A second FET having the other end of the current path connected to the output terminal of the first FET, a first inductance connected between the gates of the first and second FETs, and a first inductance provided at one end of the first inductance. A first control terminal to which a first control signal is supplied; a third FET having one end of a current path connected to an input terminal of the controlled signal; and a current path of the third FET. A fourth FET having one end connected to the other end of the current path and the other end connected to the second output terminal; and a second FET connected between the gates of the third and fourth FETs. And one end of the second inductance. It is, fifth and second control terminal a second control signal is supplied, one end of the current path to the first output terminal connected
A sixth FET having one end of the current path connected to the other end of the current path of the fifth FET, and the other end of the current path connected to a node of the ground potential; A third inductance having one end connected to the second control terminal and a seventh inductance having one end of a current path connected to the second output terminal.
An eighth FET in which one end of a current path is connected to the other end of the current path of the seventh FET, and the other end of the current path is connected to a node of the ground potential; A fourth inductance connected between the gates of the FETs and having one end connected to the first control terminal. 15. The first inductance and the first inductance.
A first element connected between the second inductance and the second control terminal, the first element having a high impedance with respect to the controlled signal; A second element having a high impedance with respect to a third element connected between the third inductance and the second control terminal and having a high impedance with respect to the controlled signal; The semiconductor switch according to claim 14, further comprising: a fourth element connected between a fourth inductance and the first control terminal and having a high impedance with respect to the controlled signal. circuit. 16. The threshold voltage of the first to fourth FETs is higher than a DC potential in a current path between an input terminal of the controlled signal and a first or second output terminal. The first and second control signals are binary signals consisting of a first value lower than the absolute value and a second value not lower than the absolute value of the threshold voltage, as the first and second control signals. 16. A power supply for a terminal.
A semiconductor switch circuit as described in the above. 17. The semiconductor device according to claim 17, wherein the first inductance is configured such that, when the first control signal takes the first value, the first FET operates under a fundamental frequency included in the controlled signal.
Between the gate of the first FET and the other end of the current path of the first FET and the parasitic capacitance between the gate of the second FET and one end of the current path of the second FET. When the second control signal takes the first value, the second inductance is set below the fundamental frequency included in the controlled signal. Between the gate of the third FET and the other end of the current path of the third FET and the fourth FE
The third inductance is set to a value that causes a parallel resonance between a gate of T and a parasitic capacitance existing between one end of the current path of the fourth FET and the third control signal. Takes the first value between the gate of the fifth FET and the other end of the current path of the fifth FET under the fundamental frequency included in the controlled signal. 6 FE
The fourth inductance is set to a value that causes parallel resonance between a gate of T and a parasitic capacitance existing between one end of the current path of the sixth FET and the fourth control signal. Takes the first value, between the gate of the seventh FET and the other end of the current path of the seventh FET under the fundamental frequency included in the controlled signal, and 8 FE
17. The semiconductor device according to claim 14, wherein a value is set so as to cause parallel resonance between a parasitic capacitance existing between the gate of T and one end of the current path of the eighth FET. 9. The semiconductor switch circuit according to claim 1. 18. The semiconductor switch circuit according to claim 14, wherein each of said first to eighth FETs is constituted by a MESFET. 19. The semiconductor switch circuit according to claim 14, wherein each of said first to eighth FETs comprises a GaAs MESFET. 20. First and second input terminals to which first and second controlled signals are supplied, first and second output terminals, and one end of a current path is connected to the first input terminal. Connected first
A second FET having one end of a current path connected to the other end of the current path of the first FET and the other end of the current path connected to the first output terminal; A first inductance connected between the gates of the second FET; a first control terminal provided at one end of the first inductance, to which a first control signal is supplied; A third terminal having one end of the current path connected to the terminal
A fourth FET having one end of a current path connected to the other end of the current path of the third FET and the other end of the current path connected to the second output terminal; A second inductance connected between the gates of the fourth FET; a second control terminal provided at one end of the second inductance, to which a second control signal is supplied; Fifth terminal whose one end of the current path is connected to the terminal
A sixth FET having one end of a current path connected to the other end of the current path of the fifth FET and the other end of the current path connected to the first output terminal; A third inductance connected between the gates of the sixth FET and having one end connected to the second control terminal; and a seventh inductance having one end of a current path connected to the second input terminal.
An eighth FET having one end of a current path connected to the other end of the current path of the seventh FET, and the other end of the current path connected to the second output terminal; A fourth inductance connected between the gates of an eighth FET and having one end connected to the first control terminal. 21. The first inductance and the first inductance.
A first element connected between the second inductance and the second control terminal, the first element having a high impedance with respect to the first controlled signal, and being connected between the second inductance and the second control terminal. A second element having a high impedance with respect to a second controlled signal; connected between the third inductance and the second control terminal; having a high impedance with respect to the second controlled signal; And a fourth element connected between the fourth inductance and the first control terminal and having a high impedance with respect to the first controlled signal. 21. The semiconductor switch circuit according to claim 20, wherein: 22. A threshold value of each of the first to eighth FETs based on a DC potential in a current path between the first and second input terminals and the first and second output terminals. The two-valued signal consisting of a first value lower than the absolute value of the voltage and a second value not lower than the absolute value of the threshold voltage is the first and second control signals as the first and second control signals. 22. The semiconductor switch circuit according to claim 20, wherein the control signal is supplied to the control terminal. 23. The first inductance, when the first control signal takes the first value, generates the first inductance under a fundamental frequency included in the first controlled signal. Between the gate of the FET and the other end of the current path of the first FET and the gate of the second FET and the second FET
Is set to a value that causes parallel resonance with a parasitic capacitance existing between one end of the current path and the second inductance. When the second control signal takes the first value, The third FET, between the gate of the third FET and the other end of the current path of the third FET under the fundamental frequency included in the first controlled signal;
The third inductance is set to a value that causes parallel resonance between the parasitic capacitance existing between the gate of the FET and the one end of the current path of the fourth FET. When the signal takes the first value, the signal between the gate of the fifth FET and the other end of the current path of the fifth FET under the fundamental frequency included in the second controlled signal. Between and the sixth
Is set to a value that causes a parallel resonance between a parasitic capacitance existing between the gate of the first FET and one end of the current path of the sixth FET. The fourth inductance is controlled by the first control. When the signal takes the first value, the signal between the gate of the seventh FET and the other end of the current path of the seventh FET under the fundamental frequency included in the second controlled signal. Between and the eighth
23. A value which causes a parallel resonance between a parasitic capacitance existing between the gate of the first FET and one end of the current path of the eighth FET.
The semiconductor switch circuit according to any one of the preceding claims. 24. The semiconductor switch circuit according to claim 20, wherein each of said first to eighth FETs is constituted by a MESFET. 25. The semiconductor switch circuit according to claim 20, wherein each of said first to eighth FETs comprises a GaAs MESFET.