JPH08213893A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To integrate the entire circuit and to reduce the manufacturing cost by providing a DC block capacitor respectively to both terminals of transistors(TRs) connected in series and using an SPDT switch at a positive power supply. CONSTITUTION: One terminal of bias resistors R1 to R5 is connected to a connecting point and the like in series connection of FETs 11 to 14. Other terminal of the resistors R1 to R5 connects to a point of a power supply voltage VC. Through the constitution above, the FETs 11 to 14 being switches are switched on/off at an area of a positive power supply. Furthermore, a potential is shifted increasingly in terms of DC without loss of an AC-like signal by DC-like block capacitors C1, C2. Thus, when an SPD switch is integrated in the configuration of positive power supply specification, a circuit or the like generating a negative power supply is not required to attain circuit integration and to reduce the cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit that handles frequencies in the UHF band and above, and more particularly to an SPDT (single pole double throu) for switching and outputting two signals.
gh) related to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art SPDs that are built into mobile phones and function as changeover switches for high-frequency transmission / reception signals
There is a T switch circuit. FIG. 2 is a circuit diagram showing a configuration of a conventional SPDT switch. The source / drain current paths of the GaAs field effect transistors (FETs) 11, 12, 13, 14 are connected in series. Both ends of the series connection are grounded. The FETs 11, 12, 13, and 14 have gate terminals connected to resistors 21, 22, 23, and 24 of 10 kΩ or more, respectively. The gate terminal provided with the resistor 21 of the FET 11 and F
The gate terminal of the ET 13 provided with the resistor 23 is commonly connected to the signal control terminal 15. The gate terminal of the FET 12 provided with the resistor 22 and the gate terminal of the FET 14 provided with the resistor 24 are commonly connected to the signal control terminal 16. F
A node N1 at the connection point between ET11 and 12 and a node N2 at the connection point between FETs 13 and 14 are connected to signal input terminals 17 and 18, respectively. The node N3 at the connection point between the FETs 12 and 13 is connected to the signal output terminal 19. 25 to 27 indicate the capacitive load of the circuit to which each terminal is connected.

The SPDT switch circuit configured as described above is an FET
One of the two signals input to the terminals 17 and 18 is selected by using 11, 12, 13, and 14 as switches. That is, the FE is fed by the complementary signals to the signal control terminals 15 and 16.
T11 and 13 are commonly turned ON / OFF, and FETs 12 and 14 are commonly turned OFF / ON.
One of the two signals is selected and output to the terminal 19.

FET in the SPDT switch circuit
Reference numerals 11, 12, 13, and 14 are GaAs field effect transistors, and generally MESF having a Schottky junction is currently used.
It is both ET and depletion type.

Therefore, the depletion type FETs 11 and 1
When using 2, 13 and 14 as switches, the signals to the signal control terminals 15 and 16 are both positive voltage (eg 0V) and negative voltage (eg -3V) to turn on / off the FET.
Need to be controlled by. For this reason, two kinds of power supplies are required when used together with other general semiconductor integrated circuits having a positive power supply specification.

[0006]

As described above, conventionally, the positive voltage and the negative voltage are used as the gate control signal of the GaAs field effect transistor constituting the SPDT switch. As a result, when used in combination with a semiconductor integrated circuit having a positive power supply specification, two kinds of power supplies are required, which hinders the integration of the entire circuit and increases the manufacturing cost.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a structure in which an SPDT switch can be used with a positive power supply, thereby integrating the entire circuit,
An object of the present invention is to provide a semiconductor integrated circuit that contributes to reduction in manufacturing cost.

[0008]

A semiconductor integrated circuit according to the present invention is a field-effect type first, second, third, and third field-effect type semiconductor device having a gate terminal connected to a resistance of 10 kΩ or more and a source terminal and a drain terminal connected in series. A fourth transistor and first, second, third, fourth, and fifth transistors provided so that the voltages of the source and drain terminals of each transistor are level-shifted.
Bias resistors and first and second DC blocking capacitors respectively provided at both ends of the series connection of the transistors in order to cut off a DC component of a signal which is conducted through a series connection path of the transistors. It is characterized in that it is equipped with.

[0009]

According to the present invention, the bias resistance enables the first, second, third, and fourth field-effect transistors forming the switch to be controlled by the positive power supply, and further the DC
The block capacitor upshifts the potential in a DC manner.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an SP according to a semiconductor integrated circuit of the present invention.
It is a circuit diagram which shows the structure of a DT (single pole double through) switch circuit. The source / drain current paths of the GaAs field effect transistors (FETs) 11, 12, 13, 14 are connected in series. These FETs 11, 12, 13,
14 are resistors 21 and 22 of 10 kΩ or more at the gate terminals, respectively.
23 and 24 are provided. Each of these resistors 21 to 24 is composed of a resistance element such as a diffusion resistor or a polysilicon resistor formed near the gate terminal.

One end of the current path of the FET 11, which is one end of the series connection of the FETs 11, 12, 13, and 14, and the FET 11
And 12 current path connection points, FET 12 and 13 current path connection points, and FET 13 and 14 current path connection points,
Bias resistances R1, R2, R3, respectively at one end of the current path of the FET 14 which is the other end of the series connection.
One end of each of R4 and R5 is connected. The other ends of the bias resistors R1 to R5 are commonly connected to a power source that supplies a power source voltage VC.

Further, between one end of the current path of the FET 11, which is one end of the series connection of the FETs 11, 12, 13, and 14 and the ground potential, and between one end of the current path of the FET 14 which is the other end of the series connection and the ground potential. And DC block capacitors C1 and C2 are provided between the two. The gate terminal of the FET 11 provided with the resistor 21 and the gate terminal of the FET 13 provided with the resistor 23 are commonly connected to the signal control terminal 15.
In addition, the gate terminal provided with the resistor 22 of the FET 12 and the FE
The gate terminal provided with the resistor 24 of T14 is commonly connected to the signal control terminal 16.

Nodes N1 and FE at the connection point of FETs 11 and 12
Node N2 at the connection point of T13 and 14 is the signal input terminal
It is connected to 17, 18. The node N3 at the connection point between the FETs 12 and 13 is connected to the signal output terminal 19. twenty five~
27 indicates the capacitive load of the circuit to which each terminal is connected.

According to the above construction, by providing the bias resistors R1 to R5 whose one ends are biased to the positive power source,
The FETs 11 to 14 that compose the switch are turned on in the positive power supply region.
You can turn it off. Further, the DC block capacitors C1 and C2 upshift the potential in a DC manner without impairing the RF-like (AC-like) signal.

For example, assume that an RF signal of about 22 dB is input to the terminal 17 or 18 in the 1.9 GHz band. Then, the resistors 21, 22, 23 and 24 are connected to the resistors Rj1 and Rj.
Each of 2, Rj3 and Rj4 needs to have a resistance of about 10 kΩ, and the DC blocking capacitors C1 and C2 need to have a capacitance of 10 pF or more. The bias resistors R1 to R5 are connected to the output terminal 19 to reduce current consumption.
If the impedance to be added first is 50Ω, it is necessary to have a sufficiently large impedance in terms of RF, which is preferably about 10 kΩ. Under such conditions,
With the power source as VC = 3V, the operation levels of the FETs 11 to 14 are upshifted to enable operation with a positive voltage. Each of the FETs 11 to 14 used has a pinch-off voltage Vp =
It was set to -1.7 to -1.5V. More preferably under this condition, in order to obtain a more accurate output at the terminal 19, the signal is transferred to the output with respect to the saturation current amount Idss (11,14) of the FETs 11 and 14 which plays a role of extracting the residual signal. Saturation current amount Idss (1
The size of each FET may be set so that the ratio of 2,13) is set to 1: 2.

In the figure, the node N1 at the connection point between the FETs 11 and 12 and the node N2 at the connection point between the FETs 13 and 14 are the signal input terminals 17 and 18, and the node N at the connection point between the FETs 12 and 13, respectively.
Although 3 is connected to the signal output terminal 19, the terminal 19 may be the input terminal and the terminals 17 and 18 may be the output terminal side depending on the application.

[0017]

As described above, according to the present invention,
Since the bias voltage is provided and the operating voltage is upshifted in a DC manner by the DC blocking capacitor, it is possible to configure an SPDT switch circuit that can normally control the operation of a depletion type field effect transistor with a positive power supply. . As a result, when this SPDT switch circuit is incorporated in the configuration of the positive power supply specification, a circuit for generating a negative power supply is not required, and a semiconductor integrated circuit that greatly contributes to integration and cost reduction can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an SPDT switch circuit according to a semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional SPDT switch circuit.

[Explanation of symbols]

11, 12, 13, 14 ... GaAs field effect transistor, 15,
16 ... Signal control terminal, 17, 18 ... Signal input terminal, 19 ... Signal output terminal, 21, 22, 23, 24 ... Resistor, 25-27 ... Capacitive load, R
1, R2, R3, R4, R5 ... Bias resistance, C1, C
2 ... DC block capacitor, VC ... Power supply voltage.

Claims (9)

[Claims] 1. Field-effect type first, second, third and fourth transistors each having a gate terminal connected to a resistor of 10 kΩ or more and having source and drain terminals connected in series, and a source-source transistor of each transistor. A direct current component of a signal that is transmitted through a series connection path of the first, second, third, fourth, and fifth bias resistors provided so that the voltage of the drain terminal is level-shifted in the positive direction. A first and a second DC blocking capacitors respectively provided at both ends of the series connection of the transistors for shutting off the semiconductor integrated circuit. 2. A common first control signal is supplied to the gate terminal provided with the resistance of the first transistor and the gate terminal provided with the resistance of the third transistor, and the second transistor is provided. The common second control signal is supplied to the gate terminal provided with the resistance of 4 and the gate terminal provided with the resistance of the fourth transistor, and the respective transistors are controlled to be conductive. 1
The semiconductor integrated circuit described. 3. The first and second transmission ends of a signal which conducts the series connection path are respectively connected to a connection point of the first and second transistors and a connection point of the third and fourth transistors. 3. The semiconductor integrated circuit according to claim 2, wherein a third transmission end portion of a signal that is connected and connects the second and third transistors is connected to the series connection path. 4. One end of each bias resistor is connected to a common power source, and one end of each of the first and second DC block capacitors is connected to a ground potential. Item 5. A semiconductor integrated circuit according to any one of items 1 to 3. 5. Field-effect type first, second, third, and fourth transistors each having a gate terminal connected to a resistor of kΩ or more and having source and drain terminals connected in series, and one end of the series connection. One end of the current path of the first transistor, a connection point of the current paths of the first and second transistors, a connection point of the current paths of the second and third transistors, and One end is connected to a connection point between the current paths of the third and fourth transistors and one end of the current path of the fourth transistor, which is the other end of the series connection, and the other ends are commonly connected to a power source. First, second, third, for voltage level shifting connected to the source,
Between the fourth and fifth bias resistors, one end of the current path of the first transistor, which is one end of the series connection, and the ground potential, and the fourth transistor, which is the other end of the series connection, of the fourth transistor. First and second DC blocking capacitors respectively provided between one end of the current path and the ground potential, a gate terminal provided with the resistance of the first transistor and a resistance of the third transistor are provided. A first signal control terminal connected to the gate terminal of the second transistor, a gate terminal provided with the resistance of the second transistor, and a gate terminal provided with the resistance of the fourth transistor. 2. A semiconductor integrated circuit comprising: two signal control terminals. 6. A supply end of a signal for conducting a signal through the series connection path is connected to each of a connection point of the first and second transistors and a connection point of the third and fourth transistors, and the second 3. The semiconductor integrated circuit according to claim 2, wherein an output end of the signal is connected to a connection point between the third transistor and the third transistor. 7. The semiconductor integrated circuit according to claim 3, wherein each of the bias resistors has an impedance sufficiently higher in terms of RF than an impedance of the output end of the signal. 8. The second and third transistors have the same DC and AC electrical characteristics, and the first and fourth transistors have the same characteristics.
8. The semiconductor integrated circuit according to claim 1, wherein the transistors have equal electrical characteristics in terms of direct current and alternating current. 9. The saturation current amount of each of the second and third transistors is larger than the saturation current amount of each of the first and fourth transistors.
The semiconductor integrated circuit described.