JP3284015B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which handles frequencies higher than the UHF band, and more particularly to an SPDT (single pole double throud) for switching and outputting two signals.
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[0002]

2. Description of the Related Art SPDs built in portable telephones and the like and functioning as switches for switching high-frequency transmission / reception signals include
There is a T switch circuit. FIG. 2 is a circuit diagram showing a configuration of a conventional SPDT switch. The current paths of the source and drain of each of the GaAs field effect transistors (FETs) 11, 12, 13, 14 are connected in series. Both ends of the series connection are grounded. These FETs 11, 12, 13, and 14 have resistors 21, 22, 23, and 24 of 10 kΩ or more connected to their gate terminals, respectively. The gate terminal of the FET 11 on which the resistor 21 is provided and F
The gate terminal provided with the resistor 23 of the ET 13 is commonly connected to the signal control terminal 15. The gate terminal provided with the resistor 22 of the FET 12 and the gate terminal provided with the resistor 24 of the FET 14 are commonly connected to the signal control terminal 16. F
The node N1 at the connection point between the ETs 11 and 12 and the node N2 at the connection point between the FETs 13 and 14 are connected to signal input terminals 17 and 18, respectively. The node N3 at the connection point between the FETs 12 and 13 is connected to the signal output terminal 19. Reference numerals 25 to 27 denote capacitive loads of circuits to which each terminal is connected.

[0003] The SPDT switch circuit having the above-described structure is composed of an FET.
The switches 11, 12, 13, and 14 are used as switches to select one of the two signals input to the terminals 17 and 18. That is, the FE is controlled by complementary signals to the signal control terminals 15 and 16.
Terminals 17 and 18 are controlled by commonly controlling ON / OFF of T11 and T13 and OFF / ON of FETs 12 and 14 in common.
One of the two signals is selected and output to the terminal 19.

[0004] FET in the above SPDT switch circuit
Reference numerals 11, 12, 13, and 14 denote GaAs field-effect transistors, which generally have a MESF having a Schottky junction at present.
ET and depletion type.

Accordingly, the depletion-type FETs 11, 1
When the switches 2, 13, and 14 are used as switches, the signals to the signal control terminals 15, 16 are both positive voltage (for example, 0 V) and negative voltage (for example, -3 V) for turning on / off the FET.
Need to be controlled by For this reason, when used in combination with other general semiconductor integrated circuits having a positive power supply specification, two types of power supplies are required.

[0006]

As described above, conventionally, a positive voltage and a negative voltage are used as gate control signals of a GaAs field effect transistor constituting an SPDT switch. As a result, when used together with a semiconductor integrated circuit or the like having a positive power supply specification, two types of power supplies are required, which hinders the integration of the entire circuit and increases the manufacturing cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a configuration in which an SPDT switch can be used with a positive power supply, thereby achieving integration of an entire circuit,
An object of the present invention is to provide a semiconductor integrated circuit which contributes to reduction in manufacturing cost.

[0008]

The semiconductor integrated circuit SUMMARY OF THE INVENTION The present invention has a source connected a resistor to the gate terminal, respectively, the first field effect type drain terminal are connected in series, the second, third, fourth And the source / drain terminal of each transistor so that the voltage of the source / drain terminal of each transistor is level-shifted in the positive direction.
End connected, first the other end connected to the positive power supply source, second, third, fourth, and bias resistor of the fifth, the first
1 for blocking a DC component of a signal conducting path of the series connection of a fourth transistor, said series connected first
1 to the first respectively provided at both ends of the fourth transistor, has and a second DC blocking capacitor
You.

[0009]

According to the present invention, the field effect type first, second, third, and fourth transistors constituting the switch can be controlled by a positive power supply by the bias resistor.
The potential is DC up-shifted by the blocking capacitor.

[0010]

FIG. 1 shows an SP according to a semiconductor integrated circuit of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a DT (single pole double through) switch circuit. The current paths of the source and drain of each of the GaAs field effect transistors (FETs) 11, 12, 13, 14 are connected in series. These FETs 11, 12, 13,
Reference numeral 14 denotes resistors 21 and 22, each having a resistance of 10 kΩ or more,
23 and 24 are provided. Each of the resistors 21 to 24 is constituted by a resistance element such as a diffusion resistor or a polysilicon resistor formed near the gate terminal.

One end of the current path of the FET 11, which is one end of the series connection of the FETs 11, 12, 13, 14;
12 and the current path connection point of FETs 12 and 13, and the current path connection point of FETs 13 and 14,
One end of the current path of the FET 14 which is the other end of the series connection is connected to each of the bias resistors R1, R2, R3,
One end of each of R4 and R5 is connected. The other ends of the bias resistors R1 to R5 are commonly connected to a power source for supplying a power voltage VC.

Further, one end of the current path of the FET 11, which is one end of the series connection of the FETs 11, 12, 13, 14 and one end of the current path of the FET 14, which is the other end of the series connection, is connected to the ground potential. And DC blocking capacitors C1 and C2, respectively. The gate terminal of the FET 11 where the resistor 21 is provided and the gate terminal of the FET 13 where the resistor 23 is provided are commonly connected to the signal control terminal 15.
The gate terminal of the FET 12 on which the resistor 22 is provided is connected to the FE.
The gate terminal provided with the resistor 24 of T14 is commonly connected to the signal control terminal 16.

The nodes N1 and FE at the connection point of the FETs 11 and 12
Nodes N2 at the connection points of T13 and T14 are signal input terminals, respectively.
17 and 18 are connected. The node N3 at the connection point between the FETs 12 and 13 is connected to the signal output terminal 19. twenty five~
27 indicates the capacitive load of the circuit to which each terminal is connected.

According to the above configuration, the bias resistors R1 to R5 whose one end is biased to the positive power supply are provided.
FETs 11 and 14 that constitute the switch are ON in the positive power supply area
/ OFF. Further, the DC block capacitors C1 and C2 cause the potential to be DC upshifted without damaging the RF-like (AC-like) signal.

For example, suppose that an RF signal of about 22 dB in the 1.9 GHz band is input to the terminal 17 or 18. Then, the resistances 21, 22, 23, 24 become the resistances Rj1, Rj.
2, Rj3 and Rj4 each need to be about 10 kΩ, and DC blocking capacitors C1 and C2 need to be 10 pF or more. Each of the bias resistors R1 to R5 has an output terminal 19 for reducing current consumption.
If the preceding impedance is 50Ω, it is necessary to have a sufficiently large impedance in terms of RF with respect to this, and it is preferably about 10 kΩ for each. Under these conditions,
The operation level of the FETs 11 to 14 is up-shifted by setting the power source to VC = 3 V, and the operation is possible with the positive voltage. Each of the used FETs 11 to 14 has a pinch-off voltage Vp =
-1.7 to -1.5V. Under this condition, more preferably, in order to obtain a more accurate output at the terminal 19, the signal is transferred to the output with respect to the saturation current Idss (11,14) of the FETs 11 and 14 which plays a role of extracting the residual signal. Currents Idss (1
The size of each FET may be set so that the ratio of (2,13) is 1: 2.

The node N1 at the connection point between the FETs 11 and 12 and the node N2 at the connection point between the FETs 13 and 14 are signal input terminals 17, 18 and the node N at the connection point between the FETs 12 and 13, respectively.
Although 3 is connected to the signal output terminal 19, the terminal 19 may be an input terminal and the terminals 17 and 18 may be output terminals depending on the application.

[0017]

As described above, according to the present invention,
Since the bias voltage is provided and the operating voltage is up-shifted in a DC manner by the DC blocking capacitor, an SPDT switch circuit can be configured in which the operation of a normal depletion type field effect transistor can be controlled by a positive power supply. . As a result, when the SPDT switch circuit is incorporated in a configuration with a positive power supply specification, a circuit for generating a negative power supply becomes unnecessary, and a semiconductor integrated circuit that greatly contributes to integration and cost reduction can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an SPDT switch circuit according to a semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional SPDT switch circuit.

[Explanation of symbols]

11, 12, 13, 14 ... GaAs field effect transistors, 15,
16: Signal control terminal, 17, 18: Signal input terminal, 19: Signal output terminal, 21, 22, 23, 24: Resistance, 25 to 27: Capacitive load, R
1, R2, R3, R4, R5 ... bias resistors, C1, C
2 ... DC block capacitor, VC ... power supply voltage.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-311007 (JP, A) JP-A-6-104718 (JP, A) JP-A-8-213891 (JP, A) JP-A-8-181 213553 (JP, A) JP-A-6-334506 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/00-17/70 H04B 1/38-1/58 H01P 1/10-1/195

Claims (9)

(57) [Claims] 1. A first source connecting each resistor to the gate terminal, the drain terminal of the series-connected field effect,
Second, third, and fourth transistors, and each of the transistors so that the voltage of the source / drain terminal of each of the transistors is level-shifted in the positive direction .
One end is connected to the source / drain terminal, and the other end is
A first, a second, a third, a fourth, and a fifth bias resistor connected to a source, and a DC component of a signal transmitted through a series connection path of the first to fourth transistors . Connected in series
A semiconductor integrated circuit comprising: first and second DC blocking capacitors provided at both ends of the first to fourth transistors , respectively. 2. A common first control signal is supplied to a gate terminal provided with a resistance of the first transistor and a gate terminal provided with a resistance of the third transistor, and the second transistor is provided. The common second control signal is supplied to the gate terminal provided with the resistor of the fourth transistor and the gate terminal provided with the resistor of the fourth transistor, and the conduction of each transistor is controlled. 1
A semiconductor integrated circuit as described in the above. 3. A connection point between the first and second transistors and a connection point between the third and fourth transistors respectively have first and second transmission ends of signals transmitted through the series connection path. 3. The semiconductor integrated circuit according to claim 2, wherein a third transmission end of a signal transmitted through the series connection path is connected to a connection point of the second and third transistors. 4. Before Symbol first semiconductor integrated circuit according to any one of claims 1 to 3 each end of the second DC block capacitor is characterized in that it is connected to the ground potential. Wherein each connecting a resistor to the gate terminal source, a first field effect type drain terminal are connected in series,
Second, third, and fourth transistors, one end of the current path of the first transistor, which is one end of the series connection, and a connection point between the current paths of the first and second transistors; The connection point of the current path of the second and third transistors, the connection point of the current path of the third and fourth transistors, and the current of the fourth transistor which is the other end of the series connection One end is connected to each one end of the passage, and the other end is connected in series to a first, second, third, fourth, or fifth bias resistor commonly connected to a positive power source . The first to fourth transistors connected in series between one end of a current path of the first transistor which is one end of the first to fourth transistors and a ground potential.
First respectively provided between one end and the ground potential of the current path of said fourth transistor is the other end portion of Njisuta, a second DC blocking capacitor, resistor provided in said first transistor A first signal control terminal connected to the gate terminal provided with the resistance of the third transistor and a gate terminal provided with the resistance of the second transistor; A semiconductor integrated circuit, comprising: a second signal control terminal connected to a gate terminal provided with a resistor. 6. A connection point between the first and second transistors and a connection point between the third and fourth transistors are connected to supply ends of signals transmitted through the series connection path, respectively. 3. The semiconductor integrated circuit according to claim 2, wherein an output end of the signal is connected to a connection point between the first transistor and a third transistor. 7. The semiconductor integrated circuit according to claim 3, wherein each of the bias resistors has an impedance that is sufficiently larger in terms of RF than an impedance attached to an output end of the signal. 8. The second and third transistors have the same DC and AC electrical characteristics, and the first and fourth transistors have the same electrical characteristics.
Transistors mutually galvanically, AC to semiconductor integrated circuit to any one of claims 1 to 7 serial <br/> mounting, characterized in that equal electrical properties of. 9. The device according to claim 8, wherein the saturation current amount of each of the second and third transistors is larger than the saturation current amount of each of the first and fourth transistors.
A semiconductor integrated circuit as described in the above.