JP3284015B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP3284015B2 JP3284015B2 JP01588595A JP1588595A JP3284015B2 JP 3284015 B2 JP3284015 B2 JP 3284015B2 JP 01588595 A JP01588595 A JP 01588595A JP 1588595 A JP1588595 A JP 1588595A JP 3284015 B2 JP3284015 B2 JP 3284015B2
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- transistor
- semiconductor integrated
- integrated circuit
- connection point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【0001】[0001]
【産業上の利用分野】本発明はUHF帯以上の周波数を
取り扱う半導体集積回路に係り、特に2つの信号をスイ
ッチング出力するSPDT(single pole double throu
gh)を構成する半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which handles frequencies higher than the UHF band, and more particularly to an SPDT (single pole double throud) for switching and outputting two signals.
gh).
【0002】[0002]
【従来の技術】携帯電話等に内蔵され、高周波の送受信
信号の切り替えスイッチとして機能するものに、SPD
Tスイッチ回路がある。図2は従来のSPDTスイッチ
の構成を示す回路図である。各GaAs電界効果トラン
ジスタ(FET)11,12,13,14のソース・ドレインの
電流通路は直列接続されている。直列接続の両端は接地
されている。これらFET11,12,13,14はそれぞれゲ
ート端子に10kΩ以上の抵抗21,22,23,24を接続し
ている。FET11の抵抗21が設けられたゲート端子とF
ET13の抵抗23が設けられたゲート端子とが共通に信号
制御端子15に接続されている。FET12の抵抗22が設け
られたゲート端子とFET14の抵抗24が設けられたゲー
ト端子とが共通に信号制御端子16に接続されている。F
ET11と12の接続点のノードN1 、FET13と14の接続
点のノードN2 はそれぞれ信号入力端子17,18に接続さ
れている。FET12と13の接続点のノードN3 は信号出
力端子19に接続されている。25〜27は各端子の接続先の
回路の容量負荷を示している。2. Description of the Related Art SPDs built in portable telephones and the like and functioning as switches for switching high-frequency transmission / reception signals include
There is a T switch circuit. FIG. 2 is a circuit diagram showing a configuration of a conventional SPDT switch. The current paths of the source and drain of each of the GaAs field effect transistors (FETs) 11, 12, 13, 14 are connected in series. Both ends of the series connection are grounded. These FETs 11, 12, 13, and 14 have resistors 21, 22, 23, and 24 of 10 kΩ or more connected to their gate terminals, respectively. The gate terminal of the FET 11 on which the resistor 21 is provided and F
The gate terminal provided with the resistor 23 of the ET 13 is commonly connected to the signal control terminal 15. The gate terminal provided with the resistor 22 of the FET 12 and the gate terminal provided with the resistor 24 of the FET 14 are commonly connected to the signal control terminal 16. F
The node N1 at the connection point between the ETs 11 and 12 and the node N2 at the connection point between the FETs 13 and 14 are connected to signal input terminals 17 and 18, respectively. The node N3 at the connection point between the FETs 12 and 13 is connected to the signal output terminal 19. Reference numerals 25 to 27 denote capacitive loads of circuits to which each terminal is connected.
【0003】上記構成のSPDTスイッチ回路はFET
11,12,13,14をスイッチとして、端子17及び18に入力
される二信号をいずれか一つ選択するものである。すな
わち、信号制御端子15,16への相補な信号により、FE
T11,13を共通にON/OFF、FET12,14を共通に
OFF/ON切り替え制御することにより、端子17、18
の二信号のうちの一つを選択し端子19に出力する。[0003] The SPDT switch circuit having the above-described structure is composed of an FET.
The switches 11, 12, 13, and 14 are used as switches to select one of the two signals input to the terminals 17 and 18. That is, the FE is controlled by complementary signals to the signal control terminals 15 and 16.
Terminals 17 and 18 are controlled by commonly controlling ON / OFF of T11 and T13 and OFF / ON of FETs 12 and 14 in common.
One of the two signals is selected and output to the terminal 19.
【0004】上記SPDTスイッチ回路におけるFET
11,12,13,14はGaAs電界効果トランジスタであ
り、一般に現状ではショットキー接合を有するMESF
ETであると共にデプレッション型である。[0004] FET in the above SPDT switch circuit
Reference numerals 11, 12, 13, and 14 denote GaAs field-effect transistors, which generally have a MESF having a Schottky junction at present.
ET and depletion type.
【0005】従って、デプレッション型のFET11,1
2,13,14をスイッチとして使用する場合、信号制御端
子15,16への信号は共に、FETをON/OFFさせる
ために正電圧(例えば0V)と負電圧(例えば−3V)
で制御する必要がある。このため、他の一般的な正電源
仕様を持つ半導体集積回路等と併用する場合、2種類の
電源が必要になる。Accordingly, the depletion-type FETs 11, 1
When the switches 2, 13, and 14 are used as switches, the signals to the signal control terminals 15, 16 are both positive voltage (for example, 0 V) and negative voltage (for example, -3 V) for turning on / off the FET.
Need to be controlled by For this reason, when used in combination with other general semiconductor integrated circuits having a positive power supply specification, two types of power supplies are required.
【0006】[0006]
【発明が解決しようとする課題】このように、従来では
SPDTスイッチを構成するGaAs電界効果トランジ
スタのゲート制御信号として、正電圧と負電圧を用いて
いる。この結果、正電源仕様を持つ半導体集積回路等と
併用する場合、2種類の電源が必要になり、全体回路の
集積化を妨げると共に製造コスト増大につながるという
問題がある。As described above, conventionally, a positive voltage and a negative voltage are used as gate control signals of a GaAs field effect transistor constituting an SPDT switch. As a result, when used together with a semiconductor integrated circuit or the like having a positive power supply specification, two types of power supplies are required, which hinders the integration of the entire circuit and increases the manufacturing cost.
【0007】この発明は上記のような事情を考慮してな
されたものであり、その目的は、SPDTスイッチを正
電源で使用できる構成とし、もって全体回路の集積化、
製造コストの低減に寄与する半導体集積回路を半導体集
積回路を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a configuration in which an SPDT switch can be used with a positive power supply, thereby achieving integration of an entire circuit,
An object of the present invention is to provide a semiconductor integrated circuit which contributes to reduction in manufacturing cost.
【0008】[0008]
【課題を解決するための手段】この発明の半導体集積回
路は、それぞれゲート端子に抵抗を接続しソース、ドレ
イン端子が直列接続された電界効果型の第1、第2、第
3、第4のトランジスタと、前記各トランジスタのソー
ス・ドレイン端子の電圧が正方向にレベルシフトされる
よう、前記各トランジスタのソース・ドレイン端子に一
端が接続され、他端が正の電源ソースに接続された第
1、第2、第3、第4、第5のバイアス抵抗と、前記第
1乃至第4のトランジスタの直列接続の経路を伝導する
信号の直流成分を遮断するため、直列接続された前記第
1乃至第4のトランジスタの両端にそれぞれ設けられた
第1、第2のDCブロック用キャパシタとを具備してい
る。 The semiconductor integrated circuit SUMMARY OF THE INVENTION The present invention has a source connected a resistor to the gate terminal, respectively, the first field effect type drain terminal are connected in series, the second, third, fourth And the source / drain terminal of each transistor so that the voltage of the source / drain terminal of each transistor is level-shifted in the positive direction.
End connected, first the other end connected to the positive power supply source, second, third, fourth, and bias resistor of the fifth, the first
1 for blocking a DC component of a signal conducting path of the series connection of a fourth transistor, said series connected first
1 to the first respectively provided at both ends of the fourth transistor, has and a second DC blocking capacitor
You.
【0009】[0009]
【作用】この発明ではバイアス抵抗により、スイッチを
構成する電界効果型の第1、第2、第3、第4のトラン
ジスタが正電源での動作制御が可能となり、さらにDC
ブロック用キャパシタによりDC的に電位をアップシフ
トさせる。According to the present invention, the field effect type first, second, third, and fourth transistors constituting the switch can be controlled by a positive power supply by the bias resistor.
The potential is DC up-shifted by the blocking capacitor.
【0010】[0010]
【実施例】図1はこの発明の半導体集積回路に係るSP
DT(single pole double through)スイッチ回路の構
成を示す回路図である。各GaAs電界効果トランジス
タ(FET)11,12,13,14のソース・ドレインの電流
通路は直列接続されている。これらFET11,12,13,
14はそれぞれゲート端子に10kΩ以上の抵抗21,22,
23,24を設けている。これら抵抗21〜24はいずれもゲー
ト端子近傍に形成される拡散抵抗やポリシリコン抵抗等
の抵抗素子により構成される。FIG. 1 shows an SP according to a semiconductor integrated circuit of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a DT (single pole double through) switch circuit. The current paths of the source and drain of each of the GaAs field effect transistors (FETs) 11, 12, 13, 14 are connected in series. These FETs 11, 12, 13,
Reference numeral 14 denotes resistors 21 and 22, each having a resistance of 10 kΩ or more,
23 and 24 are provided. Each of the resistors 21 to 24 is constituted by a resistance element such as a diffusion resistor or a polysilicon resistor formed near the gate terminal.
【0011】上記FET11,12,13,14の直列接続の一
端部であるFET11の電流通路の一端、及び、FET11
と12の電流通路の接続点、及び、FET12と13の電流通
路の接続点、及び、FET13と14の電流通路の接続点、
及び、この直列接続の他端部であるFET14の電流通路
の一端に、それぞれにバイアス抵抗R1 ,R2 ,R3,
R4 ,R5 の各一端が接続されている。、これらバイア
ス抵抗R1 〜R5 の各他端は共通に電源電圧VCを供給
する電源ソースに接続されている。One end of the current path of the FET 11, which is one end of the series connection of the FETs 11, 12, 13, 14;
12 and the current path connection point of FETs 12 and 13, and the current path connection point of FETs 13 and 14,
One end of the current path of the FET 14 which is the other end of the series connection is connected to each of the bias resistors R1, R2, R3,
One end of each of R4 and R5 is connected. The other ends of the bias resistors R1 to R5 are commonly connected to a power source for supplying a power voltage VC.
【0012】また、FET11,12,13,14の直列接続の
一端部であるFET11の電流通路の一端と接地電位との
間、直列接続の他端部であるFET14の電流通路の一端
と接地電位との間にそれぞれDCブロック用キャパシタ
C1 ,C2 が設けられている。 FET11の抵抗21が設
けられたゲート端子とFET13の抵抗23が設けられたゲ
ート端子とが共通に信号制御端子15に接続されている。
また、FET12の抵抗22が設けられたゲート端子とFE
T14の抵抗24が設けられたゲート端子とが共通に信号制
御端子16に接続されている。Further, one end of the current path of the FET 11, which is one end of the series connection of the FETs 11, 12, 13, 14 and one end of the current path of the FET 14, which is the other end of the series connection, is connected to the ground potential. And DC blocking capacitors C1 and C2, respectively. The gate terminal of the FET 11 where the resistor 21 is provided and the gate terminal of the FET 13 where the resistor 23 is provided are commonly connected to the signal control terminal 15.
The gate terminal of the FET 12 on which the resistor 22 is provided is connected to the FE.
The gate terminal provided with the resistor 24 of T14 is commonly connected to the signal control terminal 16.
【0013】FET11と12の接続点のノードN1 、FE
T13と14の接続点のノードN2 はそれぞれ信号入力端子
17,18に接続されている。また、FET12と13の接続点
のノードN3 は信号出力端子19に接続されている。25〜
27は各端子の接続先の回路の容量負荷を示している。The nodes N1 and FE at the connection point of the FETs 11 and 12
Nodes N2 at the connection points of T13 and T14 are signal input terminals, respectively.
17 and 18 are connected. The node N3 at the connection point between the FETs 12 and 13 is connected to the signal output terminal 19. twenty five~
27 indicates the capacitive load of the circuit to which each terminal is connected.
【0014】上記構成によれば、一端が正電源にバイア
スされるバイアス抵抗R1 〜R5 を設けたことにより、
スイッチを構成するFET11〜14が正電源の領域でON
/OFFできるようになる。さらに、DCブロック用キ
ャパシタC1 ,C2 により、RF的(交流的)な信号を
損なわせることなく、DC的に電位をアップシフトさせ
る。According to the above configuration, the bias resistors R1 to R5 whose one end is biased to the positive power supply are provided.
FETs 11 and 14 that constitute the switch are ON in the positive power supply area
/ OFF. Further, the DC block capacitors C1 and C2 cause the potential to be DC upshifted without damaging the RF-like (AC-like) signal.
【0015】例えば、1.9GHz帯で、22dB程度
のRF信号が端子17もしくは18に入力されると想定す
る。すると、抵抗21,22,23,24はその抵抗Rj1,Rj
2,Rj3,Rj4を各々10kΩ程度、DCブロック用キ
ャパシタC1 ,C2 は10pF以上必要である。各バイ
アス抵抗R1 〜R5 は消費電流削減のため、出力端子19
先に付くインピーダンスが50Ωとすれば、これに対し
てRF的に十分大きいインピーダンスを有する必要があ
り、各々10kΩ程度が好ましい。このような条件で、
電源ソースをVC=3VとしてFET11〜14の動作レベ
ルをアップシフトさせ、正電圧で動作可能とする。使用
されるFET11〜14それぞれは、ピンチオフ電圧Vp=
−1.7〜−1.5Vとした。この条件でさらに好まし
くは、より正確な出力を端子19に得るために、残留的な
信号を引き抜く役割を果たすFET11,14の飽和電流量
Idss (11,14 )に対して、信号を出力にトランスファ
する役割を果たすFET12,13の飽和電流量Idss (1
2,13 )の比を1:2にするよう、各FETのサイズ設
定を行ってもよい。For example, suppose that an RF signal of about 22 dB in the 1.9 GHz band is input to the terminal 17 or 18. Then, the resistances 21, 22, 23, 24 become the resistances Rj1, Rj.
2, Rj3 and Rj4 each need to be about 10 kΩ, and DC blocking capacitors C1 and C2 need to be 10 pF or more. Each of the bias resistors R1 to R5 has an output terminal 19 for reducing current consumption.
If the preceding impedance is 50Ω, it is necessary to have a sufficiently large impedance in terms of RF with respect to this, and it is preferably about 10 kΩ for each. Under these conditions,
The operation level of the FETs 11 to 14 is up-shifted by setting the power source to VC = 3 V, and the operation is possible with the positive voltage. Each of the used FETs 11 to 14 has a pinch-off voltage Vp =
-1.7 to -1.5V. Under this condition, more preferably, in order to obtain a more accurate output at the terminal 19, the signal is transferred to the output with respect to the saturation current Idss (11,14) of the FETs 11 and 14 which plays a role of extracting the residual signal. Currents Idss (1
The size of each FET may be set so that the ratio of (2,13) is 1: 2.
【0016】なお、図中のFET11と12の接続点のノー
ドN1 、FET13と14の接続点のノードN2 はそれぞれ
信号入力端子17,18、FET12と13の接続点のノードN
3 は信号出力端子19に接続されているとしたが、用途に
よって、端子19が入力端子で、端子17,18が、出力端子
側であってもよい。The node N1 at the connection point between the FETs 11 and 12 and the node N2 at the connection point between the FETs 13 and 14 are signal input terminals 17, 18 and the node N at the connection point between the FETs 12 and 13, respectively.
Although 3 is connected to the signal output terminal 19, the terminal 19 may be an input terminal and the terminals 17 and 18 may be output terminals depending on the application.
【0017】[0017]
【発明の効果】以上説明したようにこの発明によれば、
バイアス抵抗を設け、かつDCブロック用キャパシタに
よりDC的に動作電圧をアップシフトするので、通常デ
プレッション型の電界効果型のトランジスタも正電源で
動作制御できるようになるSPDTスイッチ回路を構成
することができる。これにより、このSPDTスイッチ
回路を正電源仕様の構成に組み込む場合、負電源を発生
させる回路等が不要となり、集積化及びコスト削減に大
いに寄与する半導体集積回路が提供できる。As described above, according to the present invention,
Since the bias voltage is provided and the operating voltage is up-shifted in a DC manner by the DC blocking capacitor, an SPDT switch circuit can be configured in which the operation of a normal depletion type field effect transistor can be controlled by a positive power supply. . As a result, when the SPDT switch circuit is incorporated in a configuration with a positive power supply specification, a circuit for generating a negative power supply becomes unnecessary, and a semiconductor integrated circuit that greatly contributes to integration and cost reduction can be provided.
【図1】この発明の半導体集積回路に係るSPDTスイ
ッチ回路の構成を示す回路図。FIG. 1 is a circuit diagram showing a configuration of an SPDT switch circuit according to a semiconductor integrated circuit of the present invention.
【図2】従来のSPDTスイッチ回路の構成を示す回路
図。FIG. 2 is a circuit diagram showing a configuration of a conventional SPDT switch circuit.
11,12,13,14…GaAs電界効果トランジスタ、15,
16…信号制御端子、17,18…信号入力端子、19…信号出
力端子、21,22,23,24…抵抗、25〜27…容量負荷、R
1 ,R2 ,R3 ,R4 ,R5 …バイアス抵抗、C1 ,C
2 …DCブロック用キャパシタ、VC…電源電圧。11, 12, 13, 14 ... GaAs field effect transistors, 15,
16: Signal control terminal, 17, 18: Signal input terminal, 19: Signal output terminal, 21, 22, 23, 24: Resistance, 25 to 27: Capacitive load, R
1, R2, R3, R4, R5 ... bias resistors, C1, C
2 ... DC block capacitor, VC ... power supply voltage.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平6−311007(JP,A) 特開 平6−104718(JP,A) 特開 平8−213891(JP,A) 特開 平8−213553(JP,A) 特開 平6−334506(JP,A) (58)調査した分野(Int.Cl.7,DB名) H03K 17/00 - 17/70 H04B 1/38 - 1/58 H01P 1/10 - 1/195 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-311007 (JP, A) JP-A-6-104718 (JP, A) JP-A-8-213891 (JP, A) JP-A-8-181 213553 (JP, A) JP-A-6-334506 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H03K 17/00-17/70 H04B 1/38-1/58 H01P 1/10-1/195
Claims (9)
ス、ドレイン端子が直列接続された電界効果型の第1、
第2、第3、第4のトランジスタと、 前記各トランジスタのソース・ドレイン端子の電圧が正
方向にレベルシフトされるよう、前記各トランジスタの
ソース・ドレイン端子に一端が接続され、他端が正の電
源ソースに接続された第1、第2、第3、第4、第5の
バイアス抵抗と、 前記第1乃至第4のトランジスタの直列接続の経路を伝
導する信号の直流成分を遮断するため、直列接続された
前記第1乃至第4のトランジスタの両端にそれぞれ設け
られた第1、第2のDCブロック用キャパシタとを具備
したことを特徴とする半導体集積回路。1. A first source connecting each resistor to the gate terminal, the drain terminal of the series-connected field effect,
Second, third, and fourth transistors, and each of the transistors so that the voltage of the source / drain terminal of each of the transistors is level-shifted in the positive direction .
One end is connected to the source / drain terminal, and the other end is
A first, a second, a third, a fourth, and a fifth bias resistor connected to a source, and a DC component of a signal transmitted through a series connection path of the first to fourth transistors . Connected in series
A semiconductor integrated circuit comprising: first and second DC blocking capacitors provided at both ends of the first to fourth transistors , respectively.
れたゲート端子と前記第3のトランジスタの抵抗が設け
られたゲート端子とは共通の第1の制御信号が供給さ
れ、前記第2のトランジスタの抵抗が設けられたゲート
端子と前記第4のトランジスタの抵抗が設けられたゲー
ト端子とは共通の第2の制御信号が供給され、各々のト
ランジスタが導通制御されることを特徴とする請求項1
記載の半導体集積回路。2. A common first control signal is supplied to a gate terminal provided with a resistance of the first transistor and a gate terminal provided with a resistance of the third transistor, and the second transistor is provided. The common second control signal is supplied to the gate terminal provided with the resistor of the fourth transistor and the gate terminal provided with the resistor of the fourth transistor, and the conduction of each transistor is controlled. 1
A semiconductor integrated circuit as described in the above.
点、前記第3と第4のトランジスタの接続点それぞれに
前記直列接続の経路を伝導する信号の第1、第2の伝達
端部が接続され、前記第2と第3のトランジスタの接続
点には前記直列接続の経路を伝導する信号の第3の伝達
端部が接続されることを特徴とする請求項2記載の半導
体集積回路。3. A connection point between the first and second transistors and a connection point between the third and fourth transistors respectively have first and second transmission ends of signals transmitted through the series connection path. 3. The semiconductor integrated circuit according to claim 2, wherein a third transmission end of a signal transmitted through the series connection path is connected to a connection point of the second and third transistors.
シタの各一端は接地電位に接続されることを特徴とする
請求項1乃至3のいずれかに記載の半導体集積回路。4. Before Symbol first semiconductor integrated circuit according to any one of claims 1 to 3 each end of the second DC block capacitor is characterized in that it is connected to the ground potential.
ス、ドレイン端子が直列接続された電界効果型の第1、
第2、第3、第4のトランジスタと、 前記直列接続の一端部である前記第1のトランジスタの
電流通路の一端、及び、前記第1と第2のトランジスタ
の電流通路の接続点、及び、前記第2と第3のトランジ
スタの電流通路の接続点、及び、前記第3と第4のトラ
ンジスタの電流通路の接続点、及び、前記直列接続の他
端部である前記第4のトランジスタの電流通路の一端そ
れぞれに各一端が接続され、各他端は共通に正の電源ソ
ースに接続された第1、第2、第3、第4、第5のバイ
アス抵抗と、 前記直列接続された第1乃至第4のトランジスタの一端
部である前記第1のトランジスタの電流通路の一端と接
地電位との間、前記直列接続された第1乃至第4のトラ
ンジスタの他端部である前記第4のトランジスタの電流
通路の一端と接地電位との間にそれぞれ設けられた第
1、第2のDCブロック用キャパシタと、 前記第1のトランジスタの抵抗が設けられたゲート端子
と前記第3のトランジスタの抵抗が設けられたゲート端
子とが接続される第1の信号制御端子と、前記第2のト
ランジスタの抵抗が設けられたゲート端子と前記第4の
トランジスタの抵抗が設けられたゲート端子とが接続さ
れる第2の信号制御端子とを具備したことを特徴とする
半導体集積回路。Wherein each connecting a resistor to the gate terminal source, a first field effect type drain terminal are connected in series,
Second, third, and fourth transistors, one end of the current path of the first transistor, which is one end of the series connection, and a connection point between the current paths of the first and second transistors; The connection point of the current path of the second and third transistors, the connection point of the current path of the third and fourth transistors, and the current of the fourth transistor which is the other end of the series connection One end is connected to each one end of the passage, and the other end is connected in series to a first, second, third, fourth, or fifth bias resistor commonly connected to a positive power source . The first to fourth transistors connected in series between one end of a current path of the first transistor which is one end of the first to fourth transistors and a ground potential.
First respectively provided between one end and the ground potential of the current path of said fourth transistor is the other end portion of Njisuta, a second DC blocking capacitor, resistor provided in said first transistor A first signal control terminal connected to the gate terminal provided with the resistance of the third transistor and a gate terminal provided with the resistance of the second transistor; A semiconductor integrated circuit, comprising: a second signal control terminal connected to a gate terminal provided with a resistor.
点、前記第3と第4のトランジスタの接続点それぞれに
前記直列接続の経路を伝導する信号の供給端部が接続さ
れ、前記第2と第3のトランジスタの接続点には前記信
号の出力端部が接続されることを特徴とする請求項2記
載の半導体集積回路。6. A connection point between the first and second transistors and a connection point between the third and fourth transistors are connected to supply ends of signals transmitted through the series connection path, respectively. 3. The semiconductor integrated circuit according to claim 2, wherein an output end of the signal is connected to a connection point between the first transistor and a third transistor.
部先に付くインピーダンスに対してRF的に十分大きい
インピーダンスを有することを特徴とする請求項3また
は6記載の半導体集積回路。7. The semiconductor integrated circuit according to claim 3, wherein each of the bias resistors has an impedance that is sufficiently larger in terms of RF than an impedance attached to an output end of the signal.
直流的、交流的に電気的特性が等しく、前記第1、第4
のトランジスタが互いに直流的、交流的に電気的特性が
等しいことを特徴とする請求項1乃至7のいずれかに記
載の半導体集積回路。8. The second and third transistors have the same DC and AC electrical characteristics, and the first and fourth transistors have the same electrical characteristics.
Transistors mutually galvanically, AC to semiconductor integrated circuit to any one of claims 1 to 7 serial <br/> mounting, characterized in that equal electrical properties of.
の飽和電流量が前記第1、第4のトランジスタそれぞれ
の飽和電流量に対して大きいことを特徴とする請求項8
記載の半導体集積回路。9. The device according to claim 8, wherein the saturation current amount of each of the second and third transistors is larger than the saturation current amount of each of the first and fourth transistors.
A semiconductor integrated circuit as described in the above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01588595A JP3284015B2 (en) | 1995-02-02 | 1995-02-02 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01588595A JP3284015B2 (en) | 1995-02-02 | 1995-02-02 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08213893A JPH08213893A (en) | 1996-08-20 |
JP3284015B2 true JP3284015B2 (en) | 2002-05-20 |
Family
ID=11901256
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP01588595A Expired - Fee Related JP3284015B2 (en) | 1995-02-02 | 1995-02-02 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3284015B2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3702189B2 (en) * | 2001-02-27 | 2005-10-05 | 三洋電機株式会社 | Compound semiconductor switch circuit device |
US7250804B2 (en) * | 2002-12-17 | 2007-07-31 | M/A -Com, Inc. | Series/shunt switch and method of control |
CN100405739C (en) * | 2002-12-17 | 2008-07-23 | M/A-Com公司 | Series/shunt switch and method of operation |
JP3790227B2 (en) | 2003-04-16 | 2006-06-28 | 松下電器産業株式会社 | High frequency switch circuit |
JP2005006072A (en) | 2003-06-12 | 2005-01-06 | Matsushita Electric Ind Co Ltd | High frequency switch apparatus and semiconductor device |
JP4029169B2 (en) | 2003-07-07 | 2008-01-09 | 株式会社村田製作所 | High frequency switch circuit |
JP4763310B2 (en) * | 2005-02-22 | 2011-08-31 | 新日本無線株式会社 | Semiconductor switch integrated circuit |
JP2007110469A (en) | 2005-10-14 | 2007-04-26 | Matsushita Electric Ind Co Ltd | High-frequency switching device |
-
1995
- 1995-02-02 JP JP01588595A patent/JP3284015B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH08213893A (en) | 1996-08-20 |
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