JPH0923101A - High frequency switching device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce transmission loss as less as possible. SOLUTION: This high frequency switching device, is provided with 1st to 3rd terminals 3, 4, 2, a 1st filter circuit consisting of a 1st FET 11 and a 1st inductor 21 connected to the FET 11 in parallel and connecting one end to the 1st terminal 3 and a 2nd filter circuit consisting of a 2nd FET 12 and a 2nd inductor 22 connected to the FET 12 in parallel, connecting one end to the other end of the 1st filter circuit and connecting the other end to the 2nd terminal 4. A 1st control signal is impressed to the gate of the 1st FET 11 through a resistor, a 2nd control signal is impressed to the gate of the 2nd FET 12 through a resistor, the 3rd terminal 2 is connected to a common node 8 between the 1st and 2nd filter circuits, and prescribed potential 15 impressed to the common node 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency switching device for switching a transmission path of high frequency signals, and is particularly used for switching an antenna of a digital cordless telephone to a transmitting or receiving state.

[0002]

2. Description of the Related Art The configuration of a conventional high frequency switching device is shown in FIG.
Shown in This conventional high frequency switching device has a typical single pole dual through (Single Pol) having three terminals.
e DualThrough) switch, which is used, for example, to switch the antenna of a digital cordless telephone to a transmitting or receiving state. In FIG. 7, an antenna terminal 2 is connected to a signal input / output terminal (hereinafter, also referred to as “transmission side terminal”) 3 of a power transmission path on the transmission side via a depletion type field effect transistor (hereinafter, referred to as FET) 11 and the depletion is performed. A signal input / output terminal (hereinafter, also referred to as a reception side terminal) 4 of a small signal transmission path is connected to the reception side via a type FET 12. The transmission side terminal 3 is grounded via the depletion type FET 13 and the reception side terminal 4 is grounded via the depletion type FET 14.

The gate signal input terminals 5 and 7 are connected to the FET 1 through the gate resistors 31 and 33 having a high resistance value (for example, several KΩ).
It is connected to the gates 1 and 12, respectively.

In the conventional high-frequency switch device shown in FIG. 7, in the transmission mode, when the gate signal input terminal 5 is supplied with 0V and the gate input terminal 7 is supplied with -3V, the FET 11 and the FET 14 are turned on. Both ON
Then, both the FET 12 and the FET 13 are turned off.
When a high frequency signal is input from the transmission side terminal 3 in this state, this high frequency signal is sent to the antenna terminal 2 via the FET 11. At this time, the signal input from the transmission-side terminal 3 includes the loss due to the ON resistance of the FET 11, the loss caused by the capacitance when the FET 13 is OFF, and the O of the FET 12.
The leak loss caused by the capacitance at the time of FF is subtracted and output from the antenna terminal 2. Since the leak current generated by the capacitance when the FET 12 is OFF flows to the GND through the FET 14 in the ON state, it hardly flows to the reception side terminal 4, and high isolation can be realized. Here, the isolation is expressed as 10 · log ₁₀ (P ₄ / P ₃ ), where P ₄ is the power of the signal obtained at the receiving side terminal 4 when the signal of power P ₃ is input to the transmitting side terminal 3. It

On the other hand, when the receiving mode is set, -3V is applied to the gate input terminal 5 and 0V is applied to the gate input terminal 7, contrary to the case of the transmitting mode. Then, FET1
FETs 2 and 13 turn on and FETs 11 and 14 turn off
However, the signal coming from the antenna signal terminal 2 is FET12.
Is sent to the receiving side terminal 4 via.

The high frequency switching device shown in FIG.
FIG. 8 shows the configuration of a conventional high-frequency switch device which operates with a negative power supply of 3V but operates with a positive power supply of 0V and + 3V. The high frequency switch device shown in FIG.
The pull-up resistors 37 and 38 of several KΩ and the DC blocking capacitors 40 and 4 of several pF in the switch device shown in FIG.
1, 42 and decoupling capacitor 45 of several pF
And are newly provided. The capacitor 40 is an FET
11 and 12 are provided between the common connection point 8 and the antenna terminal 2, a capacitor 41 is provided between the common connection point of the FETs 11 and 13 and the transmission side terminal 3, and a capacitor 42 is commonly connected between the FETs 12 and 14. It is provided between the point and the receiving side terminal 4. Then, in FIG. 7, F
The grounded terminals of the ETs 13 and 14 are commonly connected and grounded via the decoupling capacitor 45. The common connection point of the FETs 13 and 14 is connected to the pull-up power source terminal 6 via the pull-up resistor 38, and the power source terminal 6 is connected to the FE via the pull-up resistor 37.
It is connected to the common connection point 8 of T11 and T12.

With the above configuration, the FET1
Common connection point 8 of 1 and 12 and FETs 13 and 14
The common connection point of is pulled up by pull-up resistors 37 and 38. Here, if +3 V is applied to one of the gate input terminals 5 and 7 and zero V is applied to the other, the transmission mode or the reception mode is achieved as in the high frequency switch device shown in FIG.

[0008]

In the above-mentioned conventional high-frequency switch device, the transmission side terminal 3 is used in the transmission mode.
Since there is a loss of leakage current caused by the capacitance when the FET 12 is OFF and a loss caused by the capacitance of the FET 13 when the FET 12 is OFF, the signal that has arrived at the passage of power transmission from the transmission side terminal 3 to the antenna terminal 2 There was a problem that the loss (insertion loss) was large. Note that the insertion loss is 10 when the power of the signal that has entered the transmission-side terminal 3 is P ₃ and the power of the signal that is output from the antenna terminal 2 at this time is P _2.
It is represented by log (P ₃ / P ₂ ).

Further, in the high frequency switching device shown in FIG. 8, since it is necessary to provide the decoupling capacitor 45, an MMIC (Microwave Monolithic Integ) is provided.
There is a problem that the layout area increases when it is realized by a rated circuit). Further, since the circuit configuration on the MMIC is completely different between the positive power source and the negative power source, even if the negative power source driven high frequency switching device shown in FIG. 7 and the positive power source driven high frequency switching device shown in FIG. There is a problem in that the MMIC chip cannot be provided with versatility due to the use capacitor 45 and the like.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high-frequency switch device capable of reducing transmission loss as much as possible.

[0011]

A first aspect of a high-frequency switch device according to the present invention is the first to third terminals, and the first aspect.
First FET connected in parallel to the first FET and the first FET, one end of which is connected to the first terminal, and the second FET and the second F
A second inductor connected in parallel to ET, one end of which is connected to the other end of the first circuit, and the other end of which is connected to the second circuit.
A second circuit connected to the terminal of the first FET, the first control signal is applied to the gate of the first FET via a resistor, and the gate of the second FET is connected to the gate of the second FET via a resistor. Second
Control signal is applied, the third terminal is connected to a common connection point of the first and second circuits, and a predetermined potential is applied to the common connection point.

A second aspect of the high-frequency switch device according to the present invention is the high-frequency switch device according to the first aspect, wherein the first capacitor is provided between the first terminal and the first circuit, and A second capacitor provided between the second terminal and the second circuit, and a third capacitor provided between the third terminal and the common connection point. To do.

A third aspect of the high-frequency switch device according to the present invention is the high-frequency switch device according to the first or second aspect, wherein the gate width of the first FET is larger than the gate width of the second FET. In addition, the inductance of the first inductor is smaller than the inductance of the second inductor.

[0014]

In the first and second aspects of the high frequency switching device according to the present invention constructed as described above, the first F
The capacitance when the ET is off and the first inductor resonate at the desired frequency, and the capacitance when the second FET is off and the second inductor resonate at the desired frequency are set. The first FET is turned on by applying a potential signal complementary to the first control signal and the second control signal (a potential signal that causes the other to be at the “L” level if one is at the “H” level) and turns on the first FET. When the FET is turned off, the impedance of the second filter circuit becomes very large. As a result, when a signal is transmitted from the first terminal to the third terminal,
The current leaking through the second filter circuit is smaller than that in the conventional case, and the transmission loss can be minimized.

According to the third aspect configured as described above, since the gate width of the first FET is larger than the gate width of the second FET, the ON resistance of the first FET is the second resistance.
It is smaller than the ON resistance of the FET, and the insertion loss can be further reduced.

[0016]

1 shows the structure of a first embodiment of a high frequency switching device according to the present invention. The high frequency switching device of this embodiment is used as an antenna switch of a digital cordless telephone, and has a first filter circuit including a depletion type FET 11 and an inductor 21, a second filter circuit including a depletion type FET 12 and an inductor 22, and a resistor 31. , 32, 33. The first and second filter circuits are connected in series, and the antenna terminal 2 is connected to the common connection point 8. Further, the transmission side terminal 3 is connected to the other end of the first filter circuit, and the reception side terminal 4 is connected to the other end of the second filter circuit.

On the other hand, the gate signal input terminal 5 is connected to the gate of the FET 11 via the gate resistance 31 having a high resistance value (eg, several kΩ), and the gate of the FET 12 has a high resistance value (eg, several kΩ). The gate signal input terminal 7 is connected via 33. Further, the reference potential input terminal 6 is connected to the common connection point 8 via a resistor 32 having a high resistance value (for example, several kΩ).

The inductors 21 and 22 of the first and second filter circuits match the OFF-state capacitance of each FET so that the impedance becomes maximum at the frequency (for example, 1.9 GHz) used by the digital cordless telephone. It is set to the inductance value.

Next, the operation of the above embodiment will be described. In the transmission mode, 0V is applied to the gate signal input terminal 5, -3V is applied to the gate signal input terminal 7, and 0V is applied to the reference potential input terminal 6. Then, FET11 is turned on and FET12 is OF.
F In this state, if a signal comes in to the transmitter terminal 3,
Although this signal is transmitted to the antenna signal terminal 2 via the FET 11, loss due to the ON resistance of the FET 11 and OF
It suffers loss due to current leakage to the small signal transmission path on the F side. The current leak to the small signal transmission path on the OFF side is OF
Since the impedance Z of the small signal transmission path on the F side is determined by the ratio of the terminating resistance (for example, 50Ω) connected to the antenna terminal 2, the larger the impedance Z of the small signal transmission path on the OFF side, the more the terminal on the transmission side 3 to antenna terminal 2
It is possible to reduce the insertion loss to and to achieve high isolation. In the transmission mode, -3V is applied to the gate signal input terminal 5, and 0V is applied to the gate signal input terminal 7 and the reference potential input terminal 6. Then F
The ET 12 is turned on and the FET 11 is turned off. In this state, the signal coming from the antenna terminal 2 is transmitted to the reception side terminal 4 via the FET 12.

Next, the impedance Z of the above filter circuit when the filter circuit is OFF will be described with reference to FIG. Figure 2 shows FET
FIG. 3 is an equivalent circuit diagram of an OFF state of a filter circuit including an inductor connected in parallel to this FET. OFF
At this time, the capacitance C _off of the FET and the resistance R _off are connected in parallel, and the series circuit including the inductance component L and the resistance component R _{L of} the inductor is connected in parallel to the capacitance C _off . In the case of an ideal inductor without the resistance component R _L, the impedance Z _{p of} the portion where the inductance L and the capacitance C _off resonate in parallel becomes infinite, and the impedance Z of the small signal transmission path on the OFF side is equal to R _off . However, in reality, since the resistance component R _L exists in the inductor, the impedance Z _p has a finite value. In this case, the impedance Z _p of the portion where the inductance L and the capacitance C _off resonate in parallel is
Under the condition that ω · L / R _L is much larger than 1 and that the inductance L and the capacitance C _off resonate, Z _p = L / (R _L · C _off ), and OFF The impedance Z of the small signal transmission path on the side is Z = (1 / Z _p
It is expressed as + 1 / R _off ) ^-1 .

Next, the insertion loss and isolation of the high frequency switching device of the above embodiment will be described. now,
In the high frequency switching device of the embodiment shown in FIG.
T11 and 12 have a gate width W _g of 1 mm and a threshold voltage V
F with _th of −1.0 V and a unit gate width of 100 μm
It is a multi-finger type FET composed of ET, and the inductors 21 and 22 are spiral inductors each having an inductance L of 15.5 nH.
The resistance values R of 1, 32, and 33 were set to 10 KΩ. The spiral inductor has a line width of 10 μm and space 5
It was formed on the MMIC as a square spiral having a thickness of 3 μm, a thickness of 3 μm, and a side length of 340 μm.

FIG. 3 shows the measurement result of the insertion loss of the high-frequency switch device manufactured under the above conditions, and FIG. 4 shows the measurement result of the isolation. In FIG. 3, the measurement results of this example are shown by black circles, and the measurement results of the conventional case are shown by white circles.

The FETs 11 and 12 of the conventional high-frequency switch device (see FIG. 7) have a gate width W _g of 1 mm and a threshold voltage V _th of -1.0 V, and the FETs 13 and 14 have a gate width W _g. 200 μm, threshold voltage V _th is −1.
0V.

The insertion loss of the high frequency switching device of this embodiment is 1.0 dB at 1.0 GHz, 0.4 dB at a frequency of 1.9 GHz, and 0.8 dB at a frequency of 3.0 GHz.
It has a characteristic of taking a minimum value at a frequency of 1.9 GHz.
The characteristic that the loss is minimized in the narrow band of the frequency of 1.9 GHz is sufficiently satisfactory for use as an antenna switch of a digital cordless telephone.

On the other hand, the insertion loss of the conventional high frequency switching device was constant at 0.55 dB in the frequency range of 1.0 to 3.0 GHz.

Therefore, at a frequency of 1.9 GHz, the high frequency switching device of this embodiment has a frequency of 0.15.
The result is that the loss is small by dB.

On the other hand, the isolation is -1 at a frequency of 1.0 GHz in the high frequency switching device of this embodiment.
0 dB, -35 dB at frequency 1.9 GHz, frequency 3.
The characteristic is -15 dB at 0 GHz, and has the minimum characteristic at a frequency of 1.9 GHz.

On the other hand, the isolation of the conventional high frequency switching device was constant at -22 dB in the frequency range of 1.0 to 3.0 GHz. Therefore 1.9
At GHz, the result of this example is 13 dB smaller.

Next, FIG. 5 shows the layout pattern of the first embodiment. In FIG. 5, the transmission side terminal 3 is a FET
11 and one end of the spiral inductor 21. In addition, the transmission side terminal 4 is F
It is connected to one end of the ET 12 and is also connected to one end of the spiral inductor 22.

The other ends of the FETs 11 and 12 and the other ends of the inductors 21 and 22 are connected to a common connection point 8, and the antenna terminal 2 is connected to the common connection point 8.
Further, the reference potential input terminal 6 is connected to the common connection point 8 via a resistor 32 having a high resistance value. And FET1
A gate signal input terminal 5 is connected to the gate of No. 1 via a high resistance resistor 31, and a gate signal input terminal 7 is connected to the gate of the FET 12 via a high resistance resistor 32. In addition, in order to prevent interference between the two inductor elements 21 and 22, a GND region (see a satin portion) is provided so as to surround it. The chip size is 1.1 mm x
It was 1.0 mm.

Next, a second embodiment of the high frequency switching device according to the present invention will be described. The high-frequency switch device of the second embodiment has the same configuration as that of the first embodiment shown in FIG. 1, and in the high-frequency switch device of the first embodiment,
Set the gate width Wg of FET11 of the filter circuit on the transmission side to 1
The inductance of the inductor 21 is changed from 15.5 nH to 7.3 nH while being changed from 2 mm to 2 mm. At this time, the threshold voltage V _th of the FET 11 is -1.0 V, which is the same as in the first embodiment. This second
The result of measurement of the insertion loss of the high-frequency switch device of the example is shown by the white triangle in FIG. The insertion loss of the second embodiment is 0.9 dB at the frequency of 1.0 GHz, 0.3 dB at the frequency of 1.9 GHz, and 0.75 dB at the frequency of 3.0 GHz, and the loss is smaller than that of the first embodiment. Has become. It is considered that this is because the ON resistance of the FET 11 is reduced due to the increase in the gate width of the FET 11 on the transmission side.

On the other hand, the measurement result of the isolation of the high frequency switching device of the second embodiment was the same as that of the isolation of the first embodiment. This is because the impedance when the filter circuit on the receiving side is OFF is the same as that of the first embodiment and the second embodiment.
It is considered that they are the same in the above embodiments.

Next, FIG. 6 shows the configuration of a third embodiment of the high-frequency switch device according to the present invention. The high frequency switching device of this embodiment is the same as the high frequency switching device of the first or second embodiment shown in FIG. 1 except that DC blocking capacitors 40, 41 and 42 having a capacitance of several pF are newly provided. It operates on a power supply, for example + 3V and zeroV.

The capacitor 40 is provided between the antenna terminal 2 and the common connection point 8 of the transmitting side and receiving side filter circuits, and the capacitor 41 is provided between the transmitting side terminal 3 and the transmitting side filter circuit. 42 is provided between the receiving side terminal 4 and the receiving side filter circuit. In the transmission mode, the potential of + 3V is applied to the gate signal input terminal 5 and the reference potential input terminal 6, and the potential of 0V is applied to the gate signal input terminal 7. In the reception mode, 0V is applied to the gate signal input terminal 5, and + 3V is applied to the reference potential input terminal 6 and the gate signal input terminal 7.

It goes without saying that the high frequency switching device of the third embodiment also has the same loss characteristics as the high frequency switching device of the first embodiment.

In the high frequency switch device of the third embodiment, the DC blocking capacitors 40, 41 and 42 are provided.
Externally, it is possible to make the circuit configuration on the MMIC chip the same as that of the first or second embodiment operating with a negative power supply, so that an MMIC chip having versatility can be realized. .

In the above embodiment, 1.9 GH
Although the insertion loss and the isolation are minimized in z, the insertion loss and the isolation are minimized at a desired frequency by appropriately selecting the size of the FET and the size of the inductor that form the filter circuit. It goes without saying that you can do it.

In the above embodiment, the case of using the antenna switch of the digital cordless telephone has been described, but the present invention is not limited to this.

[0039]

As described above, according to the present invention, each transmission line is provided with a filter circuit which is turned on and off by a complementary signal, so that transmission loss can be minimized in a desired frequency band. Can be made smaller.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a high frequency switching device according to the present invention.

FIG. 2 is an equivalent circuit diagram of a filter circuit according to the present invention.

FIG. 3 is a graph showing insertion loss characteristics of the example of the present invention.

FIG. 4 is a graph showing isolation characteristics of the example of the present invention.

FIG. 5 is a diagram showing a layout pattern of the first embodiment.

FIG. 6 is a circuit diagram showing a configuration of a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing an example of a conventional high-frequency switch device.

FIG. 8 is a circuit diagram showing another example of a conventional high-frequency switch device.

[Explanation of symbols]

 2 Antenna terminal 3 Transmission side terminal 4 Reception side terminal 5,7 Gate signal input terminal 6 Reference potential input terminal 8 Common connection point 11,12 FET 21,22 Inductor 31,32,33 Resistance 40,41,42 DC blocking capacitor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04B 1/48

Claims (3)

[Claims] 1. A first to third terminal, a first FET and a first inductor connected in parallel to the first FET, one end of which is connected to the first terminal. Circuit, a second FET and a second inductor connected in parallel to the second FET, one end of which is connected to the other end of the first circuit and the other end of which is connected to the second terminal. A second circuit connected thereto, wherein a first control signal is applied to the gate of the first FET via a resistor and a second control circuit is applied to the gate of the second FET via a resistor. A high-frequency switch device, wherein a control signal is applied, the third terminal is connected to a common connection point of the first and second circuits, and a predetermined potential is applied to the common connection point. 2. A first capacitor provided between the first terminal and the first circuit, and a second capacitor provided between the second terminal and the second circuit.
2. The high frequency switch device according to claim 1, further comprising: a capacitor according to claim 1, and a third capacitor provided between the third terminal and the common connection point. 3. The gate width of the first FET is larger than the gate width of the second FET, and the inductance of the first inductor is smaller than the inductance of the second inductor. Item 1 or 2
The high-frequency switch device described.