JP2021022784A - Low noise amplifier and receiving module for radar device - Google Patents

Low noise amplifier and receiving module for radar device Download PDF

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JP2021022784A
JP2021022784A JP2019137089A JP2019137089A JP2021022784A JP 2021022784 A JP2021022784 A JP 2021022784A JP 2019137089 A JP2019137089 A JP 2019137089A JP 2019137089 A JP2019137089 A JP 2019137089A JP 2021022784 A JP2021022784 A JP 2021022784A
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effect transistor
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electrode
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controlled electrode
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治夫 小島
Haruo Kojima
治夫 小島
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Toshiba Infrastructure Systems and Solutions Corp
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Abstract

To improve insertion loss to reduce noise figure, in an amplifier.SOLUTION: According to an embodiment, in a low noise amplifier, a high frequency input terminal is connected to an input end of an amplifier circuit element via the drain and source of a first FET, and an output end of the amplifier circuit element is connected to a high frequency output terminal via the drain and source of a second FET. The high frequency input terminal is connected to the high frequency output terminal via the drain and source of a third FET and the drain and source of a fourth FET. The gate width of each of the first and second FETs is larger more than twice the gate width of each of the third and fourth FETs.SELECTED DRAWING: Figure 1

Description

この発明の実施形態は、低雑音増幅器とレーダ装置の受信モジュールに関する。 An embodiment of the present invention relates to a low noise amplifier and a receiving module of a radar device.

アクティブフェイズドアレイ型のレーダ装置では、受信モジュールのヘッドに、電界効果トランジスタ（以下、ＦＥＴ）スイッチのＤＣバイアス回路を省略した飽和回避型の低雑音増幅器の採用が検討されている。 In the active phased array type radar device, the adoption of a saturation avoidance type low noise amplifier in which the DC bias circuit of the field effect transistor (hereinafter referred to as FET) switch is omitted is being studied for the head of the receiving module.

この種の低雑音増幅器では、ＦＥＴスイッチのゲート幅が小さく、開放時のドレイン−ソース間の抵抗値を高抵抗にすることが可能である。しかしながら、短絡時におけるドレイン−ソース間の抵抗値を低抵抗にすることができない。このため、増幅モード時において高周波の損失が発生し、この損失が低雑音増幅器の入力側の損失となり、その分、雑音指数が悪化してしまう。 In this kind of low noise amplifier, the gate width of the FET switch is small, and it is possible to increase the resistance value between the drain and the source when the FET switch is open. However, the resistance value between the drain and the source at the time of a short circuit cannot be made low. Therefore, a high frequency loss occurs in the amplification mode, and this loss becomes a loss on the input side of the low noise amplifier, and the noise figure deteriorates by that amount.

特開２０１５−５５５２９号公報JP-A-2015-55529

この発明の実施形態の課題は、入力側での挿入損失を改善し、これによって雑音指数を低減することのできる低雑音増幅器とレーダ装置の受信モジュールを提供することにある。 An object of the embodiment of the present invention is to provide a receiving module of a low noise amplifier and a radar device capable of improving the insertion loss on the input side and thereby reducing the noise figure.

実施形態によれば、低雑音増幅器は、高周波入力端子、増幅回路素子、高周波出力端子、第１乃至第４のＦＥＴ、制御回路を備える。高周波入力端子には、第１のＦＥＴの第１の被制御電極（ドレイン）が接続され、その第２の被制御電極（ソース）は増幅回路素子の入力端に接続される。増幅回路素子の出力端には、第２のＦＥＴの第１の被制御電極（ドレイン）が接続され、その第２の被制御電極（ソース）は高周波出力端子に接続される。また、高周波入力端子には、第３のＦＥＴの第１の被制御電極（ドレイン）が接続され、高周波出力端子に第４のＦＥＴの第２の被制御電極（ソース）が接続され、第３のＦＥＴの第２の被制御電極（ソース）と第４のＦＥＴの第１の被制御電極（ドレイン）が接続され、第３のＦＥＴと第４のＦＥＴは、それぞれの制御電極に供給される制御電圧に応じて高周波入力端子及び高周波出力端子間の接続を断続する不等損スイッチ回路として機能する。第１乃至第４のＦＥＴは、それぞれの制御電極に供給される制御電圧に応じてオンオフ制御される。上記第１のＦＥＴ及び上記第２のＦＥＴそれぞれの制御電極（ゲート）の電極幅が前記第３のＦＥＴ及び第４のＦＥＴそれぞれの制御電極の電極幅より２倍以上大きいものとする。 According to the embodiment, the low noise amplifier includes a high frequency input terminal, an amplifier circuit element, a high frequency output terminal, first to fourth FETs, and a control circuit. The first controlled electrode (drain) of the first FET is connected to the high frequency input terminal, and the second controlled electrode (source) is connected to the input end of the amplifier circuit element. The first controlled electrode (drain) of the second FET is connected to the output end of the amplifier circuit element, and the second controlled electrode (source) is connected to the high frequency output terminal. Further, the first controlled electrode (drain) of the third FET is connected to the high frequency input terminal, the second controlled electrode (source) of the fourth FET is connected to the high frequency output terminal, and the third FET is connected. The second controlled electrode (source) of the FET and the first controlled electrode (drain) of the fourth FET are connected, and the third FET and the fourth FET are supplied to the respective control electrodes. It functions as an unequal loss switch circuit that interrupts the connection between the high-frequency input terminal and the high-frequency output terminal according to the control voltage. The first to fourth FETs are on / off controlled according to the control voltage supplied to the respective control electrodes. It is assumed that the electrode width of the control electrode (gate) of each of the first FET and the second FET is twice or more larger than the electrode width of the control electrode of each of the third FET and the fourth FET.

図１は、実施形態に係る低雑音増幅器の構成を示す回路図である。FIG. 1 is a circuit diagram showing a configuration of a low noise amplifier according to an embodiment. 図２は、図１に示す低雑音増幅器のインピーダンス特性を示す図である。FIG. 2 is a diagram showing impedance characteristics of the low noise amplifier shown in FIG. 図３は、実施形態が適用される低雑音増幅器の構成を示す回路図である。FIG. 3 is a circuit diagram showing a configuration of a low noise amplifier to which the embodiment is applied. 図４は、図３に示す低雑音増幅器のインピーダンス特性を示す図である。FIG. 4 is a diagram showing the impedance characteristics of the low noise amplifier shown in FIG. 図５は、上記実施形態の低雑音増幅器を用いたレーダ装置の受信モジュールの構成を示すブロック図である。FIG. 5 is a block diagram showing a configuration of a receiving module of a radar device using the low noise amplifier of the above embodiment.

以下、図面を参照しながら、種々の実施形態について説明する。
図３は、本実施形態が適用されるＦＥＴスイッチのＤＣバイアス回路を省略した飽和回避型低雑音増幅器の構成を示す回路図である。 Hereinafter, various embodiments will be described with reference to the drawings.
FIG. 3 is a circuit diagram showing a configuration of a saturation avoidant low noise amplifier in which the DC bias circuit of the FET switch to which the present embodiment is applied is omitted.

図３において、高周波入力端子１１には通常のゲート幅（100μm 〜200μm ）に設定された第１のＦＥＴ１５−ａのドレイン電極が接続され、第１のＦＥＴ１５−ａのソース電極は低雑音特性を有する増幅回路素子１３の入力端に接続され、増幅回路素子１３の出力端には第２のＦＥＴ１５−ｂのドレイン電極が接続され、第２のＦＥＴ１５−ｂのソース電極は高周波出力端子１２に接続されている。 In FIG. 3, the drain electrode of the first FET 15-a set to a normal gate width (100 μm to 200 μm) is connected to the high frequency input terminal 11, and the source electrode of the first FET 15-a has low noise characteristics. It is connected to the input end of the amplifier circuit element 13 to have, the drain electrode of the second FET 15-b is connected to the output end of the amplifier circuit element 13, and the source electrode of the second FET 15-b is connected to the high frequency output terminal 12. Has been done.

また、上記高周波入力端子１１には第３のＦＥＴ１５−ｃのドレイン電極が接続され、第３のＦＥＴ１５−ｃのソース電極には第４のＦＥＴ１５−ｄのドレイン電極が接続され、第４のＦＥＴ１５−ｄのソース電極は高周波出力端子１２に接続されている。第３のＦＥＴ１５−ｃ及び第４のＦＥＴ１５−ｄは不等損分配スイッチとして機能する。上記の各ＦＥＴ１５−ａ，１５−ｂ，１５−ｃ，１５−ｄは、いずれも制御回路１６からの制御電圧によってオン・オフ制御される。 Further, the drain electrode of the third FET 15-c is connected to the high frequency input terminal 11, the drain electrode of the fourth FET 15-d is connected to the source electrode of the third FET 15-c, and the fourth FET 15 is connected. The source electrode of −d is connected to the high frequency output terminal 12. The third FET 15-c and the fourth FET 15-d function as an unequal loss distribution switch. Each of the above FETs 15-a, 15-b, 15-c, and 15-d is on / off controlled by the control voltage from the control circuit 16.

上記構成において、制御回路１６は、通常時に、第１のＦＥＴ１５−ａと第２のＦＥＴ１５−ｂのゲート電極に印加される電圧（以下、ゲート電圧）を0Vとすることで、第１のＦＥＴ１５−ａと第２のＦＥＴ１５−ｂをそれぞれ短絡モードに設定する。また、同時に第３のＦＥＴ１５−ｃと第４のＦＥＴ１５−ｄのゲート電極に負電圧（通常はピンチオフとなる電圧-3V程度）を印加して、第３のＦＥＴ１５−ｃと第４のＦＥＴ１５−ｄを開放モードに設定する。これにより、高周波入力端子１１に印加された高周波信号は、経路１６のように増幅回路素子１３で増幅されて、高周波出力端子１２から出力される。 In the above configuration, the control circuit 16 normally sets the voltage applied to the gate electrodes of the first FET 15-a and the second FET 15-b (hereinafter referred to as the gate voltage) to 0V, so that the first FET 15 -A and the second FET 15-b are set to the short-circuit mode, respectively. At the same time, a negative voltage (usually a pinch-off voltage of about -3V) is applied to the gate electrodes of the third FET 15-c and the fourth FET 15-d to apply the third FET 15-c and the fourth FET 15-. Set d to open mode. As a result, the high-frequency signal applied to the high-frequency input terminal 11 is amplified by the amplifier circuit element 13 as in the path 16, and is output from the high-frequency output terminal 12.

また、制御回路１６は、飽和回避時に、第１のＦＥＴ１５−ａと第２のＦＥＴ１５−ｂのゲート電極に負電圧を印加して第１のＦＥＴ１５−ａと第２のＦＥＴ１５−ｂを開放モードに設定し、また同時に第３のＦＥＴ１５−ｃと第４のＦＥＴ１５−ｄのゲート電圧を0Vに設定し、それぞれのＦＥＴ１５−ｃ，１５−ｄを短絡モードに設定する。これにより、高周波入力端子１１に印加された高周波信号は、経路１７のように第３のＦＥＴ１５−ｃと第４のＦＥＴ１５−ｄを経由して高周波出力端子１２から出力される。したがって、高周波入力端子１１に印加された高周波信号により増幅回路素子１３の飽和を防止することができる。 Further, the control circuit 16 applies a negative voltage to the gate electrodes of the first FET 15-a and the second FET 15-b to open the first FET 15-a and the second FET 15-b when saturation is avoided. At the same time, the gate voltage of the third FET 15-c and the fourth FET 15-d is set to 0V, and the respective FETs 15-c and 15-d are set to the short-circuit mode. As a result, the high-frequency signal applied to the high-frequency input terminal 11 is output from the high-frequency output terminal 12 via the third FET 15-c and the fourth FET 15-d as in the path 17. Therefore, the saturation of the amplifier circuit element 13 can be prevented by the high frequency signal applied to the high frequency input terminal 11.

一般的に、増幅回路素子１３の入力飽和レベル（通常は1dB 利得圧縮時の入力電力で規定）は-10dBm 程度であり、ＦＥＴスイッチの飽和レベルはＦＥＴのゲート幅を200μm とした場合は20dBm 程度である。したがって、通常時と飽和回避時で入力飽和レベルは30dB程度向上する。ただし、通常、ゲート幅の小さいＦＥＴは、開放時のドレイン−ソース間抵抗値は高抵抗を実現可能であるが、その反面、短絡時におけるドレイン−ソース間抵抗値を低抵抗にできない欠点がある。 Generally, the input saturation level of the amplifier circuit element 13 (usually specified by the input power at 1 dB gain compression) is about -10 dBm, and the saturation level of the FET switch is about 20 dBm when the gate width of the FET is 200 μm. Is. Therefore, the input saturation level is improved by about 30 dB during normal operation and saturation avoidance. However, normally, a FET having a small gate width can achieve a high resistance between the drain and the source when it is open, but on the other hand, it has a drawback that the resistance between the drain and the source when it is short-circuited cannot be made low. ..

図４は、一例として、図３の回路構成において、増幅モード時におけるＡ点Ｂ点でのインピーダンスを示している。高周波入力端子１１から第３のＦＥＴ１５−ｃ側を見たインピーダンスはほぼ開放であるが、増幅回路素子１３側を見たインピーダンスは第１のＦＥＴ１５−ａのドレイン−ソース間の抵抗値が見えて所望のインピーダンスより高くなり、その分が増幅モード時における高周波の損失となってしまう。この損失は増幅回路素子１３の入力側の損失となるため、その分増幅回路素子１３の雑音指数が悪化してしまう欠点がある。 As an example, FIG. 4 shows the impedance at points A and B in the amplification mode in the circuit configuration of FIG. The impedance seen from the high frequency input terminal 11 to the third FET 15-c side is almost open, but the impedance seen from the amplifier circuit element 13 side shows the resistance value between the drain and the source of the first FET 15-a. The impedance becomes higher than the desired impedance, which results in a loss of high frequency in the amplification mode. Since this loss becomes a loss on the input side of the amplifier circuit element 13, there is a drawback that the noise figure of the amplifier circuit element 13 deteriorates accordingly.

（実施形態）
上記した欠点を解決し、増幅回路素子の入力側の挿入損失を大幅に改善して、その雑音指数を低減する実施形態を説明する。 (Embodiment)
An embodiment that solves the above-mentioned drawbacks, significantly improves the insertion loss on the input side of the amplifier circuit element, and reduces the noise figure will be described.

図１は本実施形態に係る低雑音増幅器の構成を示す回路図である。この低雑音増幅器は、図３に示した、ＦＥＴスイッチのＤＣバイアス回路を省略した飽和回避型の増幅器に本実施形態を適用したものであり、図１において、図３と同一部分には同一符号を付して、その説明を省略する。 FIG. 1 is a circuit diagram showing a configuration of a low noise amplifier according to the present embodiment. This low noise amplifier is an application of this embodiment to the saturation avoidant type amplifier shown in FIG. 3 in which the DC bias circuit of the FET switch is omitted. In FIG. 1, the same parts as those in FIG. 3 have the same reference numerals. , And the description thereof will be omitted.

図１において、高周波入力端子１１には第１のＦＥＴ１４−ａのドレイン電極が接続され、第１のＦＥＴ１４−ａのソース電極は増幅回路素子１３の入力端に接続され、増幅回路素子１３の出力端には第２のＦＥＴ１４−ｂのドレイン電極が接続され、第２のＦＥＴ１４−ｂのソース電極は高周波出力端子１２に接続される。また、高周波入力端子１１には第３のＦＥＴ１５−ｃのドレイン電極が接続され、第３のＦＥＴ１５−ｃのソース電極は第４のＦＥＴ１５−ｄのドレイン電極に接続され、第４のＦＥＴ１５−ｄのソース電極は高周波出力端子１２に接続される。第３のＦＥＴ１５−ｃと第４のＦＥＴ１５−ｄは不等損分スイッチとして機能する。なお、第１のＦＥＴ１４−ａと第２のＦＥＴ１４−ｂは通常のＦＥＴが３個並列接続された等価回路モデルで、第３のＦＥＴ１５−ａと第４のＦＥＴ１５−ｂと比べてゲート幅が３倍となっている。 In FIG. 1, the drain electrode of the first FET 14-a is connected to the high frequency input terminal 11, the source electrode of the first FET 14-a is connected to the input end of the amplifier circuit element 13, and the output of the amplifier circuit element 13 is output. The drain electrode of the second FET 14-b is connected to the end, and the source electrode of the second FET 14-b is connected to the high frequency output terminal 12. Further, the drain electrode of the third FET 15-c is connected to the high frequency input terminal 11, the source electrode of the third FET 15-c is connected to the drain electrode of the fourth FET 15-d, and the fourth FET 15-d is connected. The source electrode of is connected to the high frequency output terminal 12. The third FET 15-c and the fourth FET 15-d function as an unequal loss switch. The first FET 14-a and the second FET 14-b are equivalent circuit models in which three normal FETs are connected in parallel, and the gate width is larger than that of the third FET 15-a and the fourth FET 15-b. It has tripled.

上記の各ＦＥＴ１４−ａ，１４−ｂ，１５−ｃ，１５−ｄは、いずれも制御回路１６からの制御電圧によってオン・オフ制御される。 Each of the above FETs 14-a, 14-b, 15-c, and 15-d is on / off controlled by the control voltage from the control circuit 16.

ここで、制御回路１６は、通常時において、第１のＦＥＴ１４−ａと第２のＦＥＴ１４−ｂのゲート電圧を0Vに設定し、それぞれのＦＥＴ１４−ａ，１４−ｂを短絡モードに設定する。また同時に第３のＦＥＴ１５−ａと第４のＦＥＴ１５−ｂのゲート電極に負電圧（通常はピンチオフとなる電圧-3V 程度）を印加して、第３のＦＥＴ１５−ａと第４のＦＥＴ１５−ｂを開放モードに設定する。これにより、高周波入力端子１１に印加された高周波信号は、経路１６のように増幅回路素子１３で増幅され、高周波出力端子１２から出力される。 Here, in the normal state, the control circuit 16 sets the gate voltage of the first FET 14-a and the second FET 14-b to 0V, and sets the respective FETs 14-a and 14-b to the short-circuit mode. At the same time, a negative voltage (usually a pinch-off voltage of about -3V) is applied to the gate electrodes of the third FET 15-a and the fourth FET 15-b to apply the third FET 15-a and the fourth FET 15-b. Set to open mode. As a result, the high-frequency signal applied to the high-frequency input terminal 11 is amplified by the amplifier circuit element 13 as in the path 16, and is output from the high-frequency output terminal 12.

また、制御回路１６は、飽和回避時において、第１のＦＥＴ１４−ａと第２のＦＥＴ１４−ｂのゲート電極に負電圧を印加して第１のＦＥＴ１４−ａと第２のＦＥＴ１４−ｂを開放モードに設定し、また同時に第３のＦＥＴ１５−ａと第４のＦＥＴ１５−ｂのゲート電圧を0Vに設定し、それぞれのＦＥＴ１５−ａ，１５−ｂを短絡モードに設定する。これにより、高周波入力端子１１に印加された高周波信号は経路１７のように第３のＦＥＴ１５−ａと第４のＦＥＴ１５−ｂを経由して高周波出力端子１２から出力される。したがって、高周波入力端子１１に印加された高周波信号によって増幅回路素子１３が飽和することを防止することができる。 Further, the control circuit 16 applies a negative voltage to the gate electrodes of the first FET 14-a and the second FET 14-b to open the first FET 14-a and the second FET 14-b when saturation is avoided. The mode is set, and at the same time, the gate voltages of the third FET 15-a and the fourth FET 15-b are set to 0V, and the respective FETs 15-a and 15-b are set to the short-circuit mode. As a result, the high frequency signal applied to the high frequency input terminal 11 is output from the high frequency output terminal 12 via the third FET 15-a and the fourth FET 15-b like the path 17. Therefore, it is possible to prevent the amplifier circuit element 13 from being saturated by the high frequency signal applied to the high frequency input terminal 11.

通常ゲート幅の小さいＦＥＴは、短絡時のドレイン−ソース間の抵抗値を低抵抗に設定することはできないが、ゲート幅を３倍にすることで短絡時におけるドレイン−ソース間抵抗値を低抵抗にすることができる。なお、ゲート幅を２倍以上とすれば、実用上、十分な低抵抗にすることが可能である。 Normally, FETs with a small gate width cannot set the drain-source resistance value at the time of short circuit to low resistance, but by triple the gate width, the drain-source resistance value at the time of short circuit can be set to low resistance. Can be. If the gate width is doubled or more, it is possible to obtain a sufficiently low resistance in practical use.

図２は、一例として図１の回路構成において増幅モード時におけるＡ点、Ｂ点でのインピーダンスを示している。図２に示すように、高周波入力端子１１から第３のＦＥＴ１５−ａ側を見たインピーダンスは、ほぼ開放、増幅回路素子１３側を見たインピーダンスは第１のＦＥＴ１４−ａのドレイン−ソース間の抵抗値を低くすることが可能となり、ほぼ所望のインピーダンスを実現できている。その結果、増幅モード時における高周波の損失を小さくすることができ、その分、増幅回路素子１３の雑音指数の悪化を防止することができる。 FIG. 2 shows the impedance at points A and B in the amplification mode in the circuit configuration of FIG. 1 as an example. As shown in FIG. 2, the impedance seen from the high frequency input terminal 11 on the third FET 15-a side is almost open, and the impedance seen on the amplifier circuit element 13 side is between the drain and the source of the first FET 14-a. It is possible to lower the resistance value, and almost a desired impedance can be realized. As a result, the loss of high frequency in the amplification mode can be reduced, and the noise figure of the amplifier circuit element 13 can be prevented from deteriorating by that amount.

一例として、ゲート幅の小さいＦＥＴのゲート幅を100μm 、ゲート幅の大きいＦＥＴのゲート幅を300μm とし、Ku帯での雑音指数を試算したところ、2.6dB から1.8dB に低減されることが実証されている。 As an example, when the gate width of the FET with a small gate width is 100 μm and the gate width of the FET with a large gate width is 300 μm, the noise figure in the Ku band is calculated, and it is demonstrated that the noise figure is reduced from 2.6 dB to 1.8 dB. ing.

以上のように、本実施形態によれば、入力側で挿入損失を大幅に改善して増幅回路素子１３の雑音指数を低減することができる。 As described above, according to the present embodiment, the insertion loss can be significantly improved on the input side and the noise figure of the amplifier circuit element 13 can be reduced.

図５は、上記実施形態に係る低雑音増幅器を用いたレーダ装置の受信モジュールを示すブロック図である。図５において、本実施形態に係る低雑音増幅器１０は、受信モジュールのヘッドに配置され、アンテナ（図示せず）で捕捉されたレーダ受信信号が低雑音増幅器１０の高周波入力端子１１に供給される。低雑音増幅器１０で増幅されたレーダ受信信号は高周波出力端子１２から位相制御器２０に出力され、受信ビームの指向方向に応じた位相制御を受けてレーダ信号処理器（図示せず）に出力される。 FIG. 5 is a block diagram showing a receiving module of a radar device using the low noise amplifier according to the above embodiment. In FIG. 5, the low noise amplifier 10 according to the present embodiment is arranged at the head of the receiving module, and the radar reception signal captured by the antenna (not shown) is supplied to the high frequency input terminal 11 of the low noise amplifier 10. .. The radar reception signal amplified by the low noise amplifier 10 is output from the high frequency output terminal 12 to the phase controller 20, receives phase control according to the directivity of the received beam, and is output to the radar signal processor (not shown). To.

上記構成による受信モジュールは、低雑音増幅器１０の雑音指数が低減されているため、雑音に埋もれていた目標信号成分を検出できるようになり、レーダ性能を向上させることができる。 Since the noise figure of the low noise amplifier 10 is reduced in the receiving module having the above configuration, it becomes possible to detect the target signal component buried in the noise, and the radar performance can be improved.

なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。例えば、実施形態に示される全構成要素から幾つかの構成要素を削除してもよい。さらに、異なる実施形態にわたる構成要素を適宜組み合わせてもよい。 The present invention is not limited to the above embodiment as it is, and at the implementation stage, the components can be modified and embodied within a range that does not deviate from the gist thereof. In addition, various inventions can be formed by an appropriate combination of the plurality of components disclosed in the above-described embodiment. For example, some components may be removed from all the components shown in the embodiments. In addition, components across different embodiments may be combined as appropriate.

１０…低雑音増幅器、１１…高周波入力端子、１２…高周波出力端子、１３…増幅回路素子、１４−ａ…第１のＦＥＴ、１４−ｂ…第２のＦＥＴ、１５−ａ…第３のＦＥＴ、１５−ｂ…第４のＦＥＴ、２０…位相制御器。 10 ... low noise amplifier, 11 ... high frequency input terminal, 12 ... high frequency output terminal, 13 ... amplifier circuit element, 14-a ... first FET, 14-b ... second FET, 15-a ... third FET , 15-b ... Fourth FET, 20 ... Phase controller.

Claims (3)

高周波信号が入力される高周波入力端子と、
前記高周波入力端子に入力される高周波信号を低雑音で増幅する増幅回路素子と、
前記増幅回路素子で増幅された高周波信号を出力する高周波出力端子と、
前記高周波入力端子に第１の被制御電極が接続され、前記増幅回路素子の入力端に第２の被制御電極が接続され、制御電極に供給される制御電圧に応じて前記第１の被制御電極及び前記第２の被制御電極の間を断続する第１の電界効果トランジスタと、
前記増幅回路素子の出力端に第１の被制御電極が接続され、前記高周波出力端子に第２の被制御電極が接続され、制御電極に供給される制御電圧に応じて前記第１の被制御電極及び前記第２の被制御電極の間を断続する第２の電界効果トランジスタと、
前記高周波入力端子に第３の電界効果トランジスタの第１の被制御電極が接続され、前記高周波出力端子に第４の電界効果トランジスタの第２の被制御電極が接続され、前記第３の電界効果トランジスタの第２の被制御電極と前記第４の電界効果トランジスタの第１の被制御電極が接続され、前記第３の電界効果トランジスタと前記第４の電界効果トランジスタそれぞれの制御電極に供給される制御電圧に応じて前記高周波入力端子及び前記高周波出力端子間の接続を断続する不等損スイッチ回路と、
前記第１乃至第４の電界効果トランジスタそれぞれの制御電極に供給する制御電圧を生成する制御回路と
を具備し、
前記第１の電界効果トランジスタ及び前記第２の電界効果トランジスタそれぞれの制御電極の電極幅が前記第３の電界効果トランジスタ及び前記第４の電界効果トランジスタそれぞれの制御電極の電極幅より２倍以上大きい低雑音増幅器。 High frequency input terminal to which high frequency signal is input and
An amplifier circuit element that amplifies the high-frequency signal input to the high-frequency input terminal with low noise, and
A high-frequency output terminal that outputs a high-frequency signal amplified by the amplifier circuit element, and
The first controlled electrode is connected to the high frequency input terminal, the second controlled electrode is connected to the input end of the amplifier circuit element, and the first controlled electrode is controlled according to the control voltage supplied to the control electrode. A first field effect transistor intermittently between the electrode and the second controlled electrode,
A first controlled electrode is connected to the output end of the amplifier circuit element, a second controlled electrode is connected to the high frequency output terminal, and the first controlled electrode is controlled according to a control voltage supplied to the control electrode. A second field effect transistor intermittently between the electrode and the second controlled electrode,
The first controlled electrode of the third field effect transistor is connected to the high frequency input terminal, the second controlled electrode of the fourth field effect transistor is connected to the high frequency output terminal, and the third field effect is connected. The second controlled electrode of the transistor and the first controlled electrode of the fourth field effect transistor are connected and supplied to the control electrodes of the third field effect transistor and the fourth field effect transistor. An unequal loss switch circuit that interrupts the connection between the high-frequency input terminal and the high-frequency output terminal according to the control voltage, and
It is provided with a control circuit for generating a control voltage to be supplied to the control electrodes of each of the first to fourth field effect transistors.
The electrode widths of the control electrodes of the first field-effect transistor and the second field-effect transistor are more than twice as large as the electrode widths of the control electrodes of the third field-effect transistor and the fourth field-effect transistor. Low noise amplifier. 前記制御回路は、
通常時に、前記第１の電界効果トランジスタと前記第２の電界効果トランジスタそれぞれの制御電極に供給する制御電圧を短絡モードの電圧に設定し、同時に前記第３の電界効果トランジスタと前記第４の電界効果トランジスタそれぞれの制御電極に供給する制御電圧を開放モードの電圧に設定して、前記高周波入力端子に供給された高周波信号を前記増幅回路素子で増幅して前記高周波出力端子１２から出力するようにし、
飽和回避時に、前記第１の電界効果トランジスタと前記第２の電界効果トランジスタそれぞれの制御電極に供給する制御電圧を開放モードの電圧に設定し、同時に前記第３の電界効果トランジスタと前記第４の電界効果トランジスタそれぞれの制御電極に供給する制御電圧を短絡モードの電圧に設定することで、前記高周波入力端子に供給された高周波信号を前記第３の電界効果トランジスタと前記第４の電界効果トランジスタを経由して高周波出力端子１２から出力する
請求項１記載の低雑音増幅器。 The control circuit
At normal times, the control voltage supplied to the control electrodes of the first field-effect transistor and the second field-effect transistor is set to the voltage in the short-circuit mode, and at the same time, the third field-effect transistor and the fourth field effect transistor are set. Effect The control voltage supplied to the control electrodes of each transistor is set to the voltage in the open mode, and the high-frequency signal supplied to the high-frequency input terminal is amplified by the amplifier circuit element and output from the high-frequency output terminal 12. ,
At the time of avoiding saturation, the control voltage supplied to the control electrodes of the first field-effect transistor and the second field-effect transistor is set to the voltage in the open mode, and at the same time, the third field-effect transistor and the fourth field-effect transistor By setting the control voltage supplied to the control electrodes of each field-effect transistor to the voltage in the short-circuit mode, the high-frequency signal supplied to the high-frequency input terminal can be used as the third field-effect transistor and the fourth field-effect transistor. The low noise amplifier according to claim 1, which outputs from the high frequency output terminal 12 via the device. レーダ装置のアンテナで捕捉されたレーダ受信信号を低雑音で増幅する低雑音増幅器と、
前記低雑音増幅器で増幅されたレーダ受信信号に受信ビームの指向方向に応じた位相制御を施す位相制御器とを具備し、
前記低雑音増幅器は、
前記レーダ受信信号が入力される入力端子と、
前記入力端子に入力されるレーダ受信信号を低雑音で増幅する増幅回路素子と、
前記増幅回路素子で増幅されたレーダ受信信号を出力する出力端子と、
前記入力端子に第１の被制御電極が接続され、前記増幅回路素子の入力端に第２の被制御電極が接続され、制御電極に供給される制御電圧に応じて前記第１の被制御電極及び前記第２の被制御電極の間を断続する第１の電界効果トランジスタと、
前記増幅回路素子の出力端に第１の被制御電極が接続され、前記出力端子に第２の被制御電極が接続され、制御電極に供給される制御電圧に応じて前記第１の被制御電極及び前記第２の被制御電極の間を断続する第２の電界効果トランジスタと、
前記入力端子に第３の電界効果トランジスタの第１の被制御電極が接続され、前記出力端子に第４の電界効果トランジスタの第２の被制御電極が接続され、前記第３の電界効果トランジスタの第２の被制御電極と前記第４の電界効果トランジスタの第１の被制御電極が接続され、前記第３の電界効果トランジスタと前記第４の電界効果トランジスタそれぞれの制御電極に供給される制御電圧に応じて前記入力端子及び前記出力端子間の接続を断続する不等損スイッチ回路と、
前記第１乃至第４の電界効果トランジスタそれぞれの制御電極に供給する制御電圧を生成する制御回路と
を具備し、
前記第１の電界効果トランジスタ及び前記第２の電界効果トランジスタそれぞれの制御電極の電極幅が前記第３の電界効果トランジスタ及び前記第４の電界効果トランジスタそれぞれの制御電極の電極幅より２倍以上大きいレーダ装置の受信モジュール。 A low noise amplifier that amplifies the radar reception signal captured by the antenna of the radar device with low noise,
A phase controller that performs phase control according to the directivity direction of the received beam to the radar received signal amplified by the low noise amplifier is provided.
The low noise amplifier
An input terminal to which the radar reception signal is input and
An amplifier circuit element that amplifies the radar reception signal input to the input terminal with low noise, and
An output terminal that outputs a radar reception signal amplified by the amplifier circuit element, and
A first controlled electrode is connected to the input terminal, a second controlled electrode is connected to the input end of the amplifier circuit element, and the first controlled electrode is connected according to a control voltage supplied to the control electrode. And the first field effect transistor intermittently between the second controlled electrode, and
A first controlled electrode is connected to the output end of the amplifier circuit element, a second controlled electrode is connected to the output terminal, and the first controlled electrode is connected according to a control voltage supplied to the control electrode. And a second field effect transistor intermittently between the second controlled electrode,
The first controlled electrode of the third field effect transistor is connected to the input terminal, the second controlled electrode of the fourth field effect transistor is connected to the output terminal, and the third field effect transistor of the third field effect transistor is connected. The control voltage supplied to the control electrodes of the third field effect transistor and the fourth field effect transistor by connecting the second controlled electrode and the first controlled electrode of the fourth field effect transistor. An unequal loss switch circuit that interrupts the connection between the input terminal and the output terminal according to
It is provided with a control circuit for generating a control voltage to be supplied to the control electrodes of each of the first to fourth field effect transistors.
The electrode widths of the control electrodes of the first field-effect transistor and the second field-effect transistor are more than twice as large as the electrode widths of the control electrodes of the third field-effect transistor and the fourth field-effect transistor. Receiving module of radar device.
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Citations (4)

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JPH05505466A (en) * 1991-03-08 1993-08-12 インターナショナル・スタンダード・エレクトリック・コーポレイション TR module with error correction
JPH0923101A (en) * 1995-07-05 1997-01-21 Toshiba Corp High frequency switching device
WO2007129716A1 (en) * 2006-05-08 2007-11-15 Hitachi Metals, Ltd. High frequency circuit, high frequency part, and communication device
JP2013090263A (en) * 2011-10-21 2013-05-13 Toshiba Corp Reception circuit for phased array radar and transmission/reception module for phased array radar

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05505466A (en) * 1991-03-08 1993-08-12 インターナショナル・スタンダード・エレクトリック・コーポレイション TR module with error correction
JPH0923101A (en) * 1995-07-05 1997-01-21 Toshiba Corp High frequency switching device
WO2007129716A1 (en) * 2006-05-08 2007-11-15 Hitachi Metals, Ltd. High frequency circuit, high frequency part, and communication device
JP2013090263A (en) * 2011-10-21 2013-05-13 Toshiba Corp Reception circuit for phased array radar and transmission/reception module for phased array radar

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