JP3989916B2 - Switch matrix - Google Patents

Description

  The present invention relates to a switch matrix, and more particularly to a multi-input multi-output switch matrix that outputs an input signal by switching to an arbitrary output.

  Single-pole double-throw switch (hereinafter referred to as SPDT switch) using a field effect transistor (hereinafter referred to as FET), or generally a single-pole n-throw switch (Sing1e-Po1e n-Throw Switch, hereinafter referred to as SPnT switch). , Where n is an integer greater than or equal to 2), because of the characteristics of wideband, low power consumption and high speed switching speed, the transmission / reception switch of the wireless communication portable terminal and the input signal are switched to an arbitrary output and output. Widely used in multi-input multi-output switch matrices.

  FIG. 14 is a diagram showing a circuit configuration of a conventional switch matrix described in Patent Document 1 below. In the figure, a code starting with 1 is an input terminal, a code starting with 2 is an output terminal, a code starting with 3 is a FET, a code starting with 4 is a resistor, a code starting with 5 is a transmission line, a code starting with 6 is a control terminal, 9 Reference numerals beginning with indicate each SPDT switch.

This conventional example is a 2 × 2 switch matrix when the number of input / output terminals is 2, and the input / output terminals 11, 12, 21, and 22 are provided with SPDT switches 91 ₁ , 91 ₂ , 92 ₁ , and 92 ₂ , respectively. These SPDT switches operate as a switch matrix by connecting four interconnection transmission lines 51-54. Each SPDT switch is a series shunt FET configuration, for example, in the case of the SPDT switch 91 _1, and a series FET 31 ₁ and the shunt FET 31 _1S and series FET 31 ₂ and the shunt FET 31 _2S.

  The operation of this switch matrix is as follows.

Signal input from the input terminal 11 is input to the SPDT switch 91 ₁ is output to the transmission line 52 is a connection route to the transmission line 51 or SPDT switch 92 ₂ is a connection route to the SPDT switch 92 ₁ The

Similarly, the signal input from the input terminal 12 is inputted to the SPDT switch 91 _2, the transmission line 54 transmission line 53 or a connection route to the SPDT switch 92 _1, or a connection route to the SPDT switch 92 ₂ Is output.

In SPDT switch 92 ₁ is controlled to output either a signal from the transmission line 51 or the transmission line 53 to the output terminal 21, in the SPDT switch 92 _2, both from the transmission line 52 or the transmission line 54 One of the signals is controlled to be output to the output terminal 22.

Here, the gate bias of the SPDT switch 91 ₁ and 92 _1, the series FET 31 ₁ SPDT switch 91 _1, the shunt FET 31 _2S and SPDT switch 91 _{and second} series FET 32 _1, shunt FET 32 _2S control terminal 61, the SPDT switch 91 ₁ series FET 31 _2, shunt FET 31 _1S and SPDT switch 91 _{and second} series FET 32 _2, it has to be applied to the common respectively from the shunt FET 32 _1S control terminal 62. Similarly, the SPDT switches 92 ₁ and 92 ₂ connected to the output terminals 21 and 22 are configured to be able to apply a gate bias from the two control terminals 61 and 62.

  The switch of the series shunt FET configuration controls the series FET to be ON and the shunt FET to be OFF when passing, and controls the series FET to be OFF and the shunt FET to be ON when the switch is cut off. Therefore, in the conventional example shown in FIG. 14, by applying a complementary voltage to the control terminals 61 and 62, the signal passing state is output from the output terminal 21 and the signal input to the input terminal 11 is output. A passing state in which the signal input to the terminal 12 is output from the output terminal 22, the signal input to the input terminal 11 is output from the output terminal 22, and the signal input to the input terminal 12 is output from the output terminal 21. It can be switched in two ways with the passing state.

Japanese Patent Laid-Open No. 6-232604

  This conventional switch matrix has the following problems.

First, since the signal passing path is connected to the ground by the shunt FETs 31 _1S , 31 _2S , 32 _1S , and 32 _2S , the baseband signal having a DC level other than 0V cannot be passed. .

  Secondly, when a switch is configured by MESFET or HEMT using a compound semiconductor such as GaAs, there is a problem that the positive power supply operation is difficult.

  What is important in the characteristics of the switch is the insertion loss of the ON path and the isolation of the OFF path. Of these, the insertion loss mainly depends on the ON resistance (Ron) of the FET used, and the isolation mainly depends on the OFF capacitance (Coff) of the FET. For this reason, MESFETs and HEMTs using compound semiconductors such as GaAs that can reduce the ON resistance and the OFF capacitance are frequently used as high frequency switching devices.

  However, since MESFETs and HEMTs are generally depletion (normally on) type FETs, the threshold voltage (Vth) is a negative voltage. Accordingly, when the drain and source potentials are automatically set to 0 V by the shunt FET as in the conventional example, when the gate bias is 0 V, the FET is in the on state, and to turn the FET off, Vth A lower negative voltage is required, and a negative voltage generation circuit is required for the control circuit. In particular, in a portable terminal, since the negative voltage generation circuit occupies a large area for mounting, a positive power supply operation of the FET switch is strongly desired.

These problems, as shown in FIG. 15 (a), resolved by the exception of shunt FET, constitute the SPDT switch _{91 1,} 91 _2, 92 1, 92 ₂ only series FET 31 ₁ to 34C ₂ Is expected to be. However, in the conventional example shown in FIG. 15, for example, the signal passes from the input terminal 11 to the output terminal 22, and from the input terminal 12 to the output terminal 21. In this case, although the same potential as the source is applied to the drain terminal of the FET of the ON path via the low resistance Ron, the DC potential is not determined at the drain terminal of the FET of the OFF path. There is a problem that the transmission characteristics deteriorate. Furthermore, when a signal having a direct current component is passed, there arises a problem that the fluctuation of the direct current level due to the ON resistance value (Ron) of the FET cannot be compensated. The former problem can be solved, for example, by connecting all the transmission lines 51 to 54 to the ground via a resistor having a very large resistance value compared to the characteristic impedance of the transmission line. The signal passing path is connected to the ground, and the problem that the baseband signal with a DC level other than 0V cannot be passed and the problem that the positive power supply operation is difficult are the conventional problems shown in FIG. Like the example, it remains unresolved.

  The object of the present invention is to solve the above-mentioned problems in the conventional switch matrix technology, that is, the problem that a baseband signal with a DC level other than 0V cannot be passed and the problem that the positive power supply operation is difficult. Another object of the present invention is to provide a switch matrix capable of passing a baseband signal having a DC level other than 0 V and capable of positive power supply operation.

In the present invention, in order to achieve the above object, as described in claim 1,
Two input terminals, two input side single pole double throw switches, four transmission lines, two output terminals, and two output side single pole double throw switches, the input side Each of the single-pole double-throw switch and the output-side single-pole double-throw switch includes two field effect transistors, and one of the drains or sources of the two field effect transistors is connected to one common terminal. The other is connected to the two switch terminals in a one-to-one relationship, the two input terminals are connected to the common terminal in the two input-side single-pole double-throw switches in a one-to-one relationship, and the two output terminals Are connected to the common terminals of the two output-side single-pole double-throw switches on a one-to-one basis, enabling signal transmission from each of the input-side single-pole double-throw switches to each of the output-side single-pole double-throw switches. So that the switch on the input side single-pole double-throw switch 2 in each of the input-side single-pole double-throw switches in the switch matrix in which the four transmission lines are connected one-to-one between the switch terminal and the switch terminal of the output-side single-pole double-throw switch. These switch terminals are connected by resistors, or two switch terminals in each of the output side single-pole double throw switches are connected by resistors.

In the present invention, as described in claim 2,
2. The switch matrix according to claim 1, wherein the resistor is bent between the field effect transistors or between the transmission lines.

In the present invention, as described in claim 3,
3. The switch matrix according to claim 1, wherein a common terminal in the two input-side single-pole double-throw switches is connected to a control terminal via an inductor, or in the output-side single-pole double-throw switch. The common terminal is connected to the control terminal via an inductor to constitute a switch matrix.

In the present invention, as described in claim 4,
3. The switch matrix according to claim 1, wherein a common terminal in the two input-side single-pole double-throw switches is connected to a control terminal via a resistor, or in the output-side single-pole double-throw switch. The common terminal is connected to the control terminal via a resistor to form a switch matrix.

In the present invention, as described in claim 5,
5. The switch matrix according to claim 3, wherein the two input terminals are connected one-to-one to a common terminal in the two input-side single-pole double-throw switches through a capacitor. Configure the switch matrix.

In the present invention, as described in claim 6,
6. The switch matrix according to claim 5, wherein the two output terminals are connected one-to-one to a common terminal in the two output-side single-pole double-throw switches through a capacitor. Configure.

In the present invention, as described in claim 7,
When n is an integer of 2 or more, n input terminals, n input-side single-pole n-throw switches, n ² transmission lines, n output terminals, and n output-side singles Each of the input-side single-pole n-throw switch and the output-side single-pole n-throw switch includes n field-effect transistors, and the drains or sources of the n field-effect transistors Is connected to one common terminal, the other is connected to n switch terminals in a one-to-one relationship, and the n input terminals are paired to a common terminal in the n input-side single-pole n-throw switches. The n output terminals are connected one-to-one to the common terminals of the n output side single pole n throw switches, and the output side single pole is connected to each of the input side single pole n throw switches. To enable signal transmission to each of the n-throw switches, In the switch matrix in which the switch terminals of the input-side single-pole n-throw switch and the output-side single-pole n-throw switch are connected one-to-one with the n ² transmission lines, the input side N switch terminals in each single-pole n-throw switch are connected one-to-one to n other ends of n resistors, one end of which is connected to one common conductor, or The n switch terminals in each of the output-side single-pole n-throw switches are connected one-to-one to the n other ends of the n resistors whose one ends are connected to one common conductor. The switch matrix is configured as follows.

In the present invention, as described in claim 8,
8. The switch matrix according to claim 7, wherein a resistor having one end connected to the common conductor is disposed between the transmission lines in parallel with the transmission line.

In the present invention, as described in claim 9,
9. The switch matrix according to claim 7, wherein at least one control terminal is connected to the common conductor.

In the present invention, as described in claim 10,
10. The switch matrix according to claim 7, 8, or 9, wherein a common terminal of the n input-side single-pole n-throw switches is connected to a control terminal via an inductor, or the output-side single-pole n-throw switch. A switch matrix is characterized in that a common terminal in the switch is connected to a control terminal via an inductor.

In the present invention, as described in claim 11,
10. The switch matrix according to claim 7, 8, or 9, wherein a common terminal of the n input-side single-pole n-throw switches is connected to a control terminal through a resistor, or the output-side single-pole n-throw switch. A switch matrix is characterized in that a common terminal of the switch is connected to a control terminal via a resistor.

In the present invention, as described in claim 12,
12. The switch matrix according to claim 9, 10 or 11, wherein the n input terminals are connected one-to-one to a common terminal of the n input side single pole n throw switches through a capacitor. The switch matrix is configured as follows.

In the present invention, as described in claim 13,
13. The switch matrix according to claim 12, wherein the n output terminals are connected one-to-one to a common terminal in the n output-side single-pole n-throw switches through a capacitor. Configure.

  In the switch matrix according to the present invention, SPnT switches using series FETs are arranged at the input and output, and connected to each other via an interconnection transmission line, the terminals of the FETs connected to the interconnection transmission line side. Since the switches are connected to each other by a resistor, it is possible to achieve high isolation of the switch independent of the control voltage polarity and the signal DC logic level and to compensate for the DC level fluctuation. Accordingly, a baseband signal with a DC level other than 0V can be passed, and a positive power supply operation is possible, so that the problems associated with the switch matrix having the conventional configuration can be solved. That is, by implementing the present invention, it is possible to provide a switch matrix capable of passing a baseband signal having a DC level other than 0 V and capable of positive power supply operation.

  In the following, embodiments of the present invention are illustrated, and thereby the best mode for carrying out the present invention will be described.

[First Embodiment]
FIG. 1A is a diagram showing a configuration of a switch matrix according to the first embodiment of the present invention. In the figure, a code starting with 1 is an input terminal, a code starting with 2 is an output terminal, a code starting with 3 is a field effect transistor (hereinafter referred to as FET), a code starting with 4 is a resistor, a code starting with 5 is a transmission line, Reference numerals starting with 6 represent control terminals, and reference numerals beginning with 9 represent single-pole double-throw switches (hereinafter referred to as SPDT switches).

The switch matrix includes two input terminals 11 and 12, two input-side SPDT switches 91 ₁ and 91 ₂ , four transmission lines 51 to 54, two output terminals 21 and 22, A switch matrix comprising a plurality of output side SPDT switches 92 ₁ , 92 ₂ ;
Each of the input-side SPDT switches 91 ₁ and 91 ₂ and the output-side SPDT switches 92 ₁ and 92 ₂ has one of its drain or source connected to a common terminal (not shown) and the other two switch terminals (see FIG. 2 FETs 31 ₁ and 31 ₂ , 32 ₁ and 32 ₂ , 33 ₁ and 33 ₂ , 34 ₁ and 34 _{2 connected} to each other
Input terminals 11 and 12 are respectively connected to one-to-one to the common terminal of the input-side SPDT switch ₉₁ 1, 91 _2,
The output terminals 21 and 22 are respectively connected to the common terminals of the output side SPDT switches 92 ₁ and 92 ₂ in a one-to-one relationship.
A switch terminal of the input side SPDT switch and a switch terminal of the output side SPDT switch so that signal transmission from each of the input side SPDT switches 91 ₁ and 91 ₂ to each of the output side SPDT switches 92 ₁ and 92 ₂ is possible. Is a switch matrix in which four transmission lines 51 to 54 are connected in a one-to-one relationship,
Features of the switch matrix between the two switch terminals in each of the input-side SPDT switch ₉₁ 1, 91 _2, is that each is connected by a resistor 45 and 46.

That is, the present switch matrix that has a resistor 45 and 46 is disposed between the SPDT switches 91 ₁ and 91 ₂ of the series FET is (as shown in (a) of FIG. 15) conventional example are different, this is This is a feature of this switch matrix.

  The operation of this switch matrix will be described focusing on the difference from the conventional example.

  The difference between the present embodiment and the conventional example shown in FIG. 15A is that resistors 45 and 46 having very large resistance values compared to the characteristic impedance of the transmission lines 51 to 54 are arranged. It is.

  Thereby, for example, when the signal is in a passing state in which the signal passes from the input terminal 11 to the output terminal 22 and from the input terminal 12 to the output terminal 21 (an equivalent circuit is shown in FIG. 1B), the OFF path Since a voltage having substantially the same potential as that of the source is also applied to the drain terminal of the FET via the resistors 45 and 46, the FET can be normally pinched off, and deterioration of isolation characteristics can be prevented. Further, since the signal passing path is not connected to the ground, a baseband signal having an arbitrary DC level can be passed.

Figure 2 is an illustration of an embodiment of the SPDT switch 91 ₁ near the pattern layout in Fig. 1, and illustrates what (a) was used a microstrip line on the transmission line 51 and 52, (b ) Illustrates a transmission line 51, 52 using a coplanar line.

  The presence of the resistors 45 and 46 can determine the potential of the FET in the OFF path, while the signal leaks through these resistors. Since this leakage causes an increase in insertion loss and deterioration of isolation, it is desirable that the resistance values of the resistors 45 and 46 be as large as possible.

  Generally, the resistance value of a resistor formed on a semiconductor substrate is uniquely determined by the ratio of length to width. For example, when the sheet resistance value is 100Ω, a resistance of 1 kΩ can be formed if the ratio of length to width is 10, and a resistance of 10 kΩ can be formed if the ratio is 100. Therefore, as the elongated resistor is used, a larger resistance value can be realized.

Therefore, as shown in FIG. 2A, the resistance value of the resistor 45 is greatly increased even in a small space by forming a resistor by bending between the microstrip lines as the transmission lines 51 and 52. Is possible. Further, as shown in FIG. 2B, a configuration may be adopted in which a resistor 45 is bent between the FETs 31 ₁ and 31 ₂ , and thereby, a coplanar including transmission lines 51 and 52 and including a ground conductor. Crossing between the line and the resistance can be completely avoided. Accordingly, the resistance value of the resistor 45 can be increased without increasing the circuit size, and at the same time, the deterioration of the isolation caused by the crossing is not caused. Performance can be achieved.

  FIG. 5 is a diagram comparing the isolation characteristics of the prototype 2 × 2 switch matrix of this embodiment and the conventional 2 × 2 switch matrix. It has been demonstrated that the isolation characteristics can be improved by about 2 dB by applying the resistors 45 and 46.

Note that without being limited to the embodiments illustrated in FIG. 1, to may be a configuration of arranging the SPDT switch 92 _1, 92 ₂ side to the resistor 45 and 46 in the same connection type, both SPDT switch side of the input-output A configuration in which similar resistors are arranged in the same connection form may be used.

[Second Embodiment]
FIG. 3 is a diagram showing a switch matrix according to the second embodiment of the present invention.

In the present embodiment, as compared with the first embodiment illustrated in FIG. 1, the resistors 45 and 46 are divided into resistors 45 ₁ , 45 ₂ and 46 ₁ , 46 ₂ , respectively, and the control terminal 63 The difference is that the dividing points of these resistors are connected. The resistors _{45 1,} 45 _2, 46 1, 46 ₂ of the resistance value is much higher than the characteristic impedance of the transmission line 51 to 54, is preferably set to the same resistance value.

  This embodiment will be described with a focus on differences from the first embodiment.

  In the switch matrix of the present embodiment, it is most important that a bias can be applied to the source or drain of the FET connected from the control terminal 63 to the transmission lines 51 to 54 independently of the drain or source on the input / output terminal side. There are features. As a result, when a signal including a DC component is allowed to pass, fluctuations in the DC level caused by the ON resistance value (Ron) of the FET can be suppressed. This is because a voltage drop generated when passing through the FET can be compensated by a bias from the control terminal 63.

Figure 4 is an illustration of an embodiment of the SPDT switch 91 ₁ near the pattern layout in Fig. 3, (a), illustrates that using coplanar line to both the transmission lines 51 and 52 (b) ing.

4A and 4B, the resistors 45 ₁ and 45 ₂ are arranged approximately in the middle between the center conductor and the ground conductor of the coplanar line so that the longitudinal directions thereof are parallel to each other. By arranging in this way, the resistance values of the resistors 45 ₁ and 45 ₂ can be increased without intersecting with the central conductor and the ground conductor, so that the switch matrix can be reduced in size / economic / performance. .

Note that the present invention is not limited to the embodiment illustrated in FIG. 3, and the resistors 45 ₁ , 45 ₂ , 46 ₁ , and 46 ₂ and the control terminal 63 are arranged in the same connection form on the SPDT switches 92 ₁ and 92 ₂ side. Alternatively, a configuration may be adopted in which similar resistors and control terminals are arranged in the same connection form on both input and output SPDT switches.

[Third Embodiment]
6 and 7 are diagrams showing a switch matrix according to the third embodiment of the present invention, which is a modified example of the first embodiment. In the figure, a symbol starting with 7 indicates a capacitor, and a symbol starting with 8 indicates an inductor. The switch matrix of the present embodiment will be described focusing on differences from the first embodiment.

This embodiment, capacitors _{71 1,} 71 _2, 72 1, 72 ₂ by then galvanically separated input and output terminals and the SPDT switch, the inductor ₈₁ 1, 81 ₂ or resistor _{47 1,} 47 _2, 47 3, 47 ₄ is characterized in that the bias of the source or drain of the FET can be applied via ₄ . Here, the inductors ₈₁ 1, 81 ₂ of the impedance and the resistor _{47 1,} 47 _2, 47 3, 47 resistance value of _4, the same value and in comparison with the characteristic impedance of the transmission line 51 to 54 to a sufficiently large value Is set. Preferably, the control terminals 64 ₁ , 64 _{2 in} FIG. 6 and the control terminals 64 ₁ , 64 ₂ , 64 ₃ , 64 _{4 in} FIG. 7 are provided on a substrate on which a switch matrix is formed or a package on which the switch matrix is mounted. Are connected to corresponding inductors or resistors, respectively. Some of these control terminals may be the same. The capacitor _{71 1,} 71 _2, 72 1, 72 ₂ of the capacitance value is set so that the impedance at the desired frequency is sufficiently small value.

Therefore, the control terminal by ₆₄ 1 to 64 ₄ by applying a voltage, in the case where the threshold voltage (Vth) is using the negative voltage at which the depletion (normally-on) type FET also the source / drain of the FET The potential can be raised and positive power supply operation becomes possible. This makes it possible to apply MESFETs and HEMTs using compound semiconductors such as GaAs, which have the features of low ON resistance and low OFF capacity, to a switch matrix for positive power supply operation, and downsizing / high performance of the device Can be achieved.

Further, the capacitors _{71 1,} 71 _2, 72 1, 72 ₂ by the external, may be easily applied to large-capacity capacitor. As a result, a signal having a component close to a direct current can be passed without deterioration.

It should be noted that the inductors 81 ₁ and 81 ₂ and the control terminals 64 ₁ and 64 ₂ are arranged in the same connection form only on the output terminal side without being limited to the embodiment illustrated in FIG. The same inductor and control terminal may be arranged in the same connection form on the child side. Further, without being limited to the embodiments illustrated in FIG. 7, the resistor _{47 1,} 47 _2, 47 3, of 47 ₄ and a control terminal ₆₄ 1 to 64 _4, which input terminal side or output terminal side Either of the resistors and the control terminal may be omitted.

Furthermore, it may be in a form other than the capacitors ₇₂ 1, 72 _2. In this case, the baseband signal can be output after being level-shifted to an arbitrary DC level. If a positive voltage is applied to the control terminals 64 ₁ to 64 ₂ or the control terminals 64 ₁ to 64 ₄ , a signal having a positive DC offset voltage can be output, and if a negative voltage is applied, a negative DC offset voltage is output. It is possible to output a signal having Therefore, it is possible to output the input baseband signal with the DC offset voltage level-shifted to +0.5 V, −0.5 V or the like in accordance with the interface of the device connected to the subsequent stage.

[Fourth Embodiment]
FIG. 8 and FIG. 9 are diagrams showing a switch matrix according to the fourth embodiment of the present invention, which is a modified example of the second embodiment. The switch matrix of the present embodiment will be described focusing on the differences from the second embodiment.

In the embodiment shown in FIG. 8, the capacitor _{71 1,} 71 _2, 72 1, 72 ₂ by the most important features that they have galvanically separated input and output terminals and the SPDT switch. Here, the capacitors _{71 1,} 71 _2, 72 1, 72 ₂ of the capacitance value is set so that the impedance at the desired frequency is sufficiently small value.

  Therefore, by applying a voltage to the control terminal 63, even when a depletion (normally on) type FET having a negative threshold voltage (Vth) is used, the source / drain potential of the FET is raised. And positive power supply operation becomes possible. This makes it possible to apply MESFETs and HEMTs using compound semiconductors such as GaAs, which have the features of low ON resistance and low OFF capacity, to a switch matrix for positive power supply operation, and downsizing / high performance of the device Can be achieved.

Further, the capacitors _{71 1,} 71 _2, 72 1, 72 ₂ by the external, may be easily applied to large-capacity capacitor. As a result, a signal having a component close to a direct current can be passed without deterioration.

The main feature of the embodiment shown in FIG. 9 is that the input terminals and the SPDT switch are separated in a DC manner by the capacitors 71 ₁ and 71 ₂ . Here, the capacitance value of the capacitor 71 _1, 71 ₂ is set so that the impedance at the desired frequency is sufficiently small value.

  With such a configuration, the baseband signal can be level-shifted to an arbitrary DC level and output. If a positive voltage is applied to the control terminal 63, a signal having a positive DC offset voltage can be output, and if a negative voltage is applied, a signal having a negative DC offset voltage can be output. Therefore, it is possible to output the input baseband signal by shifting the level of the DC offset voltage to +0.5 V, −0.5 V or the like in accordance with the interface of the device connected to the subsequent stage.

Incidentally, FIG. 8, without being limited to the embodiments illustrated in FIG. 9, the SPDT switch ₉₂ 1, 92 ₂ resists side _{45 1,} 45 _2, 46 1, 46 ₂ and the control terminal 63 in the same connection type A configuration in which similar resistors and control terminals are arranged in the same connection form on both input and output SPDT switches may be used.

[Fifth Embodiment]
10 and 11 are diagrams showing a switch matrix according to the fifth embodiment of the present invention. In the figure, a symbol beginning with 10 represents a single-pole four-throw switch (hereinafter referred to as an SP4T switch). This switch matrix is a 4 × 4 switch matrix in the case of 4 in both the number of input and output terminals, respectively to the input and output terminals 11 through 14 and 21 through 24 with the SP4T switch ₁₀₁ 1 to 101 ₄ and ₁₀₂ 1 to 102 _4, These SP4T switches are connected by 16 interconnection transmission lines 51 _{1 to} 54 ₄ to operate as a switch matrix. Each SP4T switch series FET 31 ₁ to 38 DEG ₄ only, and is formed over the most important feature that it is connected between the SP4T switches ₁₀₁ 1 to 101 ₄ of the series FET by resistors ₄₁₁ 1-414 ₄ together And The resistance value of the resistor ₄₁₁ 1-414 ₄ is much higher than the characteristic impedance of the transmission line ₅₁ 1 to 54 ₄ are preferably set to the same resistance value. The gate bias control line and the control terminal are not shown.

  The operation of this switch matrix will be described with a focus on differences from the first and second embodiments.

10 and 11, the terminals on the transmission line side of the FETs in the SP4T switches 101 _{1 to} 101 ₄ on the input terminal side are mutually connected to resistors 411 _{1 to} 411 ₄ , 412 _{1 to} 412 ₄ , 413 _1. ˜413 ₄ , 414 _{1 to} 414 ₄ . Here, the SP4T switch in the switch matrix is controlled so that only one FET is ON and the other three FETs are OFF. Therefore, in the present embodiment, almost the same voltage as the input terminal is applied to the terminal on the transmission line side of the FET in the OFF path via the resistors 411 _{1 to} 411 ₄ . Therefore, all FETs in the OFF path can be normally pinched off, and deterioration of isolation characteristics can be prevented. Further, since the signal passing path is not connected to the ground, a baseband signal having an arbitrary DC level can be passed.

In the embodiment illustrated in FIG. 11, a control terminal 63 is further provided, and _one end of the control terminal 63 and resistors 411 _{1 to} 411 ₄ , 412 _{1 to} 412 ₄ , 413 _{1 to} 413 ₄ , 414 _{1 to} 414 ₄ are connected. Thus, the main feature is that a bias can be applied to the source or drain of the FET on the side connected to the transmission line independently of the drain or source on the input / output terminal side. As a result, when a signal including a DC component is allowed to pass, fluctuations in the DC level caused by the ON resistance value (Ron) of the FET can be suppressed. This is because a voltage drop generated when passing through the FET can be compensated by a bias from the control terminal 63.

Figure 12 is a diagram showing an embodiment of the SP4T switch 101 ₁ near the pattern layout in FIGS. 10 and 11.

In this embodiment, the resistor ₄₁₁ 1-411 ₄ approximately midway of the center conductor and the ground conductor of the transmission line ₅₁ 1 to 51 ₄ in which the coplanar line, and the longitudinal direction are arranged in parallel. By arranging in this way, the resistance values of the resistors 411 _{1 to} 411 ₄ can be increased without intersecting with the central conductor and the ground conductor, so that the switch matrix can be reduced in size / economic / performance. .

FIG. 13 is a diagram comparing the isolation characteristics of the prototype 4 × 4 switch matrix of this embodiment and the conventional 4 × 4 switch matrix. It has been demonstrated that the isolation characteristics can be significantly improved by applying the resistors 411 _{1 to} 414 ₄ .

The SP4T switches 102 _{1 to} 102 ₄ are not limited to the embodiments illustrated in FIGS. 10 and 11, and resistors 411 ₁ to 411 ₄ , 412 _{1 to} 412 ₄ , 413 _{1 to} 413 ₄ , 414 ₁ to 414 ₄ (the control terminal 63 in addition to these in the case of FIG. 11) may be arranged in the same connection form, and the same resistance (in addition to this in the case of FIG. 11) on both input and output SP4T switches side. The control terminals may be arranged in the same connection type. Further, the present invention is not limited to the embodiment illustrated in FIG. 12, and a microstrip line may be used instead of the coplanar line.

[Other embodiments]
The switch matrix is not limited to the 2 × 2 and 4 × 4 switch matrix exemplified in the present embodiment, but may be a switch matrix of any scale such as 3 × 3 or 8 × 8. Further, the form of connecting the capacitors illustrated in FIGS. 6 to 9 to the input / output terminals is not limited to the 2 × 2 switch matrix, but may be a 4 × 4 or other scale switch matrix.

  For example, the configuration excluding the control terminal 63 in the second embodiment is generalized as follows.

That is, n is an integer of 2 or more, n input terminals, n input-side single-pole n-throw switches (hereinafter referred to as SPnT switches), n ² transmission lines, and n output terminals And a switch matrix comprising n output-side SPnT switches,
Each of the input-side SPnT switch and the output-side SPnT switch includes n FETs, and one of drains or sources of the n FETs is connected to one common terminal, and the other is n switch terminals. The n input terminals are connected to the common terminals of the n input-side SPnT switches in a one-to-one relationship, and the n output terminals are connected to the n output-side SPnT switches. A switch terminal of the input-side SPnT switch and the output-side SPnT switch are connected to a common terminal in a one-to-one relationship so that signals can be transmitted from each of the input-side SPnT switches to each of the output-side SPnT switches. And the switch terminals of the n ² transmission lines are connected one-to-one, and
As a feature of the present invention, n switch terminals in each of the input side SPnT switches are connected one-to-one to n other ends of n resistors, one end of which is connected to one common conductor. Alternatively, n switch terminals in each of the output side SPnT switches are connected one-to-one to n other ends of n resistors, one end of which is connected to one common conductor. What is necessary is just composition.

In this case, in order to enable signal transmission from each of the n input-side SPnT switches to each of the n output-side SPnT switches, each input side uses n ² transmission lines. A signal may be transmitted from n switch terminals of the SPnT switch to different output side SPnT switches.

  In this case as well, as in the fifth embodiment, each resistor having one end connected to the common conductor may be arranged between the transmission lines and in parallel with the transmission line. As in the second embodiment, at least one control terminal may be connected to the common conductor. Similarly to the fourth embodiment, the n input terminals are connected via a capacitor. The n input side SPnT switches are connected to a common terminal in a one-to-one relationship, and the input terminals and the SPnT switch are separated in a DC manner, or the n output terminals are also connected to the n output side SPnTs via a capacitor. A configuration may be adopted in which the input / output terminals and the SPnT switch are separated in a direct current manner by being connected one-to-one to the common terminal in the switch.

  As described above in detail, the switch matrix according to the present invention has an SPnT switch using series FETs arranged at the input and output and connected to each other via the interconnection transmission line. The most important feature is that the terminals of the connected FETs are connected to each other by a resistor.

  For this reason, it is possible to achieve high isolation of a switch independent of control voltage polarity and signal DC logic level and compensation of DC level fluctuation, which contributes to miniaturization and high performance of Ethernet (registered trademark) switches and routers. However, it is big. Further, since positive power supply operation is possible, it is possible to contribute to miniaturization and high performance of the wireless communication terminal.

It is a figure which shows the circuit structure and equivalent circuit of a switch matrix concerning the 1st Embodiment of this invention. Is a diagram showing an embodiment of the SPDT switch 91 ₁ near the pattern layout in Fig. It is a figure which shows the circuit structure of the switch matrix concerning the 2nd Embodiment of this invention. Embodiments of the SPDT switch 91 ₁ near the pattern layout of FIG. 3 is a示図. It is the figure which compared the isolation characteristic of 2 * 2 switch matrix of 1st Embodiment, and 2 * 2 switch matrix of a prior art example. It is a figure which shows the circuit structure of the switch matrix concerning the 3rd Embodiment of this invention. It is a figure which shows the circuit structure of the switch matrix concerning the 3rd Embodiment of this invention. It is a figure which shows the circuit structure of the switch matrix concerning the 4th Embodiment of this invention. It is a figure which shows the circuit structure of the switch matrix concerning the 4th Embodiment of this invention. It is a figure which shows the circuit structure of the switch matrix concerning the 5th Embodiment of this invention. It is a figure which shows the circuit structure of the switch matrix concerning the 5th Embodiment of this invention. Is a diagram showing an embodiment of the SP4T switch 101 ₁ near the pattern layout in FIGS. 10 and 11. It is the figure which compared the isolation characteristic of 4x4 switch matrix of 5th Embodiment, and 4x4 switch matrix of a prior art example. It is a figure which shows the circuit structure of the conventional switch matrix. It is a figure which shows the circuit structure and equivalent circuit of the conventional switch matrix.

Explanation of symbols

A code starting with 1 (excluding a code starting with 10) represents an input terminal,
A code starting with 2 represents an output terminal,
Symbols beginning with 3 represent field effect transistors (FETs),
The sign starting with 4 represents resistance,
A code starting with 5 represents a transmission line,
A code starting with 6 represents a control terminal,
A code starting with 7 represents a capacitor,
A code starting with 8 represents an inductor,
Symbols beginning with 9 represent single pole double throw switches (SPDT switches)
A symbol starting with 10 represents a single pole four throw switch (SD4T switch).

Claims (13)

Two input terminals, two input-side single-pole double-throw switches, four transmission lines, two output terminals, and two output-side single-pole double-throw switches,
Each of the input-side single-pole double-throw switch and the output-side single-pole double-throw switch includes two field effect transistors, and one of the drains or sources of the two field effect transistors has one common terminal. And the other is connected to the two switch terminals on a one-to-one basis,
The two input terminals are connected one-to-one to a common terminal in the two input-side single-pole double-throw switches,
The two output terminals are connected one-to-one to a common terminal in the two output-side single-pole double-throw switches,
A switch terminal of the input side single pole double throw switch and the output side single pole double throw switch are configured so that signal transmission from each of the input side single pole double throw switches to each of the output side single pole double throw switches is possible. In the switch matrix in which the four transmission lines are connected one-to-one with the switch terminals of the throw switch,
The two switch terminals in each of the input-side single-pole double-throw switches are connected by resistors, or the two switch terminals in each of the output-side single-pole double-throw switches are connected by resistors. A switch matrix characterized by that. The switch matrix of claim 1, wherein
The switch matrix, wherein the resistor is bent between the field effect transistors or between the transmission lines. The switch matrix according to claim 1 or 2,
The common terminal of the two input side single pole double throw switches is connected to the control terminal via an inductor, or the common terminal of the output side single pole double throw switch is connected to the control terminal via an inductor. A switch matrix characterized by that. The switch matrix according to claim 1 or 2,
The common terminal of the two input side single pole double throw switches is connected to the control terminal via a resistor, or the common terminal of the output side single pole double throw switch is connected to the control terminal via a resistor. A switch matrix characterized by that. The switch matrix according to claim 3 or 4,
The switch matrix characterized in that the two input terminals are connected to a common terminal in the two input-side single-pole double-throw switches through a capacitor in a one-to-one relationship. The switch matrix of claim 5,
The switch matrix, wherein the two output terminals are connected one-to-one to a common terminal in the two output-side single-pole double-throw switches through a capacitor. When n is an integer of 2 or more, n input terminals, n input-side single-pole n-throw switches, n ² transmission lines, n output terminals, and n output-side singles A pole n throw switch,
Each of the input-side single-pole n-throw switch and the output-side single-pole n-throw switch includes n field effect transistors, and one of the drains or sources of the n field effect transistors is a common terminal. And the other is connected to the n switch terminals on a one-to-one basis,
The n input terminals are connected one-to-one to a common terminal in the n input side single pole n throw switches,
The n output terminals are connected one-to-one to a common terminal in the n output-side single-pole n-throw switches,
A switch terminal of the input-side single-pole n-throw switch and the output-side single-pole n so that signal transmission from each of the input-side single-pole n-throw switches to each of the output-side single-pole n-throw switches is possible. In a switch matrix in which the n ² transmission lines are connected one-to-one with the switch terminal of the throw switch,
N switch terminals in each of the input-side single-pole n-throw switches are connected one-to-one to n other ends of n resistors, one end of which is connected to one common conductor; Alternatively, n switch terminals in each of the output-side single-pole n-throw switches are connected one-to-one to n other ends of n resistors, one end of which is connected to one common conductor. A switch matrix characterized by that. The switch matrix of claim 7,
A switch matrix, wherein a resistor having one end connected to the common conductor is disposed between the transmission lines and in parallel with the transmission lines. The switch matrix according to claim 7 or 8,
A switch matrix, wherein at least one control terminal is connected to the common conductor. Switch matrix according to claim 7, 8 or 9,
A common terminal of the n input-side single-pole n-throw switches is connected to a control terminal via an inductor, or a common terminal of the output-side single-pole n-throw switch is connected to a control terminal via an inductor. A switch matrix characterized by that. Switch matrix according to claim 7, 8 or 9,
A common terminal of the n input-side single-pole n-throw switches is connected to a control terminal via a resistor, or a common terminal of the output-side single-pole n-throw switch is connected to a control terminal via a resistor. A switch matrix characterized by that. Switch matrix according to claim 9, 10 or 11,
The switch matrix, wherein the n input terminals are connected to common terminals of the n input side single-pole n-throw switches through a capacitor in a one-to-one relationship. The switch matrix of claim 12,
The switch matrix, wherein the n output terminals are connected to a common terminal of the n output-side single-pole n-throw switches through a capacitor in a one-to-one relationship.

Images