JP4071201B2 - Switch matrix - Google Patents

Description

  The present invention relates to a multi-input multi-output switch matrix that switches an input signal to an arbitrary output for output, and relates to a high-frequency switch that can switch a signal of approximately several GHz or several Gbit / s or more.

  FIG. 8 and FIG. 9 are diagrams showing a circuit configuration of a conventional switch matrix disclosed in Patent Document 1 and Non-Patent Document 1 below. FIG. 8 shows a 2 × 2 switch when both the number of input terminals and the number of output terminals are two, and FIG. 9 shows a 4 × 4 switch when both the number of input terminals and the number of output terminals are four. These switches have 1 input, 2 output, 2 input, 1 output or 1 input, 4 output, 4 input, 1 output switch for each input terminal and output terminal, and 4 or 16 interconnections between these switch output terminals. It is configured by connecting with a transmission line for use.

The operation of this switch matrix will be described with reference to the 2 × 2 switch in FIG. Signal input from the first input terminal 1 ₁ is input to the first one-input two-output switch 3 ₁ via the transmission line 10 ₁ for the first input. Selecting whether to output the first 1 Input 2 Output switch 3 ₁ the first transmission line 71 ₁ and the second either a signal interconnection transmission line ₈₁ for interconnection at.

If the path of the first to the interconnection transmission lines 71 ₁ is selected, the first two inputs and one output switch 4 ₁ selects the path from the transmission line 71 ₁ for the first interconnection, first A signal is output to the _first output terminal 21 via the output transmission line 10 ₉ of ₁ . Also, when the path of the second to the interconnection transmission line ₈₁ is selected, the second 2-input 1-output switch 4 ₂ Select a path from the transmission line ₈₁ for the second interconnection A signal is output to the _second output terminal 22 via the second output transmission line 10 ₁₀ .

Meanwhile, the signal input from the second input terminal 1 ₂ is input a second to 1 input 2 output switch 3 ₂ via the second input transmission line 10 _2. Here, in the second 1 input 2 output switch 3 _2, selects whether to output the signal to either the first interconnection transmission lines ₇₁₂ or the second interconnection transmission line _82. If the path to the first interconnection transmission lines ₇₁₂ is selected, the second 2-input 1-output switch 4 ₂ Select a path from the transmission line 71 ₂ for the first interconnection, first A signal is output to the _second output terminal 22 through the second output transmission line 10 ₁₀ . Also, when the path of the second to the interconnection transmission line ₈₂ is selected, the first two inputs and one output switch 4 ₁ selects the path from the transmission line 8 ₂ for the second interconnection , and it outputs a signal to the first output terminal 2 ₁ via the first output transmission line _109.

Here, the switching operation of the first and second 1-input 2-output switches 3 ₁ , 3 ₂ and the first and second 2-input 1-output switches 4 ₁ , 4 ₂ is performed by supplying a control signal from the control terminal 6. It implement _| achieves by inputting via the control lines _51-4 and _55-5 , respectively.
The operation of the switch matrix when the number of input terminals and the number of output terminals are both 3 or more is the same as described above. FIG. 9 shows the case where the number of input terminals and the number of output terminals are both 4, and the first to fourth input terminals 1 ₁ to 1 ₄ , the _first to _fourth input transmission lines 10 ₁ to 10 ₄ , 1st to 4th 1 input 4 output switches 11 _{1 to} 11 ₄ , 1st to 16th interconnection transmission lines 77 _{1 to} 77 ₁₆ , 1st to 4th 4 input 1 output switches 12 _{1 to} 12 ₄ , first to fourth output transmission line ₁₀₅ to _8, and an output terminal 21 _{to 24} of the first to fourth. Note that the control line and the control terminal are not shown.
These conventional switch matrices have the following problems.

  First, there is a problem that it is difficult to achieve both reduction in insertion loss / high isolation and circuit miniaturization. This is due to the fact that a finite length is required for the interconnection transmission line, and there is a considerable increase in insertion loss due to this finite length. When the transmission line is constituted by a coplanar line, for example, it is necessary to widen the center conductor width and the gap between the center conductor and the ground conductor in order to reduce the insertion loss. This is because the characteristic impedance of the coplanar line is almost uniquely determined by the ratio between the center conductor width and the gap interval.

  On the other hand, the switch matrix is also required to have high isolation characteristics between the paths. Here, the isolation between the coplanar lines increases as the inter-line ground width increases. Therefore, in order to realize low loss and high isolation characteristics, it is necessary to widen both the center conductor width and the ground width. As a result, in a switch matrix in which transmission lines are arranged at high density, The length of each connection path is unavoidable, and the effect of reducing the insertion loss by increasing the width of the center conductor is canceled out.

  This also means an increase in the size of the circuit. In particular, when the switch matrix is to be integrated on the semiconductor substrate, the increase in the size of the circuit causes an increase in cost. If the number of input terminals and the number of output terminals are both n, the number of connection paths requires the square of n, so these problems become more prominent as the scale of the switch increases. In the switch matrix having a scale of 4 × 4 or more shown in FIG. 9, this is a very big problem.

Second, it is difficult to make the insertion loss between the paths uniform. In the 2 × 2 switch shown in FIG. 8, the second interconnection transmission lines 8 ₁ and 8 ₂ are longer than the _first interconnection transmission lines 71 ₁ and 71 ₂ . Therefore, the path using the second interconnection transmission line has a larger insertion loss. In order to avoid this, there is no choice but to lengthen the first transmission line for transmission, and as a result, there is no choice but to align the characteristics with a path with a large insertion loss.

Furthermore, this problem becomes significant with 4 × 4 switches. In other words, the transmission line (77 ₁ , 77 ₆ , 77 ₁₁ , 77 _{16 in} FIG. 9) and the longest transmission line (77 ₄ , 77 _{13 in} FIG. 9) connecting the switches facing each other in the shortest are approximately 1. Nine times as long. In order to align the lengths of the 16 transmission lines, for example, all 14 transmission lines other than the longest transmission line (77 ₄ , 77 ₁₃ ) in FIG. In addition to incurring a further increase in circuit size, the result is that the characteristic must be aligned with a path with a large insertion loss as in the case of the 2 × 2 switch. This becomes a problem as the scale of the switch increases.

Thirdly, as the number of input terminals and output terminals increases, the number of intersections between connection paths increases and the isolation characteristics deteriorate. In the 2 × 2 switch, there is only one wiring intersection 9 of the _second interconnection transmission lines 8 ₁ and 8 ₂ shown in FIG. 8, but in the 4 × 4 switch matrix shown in FIG. pieces wiring intersections of even ₍₉₁ to _{93 36)} will be present. As the switch becomes more similar to this, the number of wiring intersections increases, leading to degradation of isolation characteristics.

Fourth, the isolation characteristic is deteriorated due to an increase in switch control lines. Also in the case of the 2 × 2 switch shown in FIG. 8, for example, when two control lines are required for each switch, a total of eight control lines (5 _{1 to} 5 ₈ ) are required. it is inevitable to intersect the input transmission line 10 ₂ and the output transmission line 10 _10, the isolation characteristics deteriorate this intersection. As described above, this deterioration becomes more prominent in a configuration that requires switches for both input and output, and becomes more problematic as the switch scale increases.

  Fifth, when the switch is formed of a cold FET, an FET having a double required gate width is required, and the circuit is enlarged accordingly. A cold FET is a switch that switches between passing (ON) and blocking (OFF) by setting the source / drain of the FET to the same potential and controlling the gate voltage. The loss at this ON is determined by the on resistance of the FET. Is done. In the configuration in which switches are arranged for both input and output as in the conventional example shown in FIGS. 8 and 9, the on resistance values of both the input and output switches are effective. Therefore, the on resistance value allowed for each switch is ½ of the required value determined from the insertion loss. Since the on resistance is inversely proportional to the gate width of the FET, an FET having a double gate width is required, resulting in an increase in circuit size. In addition, since the FET having a double gate width has a double off capacitance, there is a problem in that the reflection loss is deteriorated.

The above-mentioned problems of the prior art are caused by the fact that n 1-input n-output / n-input 1-output switches are arranged for both input and output, respectively. This is because n ² transmission lines are required.

JP-A-8-213472 H.J.Schindleret al.IEEE Trans.Microwave Theory and Techniques Vol.36, No.12 December (1988) p.1604

  An object of the present invention is to solve the above-described conventional problems, and to provide a switch matrix that has little variation in loss between paths, and that is easy to increase in scale with low loss / high isolation.

In order to achieve the above object, the switch matrix according to claim 1 includes a first and second one-input two-output switch or two-input one-output switch, first and second input terminals, and first and second outputs. A terminal, two first connection paths, and two second connection paths, the outputs of the first and second one-input two-output switches or the inputs of the first and second two-input one-output switches were placed face to face at a predetermined interval, the two first connection paths the first and the output or between the first second 1 input 2 output switch of the second 2-input 1-output switch Inputs are connected to each other, and one end of each of the two second connection paths is connected to the first and second output terminals or the first and second input terminals, and the other end is connected to the two second connection paths. are respectively connected to one of the connection path, said second connection via One is made to intersect with the first connection path to which the connection path is not connected, 1/36 or less of the transmission line in a wavelength length of the two first connection paths at the desired operating frequency of the It comprised so that it might become.

  The switch matrix according to claim 2 is the switch matrix according to claim 1, wherein the one-input two-output switch or the two-input one-output switch includes at least two FETs that are turned on and off by a gate voltage between the source and the drain. Used to configure.

Switch matrix according to claim 3 is, n pieces of 1 input n-output switch (n is an even number of 4 or more) and n ^2/2 pieces of the third connection path and n of the fourth individual connection paths and the n An input terminal and n output terminals are provided. The n one-input n-output switches are divided into two groups of n / 2 pieces, and the output sides of the two groups of one-input n-output switches face each other at a predetermined interval. N / 2 switch pairs are formed, the n input terminals are respectively connected to the inputs of the n 1-input n-output switches, and the output side is arranged facing each other. the outputs of the n / 2 pieces of switch pairs connected respectively by the n ^2/2 pieces of the third connection path, one end of said n fourth connection path is connected to each of the n output terminals among the other end of the ⁿ 2/2 pieces of the third connection path, Serial has a structure which is connected one by one point from the connection path for n / 2 pieces of each pair of switches.

The switch matrix according to claim 4 is the switch matrix according to claim 3 , wherein n n-input 1-output switches are used instead of n 1-input n-output switches, and the two divided groups are divided. The input side of the n-input 1-output switch is arranged to face each other at a predetermined interval to form n / 2 switch pairs, and the inputs of the n / 2 switch pairs in which the input sides are arranged face-to-face wherein n ^2/2 pieces of third respectively connected with the connection path, the n output terminals, the connected n pieces of n input 1 to the output of the output switch, the n fourth connection path 1 end connected respectively to said n input terminals, among the other end of the n ^2/2 pieces of the third connection path, one location at a time connection from the connection path for each switch pair of said n / 2 I have configured to .

The switch matrix according to claim 5 is the switch matrix according to claim 3 or claim 4 , wherein the 1-input n-output switch or the n-input 1-output switch is turned on / off between a source and a drain by a gate voltage. The above FET was used.

Switch matrix according to claim 6, in the switch matrix according to any one of claims 1 to 5, wherein each switch and forms shapes on the same semiconductor substrate connection paths and the input and output terminals.

  The switch matrix according to the present invention has a switch on either one of the input and output sides, arranges a pair of switches arranged in parallel with each other facing the output side at a predetermined interval, and arranges an interconnection transmission line at this predetermined interval. This is the main feature.

For this reason, compared to the prior art with switches on both input and output,
1) Half the required number of switches,
2) Half the required switch control line,
3) Reduction of the number of transmission lines for interconnection and shortening of the length of transmission lines for interconnection,
4) Reduction of circuit size for interconnection,
5) Reduction of intersections of interconnection transmission lines,
6) Half the required gate width (when using a cold FET switch),
It is possible to achieve low switching matrix loss, reduced path dependency of insertion loss, high isolation, downsizing, increase in the number of inputs and outputs (upscaling), wide bandwidth and economy. it can.

  Therefore, it greatly contributes to the miniaturization and high performance of RF switches for wireless communication systems, 1 Gbit / s or 10 Gbit / s Ethernet (registered trademark) switches or routers.

[First Embodiment]
FIG. 1 is a diagram showing a switch matrix according to the first embodiment of the present invention. The switch matrix includes first and second input terminals 1 ₁ , 1 ₂ , first and second input transmission lines 10 ₁ , 10 ₂ , first and second 1-input 2-output switches 3 ₁ , 3. ₂ , first interconnection transmission lines 71 ₁ , 71 ₂ , second interconnection transmission lines 8 ₁ , 8 ₂ , first and second output transmission lines 10 ₉ , 10 ₁₀ , and first and It consists of second output terminals 2 ₁ , 2 ₂ . 1, a second transmission line ₈₁ for interconnection and 8 ₂ are crossed by the wiring intersection portion 9 in the overlay structure. The difference from the conventional example shown in FIG. 8 is that a 2-input 1-output switch is not arranged on the output side, a 1-input 2-output switch is arranged only on the input side, and the required number of switches is reduced by half. That is, the transmission line is made shorter and equal in length to each other.

The switch matrix operation in the first embodiment is as follows. Signal input from the first input terminal 1 ₁ is input to the first one-input two-output switch 3 ₁ via the transmission line 10 ₁ for the first input, connection of the first to the output terminal 2 ₁ first interconnection transmission lines 71 ₁ or the path, or output the second to interconnection transmission lines 8 ₁ is a connection path of the second to the output terminal 2 _2.

Meanwhile, the signal input from the second input terminal 1 _2, the second through the input transmission line 10 ₂ is inputted second to 1 input 2 output switch 3 _2, first to the output terminal 2 ₁ the output of the second interconnection transmission line ₈₂ or a connection path, or the transmission line 71 ₂ for the second interconnection is a connection path of the second to the output terminal 2 _2. That is, the interconnection transmission lines 71 ₁ and 8 ₂ , and 71 ₂ and 8 ₁ constitute a two-input one-output combining unit.

Here, when the operation of the 2 × 2 switch matrix is considered, (connection from the input terminal 1 ₁ to the output terminal 2 ₁ ; connection from the input terminal 1 ₂ to the output terminal 2 ₂ ) or (from the input terminal 1 ₁ It will take the two states: connection) from the input terminal 1 ₂ to the output terminal 2 _1; connected to the output terminal 2 _2. In the former case, the switch connection ends of the second interconnection transmission lines 8 ₁ , 8 ₂ are in an open (open) state, and in the latter case, the switch connection ends of the first interconnection transmission lines 71 ₁ , 71 ₂ Is in an open state, and the length of these interconnection transmission lines is not negligible compared to the wavelength of the operating frequency band, resulting in deterioration of switch characteristics as an open stub.

  This situation is simulated in FIG. The horizontal axis shows the transmission line length for interconnection (ratio to one wavelength in the transmission line), and the vertical axis shows the amount of insertion loss degradation, reflection loss, and isolation when the transmission line length for interconnection is zero. Plotting. From this figure, it can be seen that as the transmission line for the interconnection becomes longer, the influence of the open stub appears gradually, the insertion loss increases, and the reflection loss decreases. On the other hand, isolation is improved by turning over the reduction in reflection loss. For example, when the length of the transmission line for interconnection is set to 1/36 or less of the wavelength within the transmission line, the deterioration of reflection loss can be suppressed to 3.5 dB and the deterioration of insertion loss can be suppressed to 0.12 dB or less. This can be easily realized as a transmission line for interconnection on a semiconductor substrate such as GaAs in a frequency range of 10 GHz or less.

Here, it can be seen that the length of the interconnection transmission line in the embodiment of FIG. 1 is shorter than that of the conventional example and is equal to each other. Therefore, the insertion loss can be reduced as compared with the conventional example, and the insertion loss for each path can be made uniform. Furthermore, when the switch is configured by, for example, a cold FET, the required gate width can be halved as compared with the configuration in which the switch is arranged for both the input and output of the conventional example shown in FIG. Along with the shortening of the line length, the circuit area can be greatly reduced.
Furthermore, since the number of required switches can be halved, the number of control lines can be halved, and crossing with a transmission line as a signal line can be avoided, so that deterioration of isolation characteristics due to this can be avoided.
It should be noted that the input terminal and the output terminal are switched, the 1-input 2-output switch is replaced with a 2-input 1-output switch, and 2 input 1 configured by 2 connection paths among the 4 connection paths. The output combining means may be configured as 1-input 2-output distribution means, and the remaining two connection paths may be configured as the other 1-input 2-output distribution means.

[Second Embodiment]
FIG. 3 is a diagram showing a switch matrix according to the second embodiment of the present invention. The switch matrix includes first and second input terminals 1 ₁ , 1 ₂ , first and second input transmission lines 10 ₁ , 10 ₂ , first and second 1-input 2-output switches 3 ₁ , 3. ₂ , interconnection transmission lines 7 ₁ , 7 ₂ , 7 ₃ , 7 ₄ , first and second output transmission lines 10 ₉ , 10 ₁₀ , 10 ₁₀ ′, and first and second output terminals 2 ₁ 2 and ₂ .

  The embodiment of the present switch matrix will be described focusing on the differences from the first embodiment. The most important difference from the first embodiment is that the output sides of the 1-input 2-output switch are arranged facing each other.

In the switch matrix of the present embodiment, the output sides of the first and second 1-input 2-output switches 3 ₁ , 3 ₂ are arranged facing each other at a predetermined interval, and the outputs are connected to the interconnection transmission line 7. ₁ and 7 _2, and most important feature that is directly connected to the shortest respectively the interconnection transmission line 7 ₃ and 7 _4. The output terminals 2 ₁ and 2 ₂ are connected to the output transmission line 10 ₉ between the interconnection transmission lines 7 ₁ and 7 ₂ and the output transmission line 10 ₁₀ ′ to the interconnection transmission line 7. _3, 7 are realized by each connected between _4.

Here, the interconnection transmission line including the output transmission line 10 ₁₀ ′ is arranged extremely compactly between two one-input two-output switches, so the connection length thereof is compared with that of the first embodiment. And can be shortened. For example, when a coplanar line having a line width of about 10 μm is used, it can be laid out in an area of about 100 μm square or less. Therefore, the influence of the open stub in the OFF path can be alleviated and the insertion loss can be reduced, so that even higher frequency operation is achieved. Although there is variation in insertion loss between paths due to the presence of the output transmission line 10 ₁₀ ′, the length of 10 ₁₀ ′ can be reduced to about 50 μm or less, which causes little problem.

FIG. 4 is a diagram showing a modification of the present embodiment. In the embodiment shown in Figure 4 extends the input transmission line 10 ₁ and 10 _2, it is made possible to collect input terminals 1 ₁ and 1 ₂ on one side. Here, it is possible to this input transmission line 10 ₁ and 10 ₂ of the line width in comparison with the transmission line 7 _{1-7 4} for interconnection by utilizing the fact that can significantly wide, routing the transmission line with low loss It has become. Therefore, it is possible to provide a very effective means when it is necessary to mount the input and output so as to be taken out from each other.

  As described above, the input terminal and the output terminal may be interchanged, and the 1-input 2-output switch may be replaced with a 2-input 1-output switch.

[Third Embodiment]
FIG. 5 is a diagram showing a switch matrix according to the third embodiment of the present invention. This matrix switch includes _first to _fourth input terminals 1 ₁ to 1 ₄ , first to fourth input transmission lines 10 ₁ to 10 ₄ , and first to fourth 1-input and 4-output switches 11 _{1 to} 11. ₄ , 1st to 16th first interconnection transmission lines 7 _{1 to} 7 ₁₆ , 1st to 6th second interconnection transmission lines 8 ₁ to 8 ₆ , and 1st to 4th outputs The transmission lines 10 ₅ to 10 ₈ and the first to fourth output terminals 2 ₁ to 2 ₄ are configured to operate as a four-input four-output (4 × 4) switch matrix.

  The main difference between the present embodiment and the conventional example shown in FIG. 9 is that a 1-input 4-output switch is arranged only in the input section and the outputs are arranged to face each other. This makes it possible to halve the required number of switches, reduce the number of interconnection transmission lines, shorten the length of interconnection transmission lines, and reduce wiring intersections. Lower switch matrix loss and path dependence of insertion loss Reduction, high isolation and downsizing. In addition, when a cold FET is used for the switch, the required gate width can be halved, which is effective in further downsizing the circuit.

In the switch matrix according to the present embodiment, the outputs of the 1-input 4-output switch pairs (11 ₁ , 11 ₄ ) and (11 ₂ , 11 ₃ ) arranged with their output sides facing each other are connected to each other as a first interconnection. 8 transmission lines (7 ₁ and 7 ₂ ), (7 ₃ and 7 ₄ ), (7 ₅ and 7 ₆ ), (7 ₇ and 7 ₈ ), (7 ₉ and 7 ₁₀ ), (7 ₁₁ and 7 ₁₂ ), (7 ₁₃ and 7 ₁₄ ), and (7 ₁₅ and 7 ₁₆ ).

Connection to the output terminal _{2 1,} the first interconnection transmission line _{71, 7 2} between and _{7 9, 7} second interconnection transmission line ₈₁ to the output transmission line which connects between ₁₀ 10 ₅ This is realized by connecting Connection to the output terminal _{2 2,} a first interconnection transmission line ₇ 3, _{7 4} between and _{7 11, 7 12} connects the second interconnection transmission line ₈₂ connected to the transmission line 8 ₅ through realized by connecting the output transmission line _106. Connection to the output terminal _{2 3,} the first interconnection transmission line ₇ 5, _{7 6} between a _{7 13, 7} connecting the ₁₄ second transmission line connected to the interconnection transmission line _{8 3} 8 ₆ through realized by connecting the output transmission line _107. Connection to the output terminal _{2 4,} the first interconnection transmission line ₇ 7 _{7 8} between a _{7 15, 7 16} second interconnection transmission line _{8 4} to the output transmission line which connects between 10 ₈ This is realized by connecting

Here, the number of interconnection transmission lines is reduced from 16 in the conventional example to 12, and the number of wiring intersections 9 is 14 (as shown in FIG. 5 from the conventional 36 shown in FIG. 9 _{1 to} 9 ₁₄ ), showing a dramatic decrease to less than half. Although not shown, the number of switch control lines can be halved, and the number of intersections between these control lines and signal lines can be halved. Due to the above two effects, the isolation characteristics of the switch can be significantly improved as compared with the conventional example.

  Furthermore, since the first and second interconnection transmission lines are compactly arranged between two 1-input 4-output switch pairs, the connection length is compared with that of the conventional embodiment shown in FIG. Can be significantly shortened. 5 and 9 show the transmission lines with the same line width and line spacing, and the lengths and sizes can be directly compared as they are, but when the transmission line lengths for the interconnections of the longest paths are compared It can be seen that it can be shortened to about 1/4. The circuit size of the interconnection part can also be reduced to 1/10 or less.

  For example, when a coplanar line having a line width of about 10 μm is used, the interconnection portion can be laid out in an area of only about 300 μm square. Therefore, it is possible to greatly reduce the insertion loss due to the high-density interconnection transmission line and to greatly suppress the variation in the insertion loss between the paths. Further, when a cold FET is used for the switch, the required gate width can be halved, so that the circuit can be further miniaturized.

  The input terminal and the output terminal may be interchanged, and the 1-input 4-output switch may be replaced with a 4-input 1-output switch.

[Other embodiments]
6 and 7 are diagrams showing a switch matrix of a modified example of the third embodiment of the present invention. In the embodiment shown in FIGS. 6 and 7, the first to fourth output terminals 2 ₁ to 2 ₄ and the _first to _fourth output transmission lines 10 ₅ to 10 ₈ are gathered on one side. Has the most main features. It moves to the third transmission line 8 _5, 8 ₆ the output terminals of the switch matrix of embodiment shown in FIG. 5, is achieved by newly adding the transmission line 8 _7. Along with this, the number of wiring intersections increases by four, but the output terminal can be taken out from one direction, and when it is implemented as an apparatus, the input / output pin arrangement can be easily made in one direction. effective. In the embodiment shown in Figure 7 allowing the further stretching the input transmission line 10 ₁ to 10 _4, collecting input terminals 1 ₁ to 1 ₄ on one side. Here, an increase in insertion loss due to the extension of the input transmission lines 10 ₁ to 10 ₄ hardly causes a problem. This is due to the fact that the transmission line can be routed with low loss by utilizing the fact that the line width of the input transmission line can be significantly wider than that of the interconnection transmission line. Therefore, it is possible to provide a very effective means when it is necessary to mount the input and the output so as to face each other.
The input terminal and the output terminal may be interchanged, and the 1-input 4-output switch may be replaced with a 4-input 1-output switch.

The circuit block diagram which shows 1st Embodiment. The characteristic view by simulation of the circuit of FIG. The circuit block diagram which shows 2nd Embodiment. The circuit block diagram which shows the modification of 2nd Embodiment. The circuit block diagram which shows 3rd Embodiment. The circuit block diagram which shows the 1st modification of 3rd Embodiment. The circuit block diagram which shows the 2nd modification of 3rd Embodiment. The circuit block diagram of the switch matrix which shows a 1st prior art example. The circuit block diagram of the switch matrix which shows a 2nd prior art example.

Explanation of symbols

1 ₁ to 1 ₄ : input terminal,
2 _{1 to} 2 ₄ : output terminals,
3 _{1 to} 3 ₂ : 1 input 2 output switch,
4 ₁ to 4 ₂ : 2 input 1 output switch,
5 _1-8 : control line,
6: Control terminal,
7 _{1 to} 7 ₁₆ : first interconnection transmission line,
71 _{1 to} 71 ₂ : transmission line for first interconnection,
77 _{1 to} 77 ₁₆ : first interconnection transmission line,
8 ₁ to 8 ₇ : transmission line for second interconnection,
9, 9 _{1 to} 9 ₃₆ : wiring intersection,
10 ₁ to 10 ₄ : transmission line for input,
10 ₅ to 10 ₁₀ ′: output transmission line,
11 _{1 to} 11 ₄ : 1 input 4 output switch,
12 _{1 to} 12 ₄ : 4 input 1 output switch

Claims (6)

1st and 2nd 1 input 2 output switch or 2 input 1 output switch, 1st and 2nd input terminal, 1st and 2nd output terminal, 2 1st connection path, and 2nd 2nd With a connection path of
The outputs of the first and second 1-input 2-output switches or the inputs of the first and second 2-input 1-output switches are arranged facing each other at a predetermined interval,
The two first connection paths the first and second 1 input 2 outputs of the output switches or the first and the input ends of the second 2-input 1-output switch connected respectively,
One end of each of the two second connection paths is connected to the first and second output terminals or the first and second input terminals, and the other end is connected to each of the two first connection paths. And
One of the second connection paths intersects the first connection path to which the connection path is not connected,
The switch matrix, wherein the length of the two first connection paths is 1/36 or less of the wavelength in the transmission line at a desired operating frequency. The switch matrix of claim 1 , wherein
The switch matrix, wherein the one-input two-output switch or the two-input one-output switch is configured by using at least two or more FETs that are turned on and off by a gate voltage between the source and drain. n 1-input n-output switch (n is an even number of 4 or more) of the n ^2/2 pieces of the third connection path and the n fourth connection path n input terminals and n output terminals Prepared,
The n 1-input n-output switches are divided into 2 groups each of n / 2, and the output sides of these 2 groups of 1-input n-output switches are arranged facing each other at a predetermined interval. Form a switch pair,
The n input terminals are connected to inputs of the n 1-input n-output switches, respectively.
The output side is connected to the outputs of the arranged n / 2 pieces of switch pairs oppositely in the n ^2/2 pieces of the third connection path,
One end of the n fourth connection path is connected to each of the n output terminals, among the other end of the n ^2/2 pieces of the third connection path, said n / 2 pieces of each pair of switches A switch matrix characterized in that one connection point is connected from each connection path. The switch matrix of claim 3 ,
Instead of n 1-input n-output switches, n n-input 1-output switches are used,
N / 2 switch pairs are formed by arranging the input sides of the two divided n-input 1-output switches facing each other at a predetermined interval;
Are respectively connected to input ends of arranged n / 2 pieces of switch pairs the input side to the opposed by the n ^2/2 pieces of the third connection path,
The n output terminals are respectively connected to outputs of the n n input 1 output switches,
Wherein one end of the n fourth connection path is connected respectively to said n input terminals, among the other end of the n ^2/2 pieces of the third connection path, each switch pair of said n / 2 A switch matrix characterized in that one connection point is connected from each connection path. The switch matrix according to claim 3 or claim 4 ,
The switch matrix, wherein the 1-input n-output switch or the n-input 1-output switch is configured by using at least n or more FETs that are turned on and off by a gate voltage between the source and the drain. The switch matrix according to any one of claims 1 to 5 ,
A switch matrix characterized in that the switches, connection paths, input terminals, and output terminals are formed on the same semiconductor substrate.

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