JP4019859B2 - Manufacturing method of ceramic electronic component - Google Patents

Manufacturing method of ceramic electronic component Download PDF

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JP4019859B2
JP4019859B2 JP2002245677A JP2002245677A JP4019859B2 JP 4019859 B2 JP4019859 B2 JP 4019859B2 JP 2002245677 A JP2002245677 A JP 2002245677A JP 2002245677 A JP2002245677 A JP 2002245677A JP 4019859 B2 JP4019859 B2 JP 4019859B2
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mother substrate
electronic component
temperature
ceramic electronic
multilayer ceramic
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JP2004087716A (en
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教真 朝倉
晋一郎 内藤
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Description

【0001】
【発明の属する技術分野】
この発明は、積層セラミックコンデンサのような積層セラミック電子部品の製造方法に関するものである。
【0002】
【従来の技術】
通常、積層セラミック電子部品の製造に際しては、まず複数の積層体が配列形成されたマザー基板を形成することで複数の積層体を同時に形成し、その後マザー基板を個々の積層体に切断してから焼成する方法が採られている。
【0003】
例えば、積層セラミックコンデンサの場合、図4(a)のフローチャートに示す工程で製造される。まず、導電ペーストをマトリクス状に塗布した複数枚のセラミックグリーンシートを積層して、所定の圧力でプレスすることでマザー基板を形成する(s101)。次に、マザー基板を個々の積層セラミックコンデンサ単位の積層体に切り出す(s102)。切り出された複数の積層体を熱処理することで、セラミックグリーンシートおよび導電ペーストに含まれる可塑剤やバインダ等の不純物を燃焼させて脱バインダを行う(s103)。次に、積層体を焼成することによりセラミックグリーンシートが誘電体層となり、導電ペーストパターンが内部電極となったセラミック焼結体を形成する(s104)。このセラミック焼結体の内部電極が露出している面を含む外面に外部電極用導電ペーストを塗布し、該導電ペーストを焼結することで外部電極を形成する(s105)。
【0004】
また、切断後の積層体の付着を防止するために、脱バインダ工程(s103)の前に乾燥を行うことが特開平6−310365号公報に開示されている。この製造方法は、マザー基板から複数の積層体を切り出した後に、所定の温度と時間で乾燥を行うものであり、図4(b)のフローチャートに示す工程で積層セラミック電子部品(積層セラミックコンデンサ)が製造される。
【0005】
図4(b)に示すように、前記技術では、導電ペーストをマトリクス状に塗布した複数枚のセラミックグリーンシートを積層してマザー基板を形成し、該マザー基板を個々の積層セラミックコンデンサ単位の積層体に切り出す(s101→s102)。その後、切り出された複数の積層体を所定の温度、時間で乾燥する(s110)。乾燥された複数の積層体を脱バインダする(s103)。さらに本焼成してセラミック焼結体を形成し(s104)、該セラミック焼結体の外面に外部電極用導電ペーストを塗布し、該導電ペーストを焼結させることで外部電極を形成し(s105)、積層セラミックコンデンサを構成する。
【0006】
【発明が解決しようとする課題】
ところが、積層体焼成後、セラミック焼結体内部で内部電極と誘電体層とが剥がれる、すなわち積層された誘電体層間に層間ハガレが生じるという問題があった。この層間ハガレの原因として脱バインダ工程において、バインダ及び可塑剤や溶液等の有機物が同時に燃焼して分解されることにより、この分解ガスが一度に抜け出ようとするためである。この点を考慮すると、特開平6−310365号のように、熱処理を、70〜200℃程度の乾燥工程と300℃以上の脱バインダの2回に分けて行った場合、可塑剤の一部や溶剤は乾燥工程で抜け出るため、上記層間ハガレを抑制することができると考えられる。しかしながら、特開平6−310365号の技術を用いると、むしろ乾燥工程を設けない場合よりも層間ハガレが大きくなる傾向があることが分かった。
【0007】
そこで、層間ハガレの原因をさらに追求した結果、マザー基板形成時のプレスによってマザー基板内部に内部歪みが生じており、積層セラミックコンデンサ単位に切り出す際に、切断歯による機械的負荷が作用して開放されやすい状態、すなわち、誘電体層間の接合強度が弱くなっていることが分かった。すなわち、誘電体層間の接合強度が弱くなっている状態で、脱バインダや乾燥等の熱処理でバインダ及び可塑剤や溶液等の有機物が抜け出るため、層間ハガレが発生していることが分かった。
【0008】
この発明の目的は、マザー基板の内部歪みを緩和し、セラミック焼結体の層間ハガレの発生を抑制することができる、セラミック電子部品の製造方法を提供することにある。
【0009】
【課題を解決するための手段】
この発明に示す積層電子部品の製造方法では、マザー基板から複数の積層体を切り出す前に、マザー基板に含まれる可塑剤の沸点より高く且つバインダの分解温度より低い温度でマザー基板を熱処理する工程を含むことを特徴としている。
【0010】
この熱処理温度は、可塑剤がジオクチルフタレートでバインダがポリビニルブチラートの場合、100℃より高く180℃未満であることが望ましく、より好ましくは120℃以上150℃以下であることが望ましい。
【0011】
この構成では、前記所定の温度でマザー基板を熱処理することで、マザー基板内部の可塑剤や溶剤等の一部が分解して外部に放出されるので、マザー基板内の有機物の含有量が低下し、有機物が一度燃焼して層間強度が低下することが抑制される。
【0012】
【発明の実施の形態】
本発明の実施形態に係る積層電子部品の製造方法について、図を参照して説明する。なお、本実施形態では、積層セラミック電子部品として積層セラミックコンデンサを例に説明する。
【0013】
図1は積層セラミックコンデンサの断面斜視図である。
図2はマザー基板から積層体を切り出した状態を示した斜視図である。
図3は本実施形態に係る積層セラミックコンデンサの製造工程を示すフローチャートである。
【0014】
図1に示すように、この積層セラミックコンデンサは、誘電体層3と内部電極2とを所定数交互に積層してなるセラミック焼結体1の、内部電極2が露出する外面に、該内部電極2に導通する外部電極4を設けた構造である。
【0015】
次に、積層セラミックコンデンサの製造工程について図2、図3を参照して説明する。
まず、セラミック粉末に合成樹脂バインダおよび可塑剤等の有機溶剤を混練してなるセラミックスラリーを作製し、このセラミックスラリーを均一な厚みの平面状にしてセラミックグリーンシートを形成する。次に、それぞれのセラミックグリーンシートの表面に導電ペーストで、焼成後に内部電極となるパターンを形成した後、これらのセラミックグリーンシートを積層して、所定の圧力でプレスすることでマザー基板100を形成する(s1)。
【0016】
次に、マザー基板100を、空気中等、所定の雰囲気で可塑剤等の有機溶剤の沸点温度よりも高く、バインダが分解する温度よりも低い温度で熱処理する(s2)。
【0017】
熱処理されたマザー基板100は、図2に示すように、それぞれが積層セラミックコンデンサとなる大きさの積層体10に切断される。この状態で、各積層体10は、導電パターン20とセラミックグリーンシート30とを積層した状態となっている(s3)。
【0018】
このようにマザー基板100から切り出した積層体10を所定の温度、雰囲気で熱処理することで、積層体10内に存在する有機溶剤やバインダ等の不純物を燃焼させて、脱バインダを行う(s4)。さらに積層体10を焼成してセラミック焼結体1を形成する(s5)。
【0019】
そして、セラミック焼結体1の内部電極2が露出している面に導電ペーストを塗布し、焼結させることで、外部電極4を形成する(s6)。
【0020】
次に、熱処理の温度条件についての実験結果を示す。
【0021】
本実験には、長さが2.0mmで、幅が1.25mmで、高さが0.85mmの外形を成し、焼成後の誘電体層の厚みが3.0μmとなるようにセラミックグリーンシートが形成されており、内部電極数が120層の積層体をマトリクス状に多数配列形成しているマザー基板を用いた。このマザー基板を乾燥させた後にマザー基板から積層体を切り出して、該積層体を焼成してセラミック焼結体を形成する。そして、該セラミック焼結体における層間ハガレを目視確認して、その発生率を調査した。更に、従来技術との比較のため、熱処理を行わずに焼成を行った場合と、マザー基板から積層体を切り出した後に、熱処理して焼成を行った場合についても実験した。なお、本実験では、加熱温度をパラメータをして、加熱時間を30分に固定してオーブンで加熱を行った。実験結果を表1に示す。
【0022】
【表1】

Figure 0004019859
【0023】
表1から判るように、マザー基板の状態で加熱し、その加熱温度が100℃より高く180℃よりも低い場合には層間ハガレの発生率が低下する。さらに、加熱温度が120℃以上150℃以下であれば、層間ハガレの発生率は一段と低下する。
【0024】
一方、マザー基板の状態で加熱して、その加熱温度が100℃以下である場合には、層間ハガレの発生率は従来技術(脱バインダ以外の熱処理を行わない場合)の場合と変わらない。また、加熱温度が180℃以上である場合、マザー基板の状態で分解される可塑剤や溶剤が多すぎて、むしろ層間ハガレが生じやすくなる。
【0025】
前記結果より、加熱温度が100℃より高く180℃より低い場合、好ましくは120℃以上150℃以下である場合に、層間ハガレの抑制効果が得られることが判る。
【0026】
このことは、一般にジオクチルフタレート等の可塑剤の沸点が100℃程度であり、この温度よりも高い温度でマザー基板を加熱することで、マザー基板内に含まれている可塑剤の一部が分解し外部に放出されるため、焼成時に積層体に含まれる有機物の含有量が低下するからであると考えられる。これにより、脱バインダ時の有機物の燃焼による層間強度の低下を抑制することができる。また、マザー基板作製時には前述のようにプレスを行うが、通常、このプレスによりマザー基板内部に歪みが生じる。しかし、マザー基板を前記のように加熱することにより、この歪みが緩和される。これにより、焼成時に生じる層間ハガレを抑制することができる。
【0027】
また、マザー基板から積層体を切り出した後に加熱する場合には、層間ハガレの発生率は加熱温度に関係なく従来技術と変わらない。これは、マザー基板を熱処理していない状態で切断するので、切断刃の機械的負荷により積層体の内部歪みが解放されやすい状態となり、層間強度を低下させるからであると考えられる。このため、積層体に切断した後に乾燥を行っても、焼成による層間ハガレの発生を抑制することができない。
【0028】
むしろ、表1においては、加熱温度によっては従来技術よりも層間ハガレが増加している。これは、本実験では、加熱にオーブンを用いているためであると考えられる。すなわち、オーブンは徐々に昇温するようなものではないため、可塑剤等が一度に分解して、層間強度の低下した部分から抜け出すことで層間ハガレが生じやすくなっていると思われる。
【0029】
【発明の効果】
この発明に示す積層電子部品の製造方法によれば、マザー基板から複数の積層体を切り出す前に、マザー基板に含まれる可塑剤の沸点より高く且つバインダの分解温度より低い温度でマザー基板を熱処理すること、さらに、この加熱温度を、100℃より高く180℃未満とし、より好ましくは120℃以上150℃以下とすることで、マザー基板に含まれる可塑剤や溶剤等の一部が分解して外部に放出されるので、マザー基板内の有機物の含有量が低下し、焼成時に有機物が燃焼して層間強度の低下が抑制できる。また、マザー基板の状態で熱処理することで、内部歪みを解放して積層体を切り出す際の層間強度の低下を抑制できる。これにより、焼成時の層間ハガレの発生率を抑制することができ、安定して積層セラミック電子部品を製造することができる。
【図面の簡単な説明】
【図1】本発明の実施形態に係る積層セラミックコンデンサの断面斜視図
【図2】本発明の実施形態に係るマザー基板の外観斜視図
【図3】本発明の実施形態に係る積層セラミックコンデンサの製造工程を示すフローチャート
【図4】従来の積層セラミック電子部品の製造工程を示すフローチャート
【符号の説明】
1−セラミック焼結体
2−内部電極
3−誘電体層
4−外部電極
10−積層体
20−導電パターン
30−セラミックグリーンシート[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a multilayer ceramic electronic component such as a multilayer ceramic capacitor.
[0002]
[Prior art]
Normally, when manufacturing a multilayer ceramic electronic component, first, a plurality of laminates are formed simultaneously by forming a mother substrate in which a plurality of laminates are arranged, and then the mother substrate is cut into individual laminates. The method of baking is taken.
[0003]
For example, in the case of a multilayer ceramic capacitor, it is manufactured by the process shown in the flowchart of FIG. First, a plurality of ceramic green sheets coated with a conductive paste in a matrix are stacked and pressed at a predetermined pressure to form a mother substrate (s101). Next, the mother substrate is cut into a multilayer body of individual multilayer ceramic capacitor units (s102). By heat-treating the plurality of cut-out laminates, impurities such as plasticizer and binder contained in the ceramic green sheet and the conductive paste are burned to remove the binder (s103). Next, the laminated body is fired to form a ceramic sintered body in which the ceramic green sheet becomes a dielectric layer and the conductive paste pattern becomes an internal electrode (s104). An external electrode conductive paste is applied to the outer surface including the surface where the internal electrode of the ceramic sintered body is exposed, and the conductive paste is sintered to form the external electrode (s105).
[0004]
JP-A-6-310365 discloses that drying is performed before the binder removal step (s103) in order to prevent adhesion of the laminated body after cutting. In this manufacturing method, a plurality of laminated bodies are cut out from a mother substrate, and then dried at a predetermined temperature and time. A multilayer ceramic electronic component (multilayer ceramic capacitor) is manufactured by the process shown in the flowchart of FIG. Is manufactured.
[0005]
As shown in FIG. 4B, in the technique, a mother substrate is formed by laminating a plurality of ceramic green sheets coated with conductive paste in a matrix, and the mother substrate is laminated in units of individual multilayer ceramic capacitors. Cut into the body (s101 → s102). Thereafter, the plurality of cut laminates are dried at a predetermined temperature and time (s110). The plurality of dried laminates are removed from the binder (s103). Further, the main body is fired to form a ceramic sintered body (s104), an external electrode conductive paste is applied to the outer surface of the ceramic sintered body, and the conductive paste is sintered to form an external electrode (s105). A multilayer ceramic capacitor is constructed.
[0006]
[Problems to be solved by the invention]
However, there has been a problem that after firing the laminated body, the internal electrode and the dielectric layer are peeled off inside the ceramic sintered body, that is, interlayer peeling occurs between the laminated dielectric layers. The cause of this interlaminar peeling is that in the binder removal step, organic substances such as the binder and plasticizer and solution are simultaneously burned and decomposed, so that the decomposed gas tends to escape at once. In consideration of this point, as in JP-A-6-310365, when the heat treatment is performed in two steps of a drying step of about 70 to 200 ° C. and a binder removal of 300 ° C. or higher, a part of the plasticizer or Since the solvent escapes in the drying process, it is considered that the interlayer peeling can be suppressed. However, it has been found that the use of the technique disclosed in Japanese Patent Laid-Open No. 6-310365 tends to increase the interlayer peeling rather than the case where the drying process is not provided.
[0007]
Therefore, as a result of further pursuing the cause of interlayer peeling, internal distortion has occurred inside the mother board due to the press at the time of forming the mother board, and when cutting out in units of multilayer ceramic capacitors, a mechanical load due to cutting teeth acts to release it It was found that the bonding strength between the dielectric layers was weakened. That is, it was found that interlayer peeling occurred because organic substances such as binder, plasticizer, and solution were removed by heat treatment such as binder removal and drying in a state where the bonding strength between the dielectric layers was weak.
[0008]
An object of the present invention is to provide a method for manufacturing a ceramic electronic component that can alleviate internal distortion of a mother substrate and suppress the occurrence of interlayer peeling in a ceramic sintered body.
[0009]
[Means for Solving the Problems]
In the method for manufacturing a laminated electronic component according to the present invention, the process of heat-treating the mother substrate at a temperature higher than the boiling point of the plasticizer contained in the mother substrate and lower than the decomposition temperature of the binder before cutting out the plurality of laminated bodies from the mother substrate. It is characterized by including.
[0010]
When the plasticizer is dioctyl phthalate and the binder is polyvinyl butyrate, the heat treatment temperature is preferably higher than 100 ° C. and lower than 180 ° C., more preferably 120 ° C. or higher and 150 ° C. or lower.
[0011]
In this configuration, by heat-treating the mother substrate at the predetermined temperature, a part of the plasticizer or solvent inside the mother substrate is decomposed and released to the outside, so that the content of organic substances in the mother substrate is reduced. In addition, it is suppressed that the organic matter burns once and the interlaminar strength decreases.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
A method for manufacturing a laminated electronic component according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a multilayer ceramic capacitor will be described as an example of the multilayer ceramic electronic component.
[0013]
FIG. 1 is a cross-sectional perspective view of a multilayer ceramic capacitor.
FIG. 2 is a perspective view showing a state in which the laminated body is cut out from the mother substrate.
FIG. 3 is a flowchart showing manufacturing steps of the multilayer ceramic capacitor according to the present embodiment.
[0014]
As shown in FIG. 1, this multilayer ceramic capacitor has a ceramic sintered body 1 formed by alternately laminating a predetermined number of dielectric layers 3 and internal electrodes 2 on the outer surface where the internal electrodes 2 are exposed. 2 is provided with an external electrode 4 that is electrically connected to 2.
[0015]
Next, a manufacturing process of the multilayer ceramic capacitor will be described with reference to FIGS.
First, a ceramic slurry is prepared by kneading a ceramic powder with an organic solvent such as a synthetic resin binder and a plasticizer, and the ceramic slurry is formed into a flat surface with a uniform thickness to form a ceramic green sheet. Next, after forming a pattern to be an internal electrode after firing with a conductive paste on the surface of each ceramic green sheet, these ceramic green sheets are stacked and pressed at a predetermined pressure to form the mother substrate 100 (S1).
[0016]
Next, the mother substrate 100 is heat-treated at a temperature higher than the boiling point of the organic solvent such as a plasticizer and lower than the temperature at which the binder decomposes in a predetermined atmosphere such as air (s2).
[0017]
As shown in FIG. 2, the heat-treated mother substrate 100 is cut into laminated bodies 10 each having a size that becomes a laminated ceramic capacitor. In this state, each laminated body 10 is in a state where the conductive pattern 20 and the ceramic green sheet 30 are laminated (s3).
[0018]
Thus, the laminated body 10 cut out from the mother substrate 100 is heat-treated at a predetermined temperature and atmosphere, thereby burning impurities such as an organic solvent and a binder present in the laminated body 10 to perform binder removal (s4). . Further, the laminate 10 is fired to form the ceramic sintered body 1 (s5).
[0019]
Then, a conductive paste is applied to the surface of the ceramic sintered body 1 where the internal electrode 2 is exposed and sintered to form the external electrode 4 (s6).
[0020]
Next, the experimental result about the temperature conditions of heat processing is shown.
[0021]
In this experiment, the ceramic green was formed so that the length was 2.0 mm, the width was 1.25 mm, the height was 0.85 mm, and the thickness of the dielectric layer after firing was 3.0 μm. A mother substrate was used in which a sheet was formed and a large number of laminates having 120 internal electrodes were arranged in a matrix. After the mother substrate is dried, the laminate is cut out from the mother substrate, and the laminate is fired to form a ceramic sintered body. And the interlayer peeling in this ceramic sintered compact was confirmed visually, and the incidence rate was investigated. Furthermore, for comparison with the prior art, an experiment was conducted in the case where the firing was performed without performing the heat treatment and the case where the firing was performed after the laminate was cut out from the mother substrate. In this experiment, the heating temperature was set as a parameter, the heating time was fixed at 30 minutes, and heating was performed in an oven. The experimental results are shown in Table 1.
[0022]
[Table 1]
Figure 0004019859
[0023]
As can be seen from Table 1, when the substrate is heated in the state of the mother substrate and the heating temperature is higher than 100 ° C. and lower than 180 ° C., the generation rate of interlayer peeling is reduced. Furthermore, if the heating temperature is 120 ° C. or higher and 150 ° C. or lower, the generation rate of interlayer peeling further decreases.
[0024]
On the other hand, when heating is performed in the state of the mother substrate and the heating temperature is 100 ° C. or less, the generation rate of interlayer peeling is the same as in the case of the conventional technique (when heat treatment other than binder removal is not performed). In addition, when the heating temperature is 180 ° C. or higher, there are too many plasticizers and solvents that are decomposed in the state of the mother substrate, and interlayer peeling is likely to occur.
[0025]
From the results, it can be seen that when the heating temperature is higher than 100 ° C. and lower than 180 ° C., preferably 120 ° C. or higher and 150 ° C. or lower, the effect of suppressing interlayer peeling is obtained.
[0026]
This is because the plasticizer such as dioctyl phthalate generally has a boiling point of about 100 ° C., and by heating the mother substrate at a temperature higher than this temperature, a part of the plasticizer contained in the mother substrate is decomposed. However, since it is released to the outside, it is considered that the content of organic substances contained in the laminate during firing is reduced. Thereby, the fall of the interlayer intensity | strength by combustion of the organic substance at the time of a binder removal can be suppressed. Further, when the mother substrate is manufactured, the press is performed as described above. Usually, the press causes distortion in the mother substrate. However, this distortion is alleviated by heating the mother substrate as described above. Thereby, interlayer peeling which arises at the time of baking can be controlled.
[0027]
Moreover, when heating after cutting a laminated body from a mother board | substrate, the generation | occurrence | production rate of interlayer peeling does not change with a prior art irrespective of heating temperature. This is presumably because the mother substrate is cut without being heat-treated, so that the internal strain of the laminate is easily released by the mechanical load of the cutting blade, and the interlayer strength is reduced. For this reason, even if it drys after cut | disconnecting to a laminated body, generation | occurrence | production of the interlayer peeling by baking cannot be suppressed.
[0028]
Rather, in Table 1, the interlaminar peeling has increased compared to the prior art depending on the heating temperature. This is considered to be because an oven is used for heating in this experiment. That is, since the oven does not gradually raise the temperature, it seems that interlayer peeling is likely to occur due to the plasticizer and the like being decomposed at a time and coming out of the portion where the interlayer strength is reduced.
[0029]
【The invention's effect】
According to the method for manufacturing a laminated electronic component shown in the present invention, before cutting a plurality of laminated bodies from the mother substrate, the mother substrate is heat-treated at a temperature higher than the boiling point of the plasticizer contained in the mother substrate and lower than the decomposition temperature of the binder. Furthermore, when the heating temperature is higher than 100 ° C. and lower than 180 ° C., and more preferably 120 ° C. or higher and 150 ° C. or lower, a part of the plasticizer or solvent contained in the mother substrate is decomposed. Since it is released to the outside, the content of the organic substance in the mother substrate is reduced, and the organic substance is combusted at the time of firing, so that a decrease in interlayer strength can be suppressed. In addition, by performing heat treatment in the state of the mother substrate, it is possible to suppress a decrease in interlayer strength when releasing the internal strain and cutting out the laminated body. Thereby, the incidence rate of interlayer peeling during firing can be suppressed, and a multilayer ceramic electronic component can be manufactured stably.
[Brief description of the drawings]
FIG. 1 is a cross-sectional perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is an external perspective view of a mother substrate according to an embodiment of the present invention. Flow chart showing the manufacturing process [FIG. 4] Flow chart showing the manufacturing process of the conventional multilayer ceramic electronic component [Explanation of symbols]
1-Ceramic sintered body 2-Internal electrode 3-Dielectric layer 4-External electrode 10-Laminate 20-Conductive pattern 30-Ceramic green sheet

Claims (3)

それぞれに所定のパターンからなる導電ペーストを表面に形成した複数のセラミックグリーンシートを積層、圧着することによりマザー基板を形成する工程と、
該マザー基板から個々のセラミック電子部品単位の積層体を切り出す工程と、
該工程により切り出された複数の積層体を焼成する工程とを含む積層セラミック電子部品の製造方法であって、
前記マザー基板を前記複数の積層体に切り出す前に、前記マザー基板を、該マザー基板に含まれる可塑剤の沸点より高く且つバインダの分解温度より低い温度で熱処理する工程を含む積層セラミック電子部品の製造方法。
A step of forming a mother substrate by laminating and pressure-bonding a plurality of ceramic green sheets each having a predetermined pattern of conductive paste formed on the surface;
Cutting out a laminate of individual ceramic electronic component units from the mother substrate;
A method of manufacturing a multilayer ceramic electronic component including a step of firing a plurality of laminates cut out in the step,
Before cutting the mother substrate into the plurality of laminates, the mother substrate includes a step of heat-treating the mother substrate at a temperature higher than a boiling point of a plasticizer included in the mother substrate and lower than a decomposition temperature of a binder. Production method.
前記可塑剤はジオクチルフタレートであり、前記バインダはポリビニルブチラートであって、前記熱処理工程での温度は、100℃より高く180℃未満である請求項1に記載の積層セラミック電子部品の製造方法。2. The method of manufacturing a multilayer ceramic electronic component according to claim 1, wherein the plasticizer is dioctyl phthalate, the binder is polyvinyl butyrate, and the temperature in the heat treatment step is higher than 100 ° C. and lower than 180 ° C. 3. 前記熱処理工程での温度は、120℃以上150℃以下である請求項2に記載の積層セラミック電子部品の製造方法。The method for producing a multilayer ceramic electronic component according to claim 2, wherein the temperature in the heat treatment step is 120 ° C. or higher and 150 ° C. or lower.
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