JP4004765B2 - Method for manufacturing semiconductor device - Google Patents

Description

【００４５】
【表２】

【００４６】
半導体膜に添加した不純物元素を活性化する場合も、ゲッタリングする場合も同様であるが、このようなパルス状の輻射を複数回繰り返し照射することにより、基板を湾曲させることなく活性化率を向上させることを可能としている。また、ゲッタリングを可能としている。
【００４７】
[実施例２]
本発明の熱処理装置の他の一例として、大面積基板に対応したインライン式の熱処理装置の構成を図１６に示す。処理室１３０１は石英で形成され、その周りは水冷による冷却手段１３０５が設けられている。ランプ光源１３０２には反射板が付加され、光学レンズ１３２４により集光し被処理物に照射するようにしている。ランプ光源１３０２には棒状のハロゲンランプが用いられ、光学レンズ１３２４としてシリンドリカルレンズを用いることにより線状の光を被処理物に照射することができる。ランプ光源は光源制御ユニット１３０４によりパルス状に点灯させている。
【００４８】
処理室１３０１には冷媒供給源１３０６より冷媒として窒素ガスまたはヘリウムガスが供給される。窒素ガスは流量制御手段１３０７により処理室１３０１への供給量を制御できるようになっている。処理室に供給された冷媒は排気口１３１１から外部に排出され、処理室内は常に清浄な窒素ガスで充填されているようにしている。
【００４９】
制御手段１３１０は光源制御ユニット１３０４、流量制御手段１３０７、処理室における被処理物１３１７とステージ１３１８の搬送手段１３２３の動作を制御し、図２で示すようにランプ光源の点滅と冷媒の供給量の増減を同期させ、さらにステージ１３１８が移動するタイミングを制御している。
【００５０】
被処理物はステージに乗せられ、ロード室１３１５の基板ホルダー１３１６に設置される。そして、搬入室１３１３の搬送手段１３１４により処理室１３０１へ搬送される。搬入室１３１３と処理室１３０１との間には仕切弁１３１２が設けられ、熱処理時に処理室１３０１が冷媒で充填されるようになっている。
【００５１】
ステージ１３１８上に乗せられた被処理物１３１７は、処理室１３０１の搬送手段１３２３により移動しながら、ランプ光源１３０２からのパルス状の輻射が照射されるようになっている。こうして、被処理物の全面を熱処理することを可能としている。熱処理の終わった被処理物１３１７は、搬送手段１３２１によりステージ１３１８ごと搬出室１３２０に移動し、その後、アンロード室１３２２の基板ホルダー１３２６に収納される。
【００５２】
加熱方法は実施例１と同様にして行われるが、図１６に示す構成の装置の場合、被処理物が移動するので、パルス状の輻射とその移動のタイミングを連携させる必要がある。勿論、冷媒として用いる窒素ガスの流量は同様に制御する。被処理物の移動は図２において示す保持期間（２）において成され、段階的に移動するようにする。移動距離は適宣設定すれば良いが、パルス状の輻射が同じ領域を複数回照射されるように移動させる。
【００５３】
このような構成とすると、装置をさほど大型化することなく大面積基板の熱処理を行うことができる。そして、半導体膜に添加した不純物元素を活性化する場合も、ゲッタリングする場合も同様であるが、このようなパルス状の輻射を複数回繰り返し照射することにより、基板を湾曲させることなく活性化率を向上させることを可能としている。また、ゲッタリングを可能としている。
【００５４】
[実施例３]
次に本発明を用いたＴＦＴの作製方法の一例について図７を用いて説明する。図７（Ａ）において、アルミノホウケイ酸ガラスまたはバリウムホウケイ酸ガラスなどによる透光性の基板５０１上にシリコンを主成分とする結晶半導体膜を形成する。結晶半導体膜は、非晶質半導体膜をレーザーアニール法で結晶化することで得られる。また、実施例１または実施例２で説明する熱処理装置を用い、パルス状の輻射を照射しても得ることができる。結晶半導体膜の厚さは２５〜８０ｎｍの範囲で形成する。ＴＦＴの作製に当たっては、素子分離のため所定の大きさにエッチングし、島状に分割した半導体膜５０３〜５０５を形成する。また、基板５０１と半導体膜との間には、窒化シリコン、酸化シリコン、窒化酸化シリコンから選ばれた一つまたは複数種を組み合わせた第１絶縁膜５０２を５０〜２００ｎｍの厚さで形成する。
【００５５】
第１絶縁膜５０２の一例として、プラズマＣＶＤ法でＳｉＨ₄とＮ₂Ｏを用い酸化窒化シリコン膜を５０〜２００ｎｍの厚さに形成する。その他の形態として、プラズマＣＶＤ法でＳｉＨ₄とＮＨ₃とＮ₂Ｏから作製される酸化窒化シリコン膜を５０ｎｍ、ＳｉＨ₄とＮ₂Ｏから作製される酸化窒化シリコン膜を１００ｎｍ積層させた２層構造や、或いは、窒化シリコン膜とＴＥＯＳ（Tetraethyl Ortho Silicate）を用いて作製される酸化シリコン膜を積層させた２層構造としても良い。
【００５６】
半導体膜５０３〜５０５上には、１００ｎｍの厚さで酸化シリコン膜５０６をプラズマＣＶＤ法で形成する。さらに、図７（Ａ）に示すようにレジストによるマスク５０７を形成し、イオンドープ法によりｎ型不純物（ドナー）を添加することにより半導体膜５０４に第１ｎ型半導体領域５０８を形成する。ｎ型不純物（ドナー）として代表的にはリンが添加され、第１ｎ型半導体領域５０８のリン濃度の平均値は１×１０¹⁷〜１×１０¹⁹／ｃｍ³の範囲とする。ここでは、酸化シリコン膜５０６はリン濃度を制御するためのマスクとして利用している。
【００５７】
従って、ドーピング後酸化シリコン膜５０６はフッ酸などで除去し、第２絶縁膜５０９を８０ｎｍの厚さで形成する。第２絶縁膜５０９はゲート絶縁膜として利用するものであり、プラズマＣＶＤ法またはスパッタ法を用いて形成する。第２絶縁膜５０９として、ＳｉＨ₄とＮ₂ＯにＯ₂を添加させて作製する酸化窒化シリコン膜は膜中の固定電荷密度を低減させることが可能となり、ゲート絶縁膜として好ましい材料である。勿論、ゲート絶縁膜はこのような酸化窒化シリコン膜に限定されるものでなく、酸化シリコン膜や酸化タンタル膜などの絶縁膜を単層または積層構造として用いても良い。
【００５８】
そして、第２絶縁膜５０９上にゲート電極を形成するための第１導電膜と第２導電膜とを形成する。第１導電膜は光吸収性の導電膜で形成する。そのような導電膜の一例は窒化タンタルであり、これを５０〜１００ｎｍの厚さに形成しする。第２導電膜はタングステンやモリブデンなどの高融点金属を用い、１００〜３００ｎｍの厚さに形成する。これらの材料は、窒素雰囲気中における４００〜６００℃の熱処理でも安定であり、抵抗率が著しく増大することがない。
【００５９】
次に図７（Ｂ）に示すように、第１導電膜及び第２導電膜をエッチングし、ゲート電極５１０〜５１２（第１導電膜５１０ａ〜５１２ａと第２導電膜５１０ｂ〜５１２ｂから成る）を形成する。エッチング方法に限定はないが、好適にはＩＣＰ（Inductively Coupled Plasma：誘導結合型プラズマ）エッチング法を用いると良い。この時、エッチング用ガスにはＣＦ₄とＣｌ₂の混合ガスを用いる。
【００６０】
ゲート電極が形成された後、当該ゲート電極をマスクとしてイオンドープ法により半導体膜５０３〜５０５にｎ型不純物（ドナー）をドーピングする。こうして第２ｎ型半導体領域５１３〜５１５を形成する。第２ｎ型半導体領域５１３〜５１５のリン濃度の平均値は１×１０¹⁶〜１×１０¹⁸／ｃｍ³の範囲とするが、第１ｎ型半導体領域よりも低濃度で添加する。従って、半導体膜５０４において形成される第１ｎ型半導体領域はそのまま残存する。
【００６１】
続いて、図７（Ｃ）に示すように半導体膜５０３、５０５上にレジストによるマスク５１６、５１７を形成した後、再度イオンドープ法によりｎ型不純物（ドナー）をドーピングする。第３ｎ型半導体領域５１８〜５２０のリン濃度の平均値は１×１０²⁰〜１×１０²¹／ｃｍ³の範囲とする。この状態で、半導体膜５０４における第１ｎ型半導体領域５０８はゲート電極と重畳する領域で残存している。また、半導体膜５０５における第２ｎ型半導体領域５１５は、マスク５１７と重畳する領域で残存することになる。
【００６２】
そして、図７（Ｄ）に示すように、レジストによるマスク５２１を形成し、ｐチャネル型ＴＦＴを形成する半導体膜５０３にｐ型不純物（アクセプタ）をドーピングする。典型的にはボロン（Ｂ）を用いる。第１ｐ型半導体領域５２２の不純物濃度は２×１０²⁰〜２×１０²¹／ｃｍ³となるようにし、含有するリン濃度の最大値に対して１．５〜３倍のボロンを添加して導電型をｐ型に反転させる。
【００６３】
次に、図７（Ｅ）において、添加した不純物を活性化する熱処理を行う。この熱処理は実施例１または実施例２で説明する熱処理装置を用い、パルス状の輻射を複数回照射して活性化を行う。輻射は基板側から照射するので、ゲート電極と重畳する第１ｎ型半導体領域が形成されていても、その領域を含め確実にｐ型及びｎ型の不純物元素を活性化させることができる。
【００６４】
以上までの工程でそれぞれの半導体膜にソースまたはドレイン領域及び、ＬＤＤ領域を形成する不純物がドーピングされ、さらに活性化までが終了する。その後、図７（Ｆ）に示すように、窒化シリコン膜または酸化窒化シリコン膜から成る保護絶縁膜５２６をプラズマＣＶＤ法で形成する。そして、３５０〜４５０℃、好ましくは４１０℃の熱処理を行う。この温度で第１の層間絶縁膜中の水素を放出させ半導体膜の水素化を行う。そのために、この熱処理はファーネスアニール炉やクリーンオーブンで行う方が適している。
【００６５】
層間絶縁膜５２７は、ポリイミド、アクリルなどの有機絶縁物材料で形成し表面を平坦化する。勿論、プラズマＣＶＤ法でＴＥＯＳ（Tetraethyl Ortho Silicate）を用いて形成される酸化シリコン膜を適用しても良いが、平坦性を高める観点からは前記有機物材料を用いることが望ましい。
【００６６】
次いで、コンタクトホールを形成し、アルミニウム（Ａｌ）、チタン（Ｔｉ）、タンタル（Ｔａ）などを用いて、ソースまたはドレイン配線５２８〜５３３を形成する。
【００６７】
以上の工程によって作製されるｐチャネル型ＴＦＴ５４０にはチャネル形成領域５２３、ソースまたはドレイン領域として機能する第１ｐ型半導体領域５２２を有している。ｎチャネル型ＴＦＴ５４１はチャネル形成領域５２４、ゲート電極５１１と重畳する第１ｎ型半導体領域５０８とソースまたはドレイン領域として機能する第３ｎ型半導体領域５１９を有している。第１ｎ型半導体領域はＬＤＤ領域であり、ゲート電極と重畳させて形成することによりドレイン端に形成れる高電界領域を緩和してホットキャリア効果によるＴＦＴの劣化を防止する。ｎチャネル型ＴＦＴ５４２はチャネル形成領域５２５、ゲート電極５１２の外側に第２ｎ型半導体領域５１５とソースまたはドレイン領域として機能する第３ｎ型半導体領域５２０が形成される。第２ｎ型半導体領域５１５はＬＤＤ領域であり、ＴＦＴのオフ電流を低減することができる。本実施例で示す工程では、オフ電流値を低減するために最適な寸法を設定することができる。
【００６８】
以上の工程で、ｎチャネル型ＴＦＴとｐチャネル型ＴＦＴとを相補的に組み合わせたＣＭＯＳ型のＴＦＴを得ることができる。本実施例で示す工程は、各ＴＦＴに要求される特性を考慮してＬＤＤを設計し、同一基板内において作り分けることができる。このようなＣＭＯＳ型のＴＦＴは、アクティブマトリクス駆動する表示装置の駆動回路を形成することを可能とする。それ以外にも、このようなｎチャネル型ＴＦＴまたはｐチャネル型ＴＦＴは、画素部を形成するトランジスタに応用することができる。さらに、従来の半導体基板にて作製されるＬＳＩに代わる薄膜集積回路を実現するＴＦＴとして用いることができる。尚、ここではＴＦＴをシングルゲートの構造で示したが、勿論、複数のゲート電極を設けたマルチゲート構造を採用することもできる。
【００６９】
このようなＴＦＴの製造工程において本発明の熱処理装置は活性化を行うために用いることができる。また本発明の熱処理方法は、基板にダメージを与えることなく活性化を短時間で行うことができる。
【００７０】
[実施例４]
本実施例では本発明の熱処理装置を用いた半導体装置の作製方法の一例として、ｎチャネル型ＴＦＴとｐチャネル型ＴＦＴから成る駆動回路と画素部を同一基板上に作製する方法を図１０〜図１２を用いて説明する。
【００７１】
まず、図１０（Ａ）に示すように基板６０１上に第１絶縁膜６０２をプラズマＣＶＤ法でＳｉＨ₄とＮＨ₃とＮ₂Ｏから作製される酸化窒化シリコン膜を５０ｎｍ、ＳｉＨ₄とＮ₂Ｏから作製される酸化窒化シリコン膜を１００ｎｍ積層させた２層構造で形成する。ここで用いる基板はアルミノホウケイ酸ガラスやバリウムホウケイ酸ガラスなどの無アルカリガラス基板が適当であり、厚さは０．５〜１．１ｍｍ程度のものを使用する。
【００７２】
この上に形成する半導体膜６０３〜６０６は厚さを４０ｎｍとし、プラズマＣＶＤ法或いは減圧ＣＶＤ法で堆積した非晶質シリコンをレーザーアニール法や固相成長法を用いて結晶化させた多結晶シリコンを用いる。或いは、実施例１または実施例２で説明する熱処理装置を用い、パルス状の輻射により結晶化させても同様に得ることができる。そして、光露光工程を経て島状に分割する。以降、本実施例では、半導体膜６０３にｐチャネル型ＴＦＴを形成し、半導体膜６０４、６０５にｎチャネル型ＴＦＴを形成することを前提に説明する。また、半導体膜６０６は補助容量を形成するために設けている。
【００７３】
これら半導体膜を覆って７５ｎｍの厚さで第２絶縁膜６０７を形成しゲート絶縁膜とする。第２絶縁膜はプラズマＣＶＤ法でＴＥＯＳ(Tetraethyl Ortho Silicate)を原料とした酸化シリコン、またはＳｉＨ₄とＮ₂Ｏを原料とした酸化窒化シリコンで形成する。
【００７４】
次に、図１０（Ｂ）に示すように、第２絶縁膜上に第１導電膜６０８と第２導電膜６０９を形成する。第１導電膜６０８は窒化タンタルであり、第２導電膜はタングステンを用いて形成する。この導電膜はゲート電極を形成する為のものであり、それぞれの厚さは３０ｎｍ及び３００ｎｍとする。
【００７５】
その後、図１０（Ｃ）に示すように光露光工程により、ゲート電極及びデータ線を形成するためのレジストパターン６１０を形成する。このレジストパターンを用いて第１のエッチング処理を行う。エッチング方法に限定はないが、好適にはＩＣＰ（Inductively Coupled Plasma：誘導結合型プラズマ）エッチング法を用いる。タングステン及び窒化タンタルのエッチング用ガスとしてＣＦ₄とＣｌ₂を用い、０．５〜２Ｐａ、好ましくは１Ｐａの圧力でコイル型の電極に５００ＷのＲＦ（１３．５６ＭＨｚ）電力を投入してプラズマを生成して行う。この時、基板側（ステージ）にも１００ＷのＲＦ（１３．５６ＭＨｚ）電力を投入して、実質的に負の自己バイアス電圧を印加する。ＣＦ₄とＣｌ₂を混合した場合にはタングステン、窒化タンタルをそれぞれ同程度の速度でエッチングすることができる。
【００７６】
上記エッチング条件では、レジストによるマスクの形状と、基板側に印加するバイアス電圧の効果により端部をテーパー形状とすることができる。テーパー部の角度は１５〜４５°となるようにする。また、ゲート絶縁膜上に残渣を残すことなくエッチングするためには、１０〜２０％程度の割合でエッチング時間を増加させると良い。Ｗ膜に対する酸化窒化シリコン膜の選択比は２〜４（代表的には３）であるので、オーバーエッチング処理により第２の絶縁膜が露出した面は２０〜４０ｎｍ程度エッチングされる。こうして、第１のエッチング処理により窒化タンタルとタングステンから成る第１形状電極６１１〜６１４（窒化タンタル６１１ａ〜６１４a、タングステン６１１ｂ〜６１４ｂ）と第１形状配線６１５窒化タンタル（６１５a、タングステン６１５ｂ）を形成する。
【００７７】
そして、第１のドーピング処理を行いｎ型の不純物（ドナー）を半導体膜にドーピングする。その方法はイオンドープ法またはイオン注入法で行う。イオンドープ法の条件はドーズ量を１×１０¹³〜５×１０¹⁴／ｃｍ²として行う。ｎ型を付与する不純物元素として１５族に属する元素、典型的にはリン（Ｐ）または砒素（Ａｓ）を用いる。この場合、第１形状電極６１１〜６１４はドーピングする元素に対してマスクとなり、加速電圧を適宣調節（例えば、２０〜６０ｋｅＶ）して、第２絶縁膜を通過した不純物元素により第１不純物領域６１６〜６１９を形成する。第１の不純物領域６１６〜６１９おけるリン（Ｐ）濃度は１×１０²⁰〜１×１０²¹／ｃｍ³の範囲となるようにする。
【００７８】
続いて、図１１（Ａ）に示すように第２のエッチング処理を行う。エッチングはＩＣＰエッチング法を用い、エッチングガスにＣＦ₄とＣｌ₂とＯ₂を混合して、１Ｐａの圧力でコイル型の電極に５００ＷのＲＦ電力(１３．５６ＭＨｚ)を供給してプラズマを生成する。基板側（ステージ）には５０ＷのＲＦ（１３．５６ＭＨｚ）電力を投入し、第１のエッチング処理に比べ低い自己バイアス電圧を印加する。このような条件によりタングステン膜を異方性エッチングし、第１の導電膜である窒化タンタル膜を残存させるようにする。こうして、第２のエッチング処理により窒化タンタルとタングステンから成る第２形状電極６２０〜６２３（窒化タンタル６２０ａ〜６２３a、タングステン６２０ｂ〜６２３ｂ）と第２形状配線６２４窒化タンタル（６２４a、タングステン６２４ｂ）を形成する。第２絶縁膜はこのエッチング処理により窒化タンタルで覆われていない部分が１０〜３０ｎｍ程度エッチングされ薄くなる。
【００７９】
第２のドーピング処理におけるドーズ量は第１のドーピング処理よりも少なくし、かつ高加速電圧の条件でｎ型不純物（ドナー）をドーピングする。例えば、加速電圧を７０〜１２０ｋｅＶとし、１×１０¹³／ｃｍ²のドーズ量で行い、第１の不純物領域の内側に第２の不純物領域を形成する。ドーピングは露出した窒化タンタル６２０ａ〜６２３aを通過させ、その下側の半導体膜に不純物元素を添加する。こうして、窒化タンタル６２０ａ〜６２３aと重なる第２不純物領域６２５〜６２８を形成する。この不純物領域は、窒化タンタル６２０ａ〜６２３aの膜厚によって変化するが、そのピーク濃度は１×１０¹⁷〜１×１０¹⁹／ｃｍ³の範囲で変化する。この領域のｎ型不純物の深さ分布は一様ではなくある分布をもって形成される。
【００８０】
次に、図１１（Ｂ）に示すように、光露光工程により第２形状電極６２１を覆うレジストマスク６２９を形成し、露出している第２形状電極の窒化タンタル膜を選択的にエッチングする。エッチングガスにはＣｌ₂とＳＦ₆の混合ガスを用いて行う。こうしてタングステンと窒化タンタルの端部が一致する第３形状電極６３０〜６３２を形成する。また、同時にデータ線も加工して、同様に第３形状の配線６３３を形成しても良い。
【００８１】
そして図１１（Ｃ）に示すようにレジストによるマスク６３４、６３５を形成し、半導体膜６０３、６０６にｐ型不純物（アクセプタ）をドーピングする。典型的にはボロン（Ｂ）を用いる。第１のｐ型半導体領域６３６、６３７の不純物濃度は２×１０²⁰〜２×１０²¹／ｃｍ³となるようにし、含有するリン濃度の１．５〜３倍のボロンを添加して導電型をｐ型にする。
【００８２】
以上までの工程でそれぞれの半導体膜に不純物領域が形成される。第２形状電極６２１及び第３形状電極６３０〜６３２はゲート電極として機能する。また、第３形状の配線６３３はデータ線を形成する。ゲート電極６３２は付加容量を形成する一方の電極となり、半導体膜６０６と重なる部分で容量を形成する。
【００８３】
その後、図１２（Ａ）に示すように、酸化窒化シリコン膜から成る保護絶縁膜６３８をプラズマＣＶＤ法で５０ｎｍの厚さに形成する。そして、添加した不純物を活性化する熱処理を行う。この熱処理は実施例１または実施例２で説明する熱処理装置を用い、パルス状の輻射を複数回照射して活性化を行う。輻射は基板側から照射するので、ゲート電極と重畳する第１ｎ型半導体領域が形成されていても、その領域を含め確実にｐ型及びｎ型の不純物元素を活性化させることができる。
【００８４】
水素化処理はＴＦＴの特性を向上させるために必要な処理であり、水素雰囲気中で加熱処理をする方法やプラズマ処理をする方法で行うことができる。その他にも、図１２（Ｂ）で示すように、窒化シリコン膜６４０を５０〜１００ｎｍの厚さに形成し、３５０〜５００℃の加熱処理を行うことで窒化シリコン膜６４０中の水素が放出され、半導体膜に拡散させることで水素化し、欠陥を補償することができる。
【００８５】
層間絶縁膜６４１は、ポリイミドまたはアクリルなどの有機絶縁物材料で形成し表面を平坦化する。勿論、プラズマＣＶＤ法でＴＥＯＳを用いて形成される酸化シリコンを適用しても良いが、平坦性を高める観点からは前記有機物材料を用いることが望ましい。
【００８６】
次いで、層間絶縁膜６４１の表面から各半導体膜の第２ｎ型半導体領域または第１ｐ型半導体領域に達するコンタクトホールを形成し、Ａｌ、Ｔｉ、Ｔａなどを用いて配線を形成する。図１２（Ｂ）において６４２、６４５はソース線とし、６４３、６４４はドレイン配線とする。６４７は画素電極であり、６４６はデータ線６３３と半導体膜６０５の第２ｎ型半導体領域６６７とを接続する接続電極である。また、６４８はゲート線であり、図中には示されていないが、ゲート電極として機能する第３形状電極６３１と接続している。
【００８７】
こうして同一基板上に駆動回路６５０と画素部６５１を形成するＴＦＴが形成される。駆動回路６５０にはｐチャネル型ＴＦＴ６５２とｎチャネル型ＴＦＴ６５３の２つを示しているが、これらのＴＦＴを用いてシフトレジスタ、レベルシフタ、ラッチ、バッファ回路など様々な機能回路を形成することができる。また、図１２（Ｂ）で示すＢ−Ｂ'間の断面構造は、図１３で示す画素構造において示すＢ−Ｂ'線に対応している。
【００８８】
駆動回路６５０のｐチャネル型ＴＦＴ６５２にはチャネル形成領域６６０、ソース領域またはドレイン領域として機能する第１のｐ型半導体領域６６１を有している。ｎチャネル型ＴＦＴ６５３はチャネル形成領域６６２、ゲート電極６２１と重なる第１のｎ型半導体領域６６３、ソース領域またはドレイン領域として機能する第２のｎ型半導体領域６６４を有している。
【００８９】
また、画素部６５１のｎチャネル型ＴＦＴ６５４は、チャネル形成領域６６５、ゲート電極６４０の外側に第１のｎ型半導体領域６６６、ソースまたはドレイン領域として機能する第２ｎ型半導体領域６６７〜６６９が形成されている。また、補助容量６５５は半導体膜６０６と第２絶縁膜６０７とゲート電極６３２とで形成される。半導体膜６０６には上記工程により第１のｐ型半導体領域６７１が形成されている。
【００９０】
ｎチャネル型ＴＦＴに形成される第１のｎ型半導体領域はＬＤＤ（Lightly Doped Drain）領域である。ｎチャネル型ＴＦＴ６５３のようにゲート電極と重畳させて形成することにより、ドレイン端に形成される高電界領域が緩和され、ホットキャリア効果による劣化を抑止することができる。一方、ｎチャネル型ＴＦＴ６５４のようにゲート電極の外側にＬＤＤ領域を設けることによりオフ電流を低下させることができる。
【００９１】
ｐチャネル型ＴＦＴ６５２はシングルドレイン構造で形成されるが、第３のエッチング処理の時間を調節することにより、ゲート電極の端部を後退させ、チャネル形成領域と不純物領域との間にオフセット領域を形成することもできる。このような構成はｎチャネル型ＴＦＴ６５４においても可能であり、オフ電流を低減する目的において非常に有効である。
【００９２】
以上のようにして、同一基板上に画素部と駆動回路をＴＦＴで形成した素子基板を形成することができる。本実施例で示す素子基板の作製工程は５枚のフォトマスクでＬＤＤ領域の構成の異なるＴＦＴを同一基板上に形成することを可能としている。
【００９３】
実施例３と同様に、このようなＴＦＴの製造工程において本発明の熱処理装置は活性化を行うために用いることができる。また本発明の熱処理方法は、基板にダメージを与えることなく活性化を短時間で行うことができる。
【００９４】
[実施例５]
本実施例は実施例３または実施例４に適用できる半導体膜の作製方法の他の一例を図８を用いて説明する。図８で説明する半導体膜の作製方法は、非晶質シリコン膜の全面に金属元素を添加して結晶化させる方法である。適用される金属元素はＦｅ、Ｃｏ、Ｎｉ、Ｒｕ、Ｒｈ、Ｐｄ、Ｏｓ、Ｉｒ、Ｐｔ、Ｃｕ、Ａｕから選ばれた一種または複数種であり、代表的にはＮｉを適用する。これらの元素は、結晶化のための熱処理温度の低温下を可能とし、また、熱処理時間の短縮をも可能とすることが見出されている。
【００９５】
まず、図８（Ａ）において、基板５５１はコーニング社の#１７７３ガラス基板に代表されるガラス基板を用いる。基板５５１の表面には、第１絶縁膜５５２としてプラズマＣＶＤ法でＳｉＨ₄とＮ₂Ｏを用い酸化窒化シリコン膜を１００ｎｍの厚さに形成する。第１絶縁膜５５２はガラス基板に含まれるアルカリ金属がこの上層に形成する半導体膜中に拡散しないために設ける。
【００９６】
非晶質シリコン膜５５３はプラズマＣＶＤ法により作製する。ＳｉＨ₄を反応室に導入し、間欠放電またはパルス放電により分解して基板５５１に堆積させる。その成膜条件の一例は、２７ＭＨｚの高周波電力を変調し、繰り返し周波数５ｋＨｚ、デューティー比２０％の間欠放電により５４ｎｍの厚さに堆積する。勿論、１３．５６ＭＨｚの連続放電を用いても良い。非晶質シリコン膜５５３の酸素、窒素、炭素などの不純物を極力低減するためには、ＳｉＨ₄は純度９９．９９９９％以上のものを用いる。また、プラズマＣＶＤ装置の仕様としては、反応室の容積１３リットルの反応室に対し、一段目に排気速度３００リットル／秒の複合分子ポンプ、二段目に排気速度４０ｍ³／ｈｒのドライポンプを設け、排気系側から有機物の蒸気が逆拡散してくるのを防ぐと共に、反応室の到達真空度を高め、非晶質半導体膜の形成時に不純物元素が膜中に取り込まれることを極力防いでいる。
【００９７】
そして、重量換算で１０ｐｐｍのニッケルを含む酢酸ニッケル塩溶液をスピナーで塗布してニッケル含有層５５４を形成する。この場合、当該溶液の馴染みをよくするために、非晶質半シリコン膜５５３の表面処理として、オゾン含有水溶液で極薄い酸化膜を形成し、その酸化膜をフッ酸と過酸化水素水の混合液でエッチングして清浄な表面を形成した後、再度オゾン含有水溶液で処理して極薄い酸化膜を形成しておく。シリコンの表面は本来疎水性なので、このように酸化膜を形成しておくことにより酢酸ニッケル塩溶液を均一に塗布することができる。
【００９８】
次に、５００℃にて１時間の加熱処理を行い、非晶質シリコン膜中の水素を放出させる。そして、５８０℃にて４時間に加熱処理を行い結晶化を行う。こうして、図８（Ｂ）に示す結晶シリコン膜５５５が形成される。
【００９９】
さらに結晶化率（膜の全体積における結晶成分の割合）を高め、結晶粒内に残される欠陥を補修するために、結晶シリコン膜５５５に対してレーザー光５５６を照射するレーザーアニールを行う。レーザーは波長３０８ｎｍにて３０Ｈｚで発振するエキシマレーザー光を用いる。当該レーザー光は光学系にて１００〜３００ｍＪ／ｃｍ²に集光し、９０〜９５％のオーバーラップ率をもって半導体膜を溶融させることなくレーザー処理を行う。結晶シリコン膜５５７を得ることができる。
【０１００】
結晶シリコン膜５５７を島状に分割して半導体膜５５８が形成される。このような半導体膜はそのまま実施例３及び実施例４に適用することができる。
【０１０１】
[実施例６]
本実施例は実施例５において得られた半導体膜に残留する金属元素をゲッタリングする方法の一例を図９を用いて説明する。ここで説明するゲッタリングは、ＴＦＴのチャネル形成領域から当該金属元素ゲッタリングする方法を前提としている。図９では、基板５６１上に第１絶縁膜５６２、半導体膜５６３、第２絶縁膜５６７、第１導電膜５６８、第２導電膜５６９が形成された状態を示している。半導体膜５６３は実施例５の方法で作製される半導体膜が適用され、ｎ型半導体領域５６５には１×１０²⁰〜１×１０²¹／ｃｍ³のリンが添加されている。
【０１０２】
半導体膜５６３は、ｎ型半導体領域５６５がＴＦＴにおけるソースまたはドレイン領域、５６４がチャネル形成領域と見なすことができる。ここで、チャネル形成領域には結晶化のために添加した金属元素が１×１０¹⁷〜１×１０¹⁹／ｃｍ³程度の濃度で残存する。本発明の熱処理方法は、この金属元素をｎ型半導体領域５６５に偏析させる、いわゆるゲッタリングを可能としている。
【０１０３】
この熱処理の方法は実施例１に従い、基板側からパルス状の輻射５７０を照射する。パルス状の輻射は図３のグラフにおいて示す曲線Ａのパルス状の輻射が適している。すなわち、１００〜２００℃／秒の速度で１１００℃まで加熱し、４秒間その温度を保持する。冷却速度は５０〜１５０℃／秒として３００〜４００℃まで冷却する。このような輻射を１回照射するだけでもゲッタリングの効果を確認することができる。さらに好ましくは、２〜１０回のパルス状の輻射を照射すると良い。こうして、結晶化の工程で使用した金属元素の濃度を１×１０¹⁷／ｃｍ³未満にまで低減させることができる。
【０１０４】
このようなゲッタリング方法は、実施例３〜４と自由に組み合わせて行うことができる。例えば、実施例４において、活性化のための熱処理に本実施例で説明するゲッタリングを組み合わせることができる。
【０１０５】
[実施例７]
本実施例では実施例４により得られる駆動回路と画素部が形成された基板（素子基板と呼ぶ）から、アクティブマトリクス駆動の液晶表示装置を作製する工程を説明する。図１４は素子基板７００と対向基板７０１とをシール材で貼り合わせた状態を示している。素子基板７００上には柱状のスペーサ７０４を形成する。柱状のスペーサ７０４、７０５は画素電極上に形成されるコンタクト部の窪みに合わせて形成すると良い。柱状スペーサ７０４は用いる液晶材料にも依存するが３〜１０μmの高さで形成する。コンタクト部では、コンタクトホールに対応した凹部が形成されるので、この部分に合わせてスペーサを形成することにより液晶の配向の乱れを防ぐことができる。その後、配向膜７０６を形成しラビング処理を行う。対向基板７０１には透明導電膜７０２、配向膜７０３を形成する。その後、素子基板７００と対向基板７０１とをシール材７０７により貼り合わせ液晶を注入し、液晶層７０８を形成する。以上のようにして作製されるアクティブマトリクス駆動の液晶表示装置を完成させることができる。
【０１０６】
[実施例８]
本実施例では実施例４により得られるＴＦＴから、アクティブマトリクス駆動の発光装置を作製する工程を図１５を用いて説明する。
【０１０７】
基板１６０１はガラス基板を用いる。このガラス基板１６０１上には駆動回路部１６５０にｎチャネル型ＴＦＴ１６５２とｐチャネル型ＴＦＴ１６５３が形成され、画素部１６５１にスイッチング用ＴＦＴ１６５４、電流制御用ＴＦＴ１６５５が形成されている。これらのＴＦＴは、半導体層１６０３〜１６０６、ゲート絶縁膜とする第２絶縁膜１６０７、ゲート電極１６０８〜１６１１などを用いて形成されている。
【０１０８】
基板１６０１上に形成する第１絶縁膜１６０２は酸化窒化シリコン（ＳｉＯ_xＮ_yで表される）、窒化シリコン膜などを５０〜２００ｎｍの厚さに形成して設ける。層間絶縁膜は窒化シリコン、酸化窒化シリコンなどで形成される無機絶縁膜１６１８と、アクリルまたはポリイミドなどで形成される有機絶縁膜１６１９とから成っている。
【０１０９】
駆動回路部１６５０の回路構成は、ゲート信号側駆動回路とデータ信号側駆動回路とで異なるがここでは省略する。ｎチャネル型ＴＦＴ１６５２及びｐチャネル型ＴＦＴ１６５３には配線１６１２、１６１３が接続され、これらのＴＦＴを用いて、シフトレジスタやラッチ回路、バッファ回路などが形成される。
【０１１０】
画素部１６５１では、データ配線１６１４がスイッチング用ＴＦＴ１６５４のソース側に接続し、ドレイン側の配線１６１５は電流制御用ＴＦＴ１６５５のゲート電極１６１１と接続している。また、電流制御用ＴＦＴ１６５５のソース側は電源供給配線１６１７と接続し、ドレイン側の電極１６１６がＥＬ素子の陽極と接続するように配線されている。
【０１１１】
陽極、陰極及びその間にエレクトロルミネセンス（Electro Luminescence）が得られる有機化合物を含む層（以下、ＥＬ層と総称する）を有するＥＬ素子は画素部のＴＦＴ上に形成される。尚、有機化合物におけるミネセンスには一重項励起状態から基底状態に戻る際の発光（蛍光）と三重項励起状態から基底状態に戻る際の発光（りん光）とがあり、その両者を含むものとする。
【０１１２】
ＥＬ素子は、配線を覆うようにアクリルやポリイミドなどの有機樹脂、好適には感光性の有機樹脂を用いてバンク１６２０、１６２１を形成した後に設ける。本実施例では、ＥＬ素子１６５６は、ＩＴＯ（酸化インジウム・スズ）で形成される陽極１６２２、ＥＬ層１６２３、ＭｇＡｇやＬｉＦなどのアルカリ金属またはアルカリ土類金属などの材料を用いて形成される陰極１６２４とから成っている。バンク１６２０、１６２１は、陽極１６２２の端部を覆うように形成され、この部分で陰極と陽極とがショートすることを防ぐために設ける。
【０１１３】
ＥＬ層１６２３の上にはＥＬ素子の陰極１６２４が設けられる。陰極１６２４としては、仕事関数の小さいマグネシウム（Ｍｇ）、リチウム（Ｌｉ）若しくはカルシウム（Ｃａ）を含む材料を用いる。好ましくはＭｇＡｇ（ＭｇとＡｇをＭｇ：Ａｇ＝１０：１で混合した材料）でなる電極を用いれば良い。他にもＭｇＡｇＡｌ電極、ＬｉＡｌ電極、また、ＬｉＦＡｌ電極が挙げられる。
【０１１４】
ＥＬ層１６２３と陰極１６２４とでなる積層体は、各画素で個別に形成する必要があるが、ＥＬ層１６２３は水分に極めて弱いため、通常のフォトリソグラフィ技術を用いることができない。また、アルカリ金属を用いて作製される陰極１６２４は容易に酸化されてしまう。従って、メタルマスク等の物理的なマスク材を用い、真空蒸着法、スパッタ法、プラズマＣＶＤ法等の気相法で選択的に形成することが好ましい。また、陰極１６２４上に外部の水分等から保護するための保護電極を積層しても良い。保護電極としては、アルミニウム（Ａｌ）、銅（Ｃｕ）若しくは銀（Ａｇ）を含む低抵抗な材料を用いることが好ましい。
【０１１５】
少ない消費電力で高い輝度を得るためには、ＥＬ層を形成する材料に三重項励起子（トリプレット）により発光する有機化合物（以下、トリプレット化合物という）を用いる。尚、シングレット化合物とは一重項励起のみを経由して発光する化合物を指し、トリプレット化合物とは三重項励起を経由して発光する化合物を指す。
【０１１６】
トリプレット化合物は、としては以下の論文に記載の有機化合物が代表的な材料として挙げられる。（１）T.Tsutsui, C.Adachi, S.Saito, Photochemical Processes in Organized Molecular Systems, ed.K.Honda, (Elsevier Sci.Pub., Tokyo,1991) p.437.（２）M.A.Baldo, D.F.O'Brien, Y.You, A.Shoustikov, S.Sibley, M.E.Thompson, S.R.Forrest, Nature 395 (1998) p.151.この論文には次の式で示される有機化合物が開示されている。（３）M.A.Baldo, S.Lamansky, P.E.Burrrows, M.E.Thompson, S.R.Forrest, Appl.Phys.Lett.,75 (1999) p.4.（４）T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.
【０１１７】
上記トリプレット化合物は、シングレット化合物よりも発光効率が高く、同じ発光輝度を得るにも動作電圧（ＥＬ素子を発光させるに要する電圧）を低くすることが可能である。
【０１１８】
図１５ではスイッチング用ＴＦＴ１６５４をマルチゲート構造とし、電流制御用ＴＦＴ１６５５にはゲート電極とオーバーラップするＬＤＤを設けている。多結晶シリコンを用いたＴＦＴは、高い動作速度を示すが故にホットキャリア注入などの劣化も起こりやすい。そのため、図１５のように、画素内において機能に応じて構造の異なるＴＦＴ（オフ電流の十分に低いスイッチング用ＴＦＴと、ホットキャリア注入に強い電流制御用ＴＦＴ）を形成することは、高い信頼性を有し、且つ、良好な画像表示が可能な（動作性能の高い）表示装置を作製する上で非常に有効である。以上のようにして作製されるアクティブマトリクス駆動の発光装置を完成させることができる。
【０１１９】
[実施例９]
結晶半導体膜にリンをイオンドープ法により添加し、その後の活性化を本発明の熱処理方法を用いて行った試料の顕微鏡写真を図１７（Ａ）〜（Ｃ）に示す。試料は図４と同様な構造を有しており、ガラス基板上に１００ｎｍの窒化酸化シリコン膜、５０ｎｍの半導体膜、８０ｎｍ窒化酸化シリコン膜が積層され、その上にパターン形成された３０ｎｍの窒化タンタル膜と３００ｎｍのタングステン膜が形成されている。
【０１２０】
周知の如く、イオンドープ法により不純物元素が注入された領域は、イオンの衝撃により非晶質化する。その後必要となる熱処理は、非晶質化した領域を再度結晶化させることを目的とし、同時に不純物元素を活性化させるものである。
【０１２１】
照射するパルス状の輻射は図３のグラフ曲線Ａ（保持時間４秒）と曲線Ｂ（保持時間０．７５秒）と同等な輻射をそれぞれ照射した。図１７（Ａ）は曲線Ｂのパルス状の輻射を１回照射した試料であり、半導体膜が露出した領域においてまだら模様が観察され、十分に結晶化が進んでいないことが確認される。この場合、経験則より色の濃い部分は非晶質であり、薄い領域が結晶であると判断している。図１７（Ｂ）は同様のパルス状の輻射を４回繰り返して照射した試料に写真であり、同様にまだら模様が観測されているもののその数は減っているものと確認できる。図１７（Ｃ）は曲線Ａのパルス状の輻射を１回照射した試料であり、殆どが結晶化しているものと判断できる。
【０１２２】
上記結果は、本発明の熱処理方法によって、基板にダメージを与えることなくイオンドープ法により添加したリンを活性化できることを示している。そして、照射する条件にもよるが、１回の照射よりも複数回照射した方がより好ましい結果が得られることを示している。
【０１２３】
[実施例１０]
本発明を用いて各種多様の半導体装置を完成させることができる。本発明が適用される半導体装置として携帯情報端末（電子手帳、モバイルコンピュータ、携帯電話等）、ビデオカメラ、スチルカメラ、パーソナルコンピュータ、テレビ受像器、プロジェクター等が挙げられる。それらの一例を図１８〜図２０に示す。
【０１２４】
図１８（Ａ）は携帯電話であり、表示用パネル２７０１、操作用パネル２７０２、接続部２７０３から成り、表示用パネル２７０１には液晶表示装置またはＥＬ表示装置に代表される表示装置２７０４、音声出力部２７０５、アンテナ２７０９などが設けられている。操作パネル２７０２には操作キー２７０６、電源スイッチ２７０７、音声入力部２７０８などが設けられている。本発明は表示装置２９０４に適用することができ、携帯電話を完成させることができる。
【０１２５】
図１８（Ｂ）はビデオカメラであり、本体９１０１、液晶表示装置またはＥＬ表示装置に代表される表示装置９１０２、音声入力部９１０３、操作スイッチ９１０４、バッテリー９１０５、受像部９１０６から成っている。本発明は表示装置９１０２に適用することができ、ビデオカメラを完成させることができる。
【０１２６】
図１８（Ｃ）はモバイルコンピュータ或いは携帯型情報端末であり、本体９２０１、カメラ部９２０２、受像部９２０３、操作スイッチ９２０４、液晶表示装置またはＥＬ表示装置に代表される表示装置９２０５で構成されている。本発明は表示装置９２０５に適用することができ、携帯型情報端末を完成させることができる。
【０１２７】
図１８（Ｄ）はテレビ受像器であり、本体９４０１、スピーカ９４０２、液晶表示装置またはＥＬ表示装置に代表される表示装置９４０３、受信装置９４０４、増幅装置９４０５等で構成される。本発明は表示装置９４０３に適用することができ、テレビ受像器を完成させることができる。
【０１２８】
図１８（Ｅ）は携帯書籍であり、本体９５０１、液晶表示装置またはＥＬ表示装置に代表される表示装置９５０３、記憶媒体９５０４、操作スイッチ９５０５、アンテナ９５０６から構成されており、ミニディスク（ＭＤ）やＤＶＤに記憶されたデータや、アンテナで受信したデータを表示するものである。本発明は表示装置９５０３に適用することができ、携帯書籍を完成させることができる。
【０１２９】
図１９（Ａ）はパーソナルコンピュータであり、本体９６０１、画像入力部９６０２、液晶表示装置またはＥＬ表示装置に代表される表示装置９６０３、キーボード９６０４で構成される。本発明は表示装置９６０１に適用することができ、パーソナルコンピュータを完成させることができる。
【０１３０】
図１９（Ｂ）はプログラムを記録した記録媒体（以下、記録媒体と呼ぶ）を用いるプレーヤーであり、本体９７０１、液晶表示装置またはＥＬ表示装置に代表される表示装置９７０２、スピーカ部９７０３、記録媒体９７０４、操作スイッチ９７０５で構成される。なお、この装置は記録媒体としてＤＶＤ（Ｄｉｇｔｉａｌ Ｖｅｒｓａｔｉｌｅ Ｄｉｓｃ）、ＣＤ等を用い、音楽鑑賞や映画鑑賞やゲームやインターネットを行うことができる。本発明は表示装置９７０２に適用することができ、プレーヤーを完成させることができる。
【０１３１】
図１９（Ｃ）はデジタルカメラであり、本体９８０１、液晶表示装置またはＥＬ表示装置に代表される表示装置９８０２、接眼部９８０３、操作スイッチ９８０４、受像部（図示しない）で構成される。本発明は表示装置９８０２に適用することができ、デジタルカメラを完成させることができる。
【０１３２】
図２０（Ａ）はフロント型プロジェクターであり、投射装置３６０１、スクリーン３６０２で構成される。本発明は投射装置３６０１に適用することができ、フロント型プロジェクターを完成させることができる。
【０１３３】
図２０（Ｂ）はリア型プロジェクターであり、本体３７０１、投射装置３７０２、ミラー３７０３、スクリーン３７０４で構成される。本発明は投射装置３７０２に組み込む液晶表示装置に適用することができ、リア型プロジェクターを完成させることができる。
【０１３４】
尚、図２０（Ｃ）は、図２０（Ａ）及び図２０（Ｂ）中における投射装置３６０１、３７０２の構造の一例を示した図である。投射装置３６０１、３７０２は、光源光学系３８０１、ミラー３８０２、３８０４〜３８０６、ダイクロイックミラー３８０３、プリズム３８０７、液晶表示装置３８０８、位相差板３８０９、投射光学系３８１０で構成される。投射光学系３８１０は、投射レンズを含む光学系で構成される。本実施例は三板式の例を示したが、特に限定されず、例えば単板式であってもよい。また、図２０（Ｃ）中において矢印で示した光路に実施者が適宜、光学レンズや、偏光機能を有するフィルムや、位相差を調節するためのフィルム、ＩＲフィルム等の光学系を設けてもよい。
【０１３５】
また、図２０（Ｄ）は、図２０（Ｃ）中における光源光学系３８０１の構造の一例を示した図である。本実施例では、光源光学系３８０１は、リフレクター３８１１、光源３８１２、レンズアレイ３８１３、３８１４、偏光変換素子３８１５、集光レンズ３８１６で構成される。なお、図２０（Ｄ）に示した光源光学系は一例であって特に限定されない。例えば、光源光学系に実施者が適宜、光学レンズや、偏光機能を有するフィルムや、位相差を調節するフィルム、ＩＲフィルム等の光学系を設けてもよい。
【０１３６】
ここでは図示しなかったが、本発明はその他にもナビゲーションシステムをはじめ冷蔵庫、洗濯機、電子レンジ、固定電話機、ファクシミリなどに組み込む表示装置にも適用することが可能である。このように本発明の適用範囲はきわめて広く、さまざまな製品に適用することができる。
【０１３７】
[実施例１１]
本実施例では、液晶表示装置の画素部に使用するＴＦＴを逆スタガ型ＴＦＴで構成した例を図２１に示す。図２１（Ａ）は、素子基板に設けられた画素部の画素の一つを拡大した上面図であり、図２１（Ａ）において、点線Ａ−Ａ'で切断した部分が、図２１（Ｂ）の画素部の断面構造に相当する。
【０１３８】
図２１（Ｂ）において、８５１は基板であり、まず、基板上に下地絶縁膜（図示しない）を形成する。
【０１３９】
画素部において、画素ＴＦＴはｎチャネル型ＴＦＴで形成されている。基板８５１上に設けられた下地絶縁膜上にゲート電極８５２が形成され、その上に窒化珪素からなる第１絶縁膜８５３ａ、酸化珪素からなる第２絶縁膜８５３ｂが設けられている。また、第２絶縁膜上には、活性層としてソース領域またはドレイン領域となる第２のｎ型不純物領域８５４〜８５６と、チャネル形成領域８５７、８５８と、前記第２のｎ型不純物領域とチャネル形成領域の間に第１のｎ型不純物領域８５９、８６０が形成される。また、チャネル形成領域８５７、８５８は絶縁層８６１、８６２で保護される。絶縁層８６１、８６２及び活性層を覆う第１の層間絶縁膜８６３にコンタクトホールを形成した後、第２のｎ型不純物領域８５４に接続する配線８６４が形成され、第２のｎ型不純物領域８５６にＡｌあるいはＡｇ等からなる画素電極８６５が接続され、さらにその上にパッシベーション膜８６６が形成される。また、８７０は画素電極８６５と隣接する画素電極である。
【０１４０】
なお、本実施例では、画素部の画素ＴＦＴのゲート配線をダブルゲート構造としているが、オフ電流のバラツキを低減するために、トリプルゲート構造等のマルチゲート構造としても構わない。また、開口率を向上させるためにシングルゲート構造としてもよい。
【０１４１】
また、画素部の容量部は、第１絶縁膜及び第２絶縁膜を誘電体として、容量配線８７１と、第２のｎ型不純物領域８５６とで形成されている。
【０１４２】
なお、図２１で示した画素部はあくまで一例に過ぎず、特に上記構成に限定されないことはいうまでもない。
【０１４３】
本発明の熱処理装置は、図２１に示す画素部のＴＦＴを作製する際の熱処理、例えば第２のｎ型不純物領域に含まれる不純物元素の活性化や、ゲッタリングに適用することができる。この熱処理は実施例１または実施例２で説明する熱処理装置を用い、パルス状の輻射を複数回照射して活性化を行う。パルス状の輻射は基板側から照射してもよいし、その逆側から照射してもよい。
【０１４４】
また、実施例７に従えば、本実施例の素子基板から、液晶表示装置を完成させることが可能である。また、こうして作製される液晶表示装置は実施例１０に示した各種電子機器の表示部として用いることができる。
【０１４５】
[実施例１２]
本実施例は、実施例６で示すゲッタリング処理を施した半導体膜を用いて作製されたｎチャネル型ＴＦＴの特性を示す。ＴＦＴはシングルドレイン構造であり、チャネル長１０μm、チャネル幅８μmである。ゲッタリングによる触媒元素の低減効果は、オフ電流値を代用特性として見ることができ、その値が１ｐＡ以下であれば概ね良好であると言える。
【０１４６】
ゲッタリングの条件は、最高加熱温度を６９０〜７３０℃、３００秒間の保持時間として、それを３回繰り返している。
【０１４７】
図２２は９４個のサンプルのオフ電流値の分布（バラツキ）について、累積度数グラフとして示すものである。同グラフ中には、比較の為にファーネスアニール炉を用い、５５０℃４時間のゲッタリング処理を行ったサンプルのデータも示されているが、両者に有意な差はないことが示されている。本発明の熱処理方法によっても良好なゲッタリングが可能であり、しかも従来のファーネスアニール炉を用いたゲッタリングよりも短時間で済んでいる。
【０１４８】
【発明の効果】
本発明の熱処理方法を用いることにより、基板ダメージを与えず、変形させることなく半導体膜に添加した不純物元素の活性化や、ゲッタリングを短時間で行うことが可能となる。また、本発明の熱処理装置は、このような熱処理を可能とする。さらに、このような熱処理方法を用いることにより、半導体装置の生産性を向上させることができる。
【図面の簡単な説明】
【図１】 本発明の熱処理の方法を説明する図。
【図２】 ランプ光源の点滅と冷媒の供給量のタイミングを説明する図。
【図３】 ランプ光源からのパルス状の輻射による被照射領域の温度変化を示すグラフ。
【図４】 本発明の熱処理のメカニズムを説明する図。
【図５】 本発明の熱処理装置の構成を説明する図。
【図６】 本発明の熱処理の方法を説明する図。
【図７】 ＴＦＴの作製工程を説明する断面図。
【図８】 半導体膜の作製方法を説明する断面図。
【図９】 ゲッタリングの方法を説明する断面図。
【図１０】 駆動回路部及び画素部を備えた半導体装置の作製工程を説明する断面図。
【図１１】 駆動回路部及び画素部を備えた半導体装置の作製工程を説明する断面図。
【図１２】 駆動回路部及び画素部を備えた半導体装置の作製工程を説明する断面図。
【図１３】 画素部の構造を説明する上面図。
【図１４】 本発明により得られる液晶表示装置の構成を説明する図。
【図１５】 本発明により得られる発光装置の構成を説明する図。
【図１６】 本発明の熱処理装置の構成を説明する図。
【図１７】 本発明の熱処理方法により活性化処理を行った半導体膜の顕微鏡写真。
【図１８】 半導体装置の一例を示す図。
【図１９】 半導体装置の一例を示す図。
【図２０】 プロジェクターの構成を説明する図。
【図２１】 画素部の上面図及び断面図。
【図２２】 複数のサンプルにおけるＴＦＴのオフ電流の分布を示す累積度数グラフ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device. Heat The present invention relates to a processing apparatus and a heat treatment method using the apparatus. In particular, a heat treatment for recrystallizing and activating a semiconductor film which has been amorphousized by crystallization, ion implantation or ion doping, and gettering of a metal element remaining in the semiconductor film. The present invention relates to a method and a heat treatment apparatus thereof. Furthermore, the present invention relates to a method for manufacturing a semiconductor device using such a heat treatment method.
[0002]
[Prior art]
A crystalline semiconductor film manufactured at a process temperature of 600 ° C. or lower is also called low-temperature polysilicon because silicon is the main raw material. The first application of this crystalline semiconductor film is to use it as an active layer for forming a channel formation region, a source or drain region, etc. of a thin film transistor (hereinafter referred to as TFT). In particular, a technique for manufacturing a liquid crystal display device using the same is attracting attention.
[0003]
The TFT manufacturing technique using the crystalline semiconductor film is characterized by using a laser annealing method, an ion doping method, or the like. By these techniques, n-channel and p-channel TFTs are formed on a large-area glass substrate. Thus, an integrated circuit having a CMOS structure can be formed.
[0004]
However, the TFT has not only an n-type or p-type impurity region that forms the source and drain regions, but also a low-concentration impurity region that forms an LDD (Lightly Doped Drain) in order to reduce leakage current and stabilize characteristics. Need to form. In addition, it is necessary to dope an impurity element of one conductivity type in order to control the threshold voltage. These controls are performed by an ion doping method in which all of the generated ion species are acceleratedly implanted without mass separation and an activation process thereafter.
[0005]
As a method for activating the impurity after doping, furnace annealing, laser annealing, RTA (Rapid Thermal Annealing), or the like can be employed. 10 which is a relatively high concentration as a dose. ¹⁵ / Cm ² The source and drain regions to which a certain degree of implantation is performed require a certain temperature and time in order to activate the added impurity element and increase the conductivity. Since the laser annealing method melts a semiconductor film, its controllability and reproducibility are problematic, and it is considered difficult to introduce it into a mass production process. Although furnace annealing is a batch process, it is considered to be compatible with the mass production process. However, when the processing temperature is lowered, the activation rate decreases and the processing time becomes long.
[0006]
In the crystallization technique, the laser annealing method enables formation of a crystalline semiconductor film on a glass substrate. However, since the reaction is in a non-equilibrium state, the crystal has a small particle size and a large number of defects. The direct control factors in the laser annealing method are very limited, such as the energy density of laser light, the number of irradiations, and the substrate heating temperature, and the application range is also limited. For example, the energy density is 250 to 400 mJ / cm. ² Is within an appropriate range, and if it is out of the range, only an amorphous structure can be obtained.
[0007]
On the other hand, as a technique for obtaining a high-quality crystal, a technique for performing crystallization by adding a metal element is disclosed in JP-A-7-183540. As the metal element, nickel, palladium, lead or the like is used. The addition method can be performed by various methods such as plasma treatment, vapor deposition, ion implantation, solution coating, and sputtering. The heat treatment for crystallization can be performed by heat treatment at 500 to 600 ° C., preferably 550 ° C. for 4 hours. However, this method often requires gettering because a metal element remains in the crystalline semiconductor film. Many metal elements are known to form deep levels in the forbidden band in semiconductors, become lifetime killer, and increase the leakage current at the junction.
[0008]
Gettering using phosphorus is a method capable of segregating the metal element in the phosphorus-added region. For the gettering, a furnace annealing furnace is used, and typically heat treatment at 450 to 600 ° C. for about 12 hours is required. Thereby, a metallic element can be segregated to a phosphorus addition area | region.
[0009]
[Problems to be solved by the invention]
One of the most promising fields of application of TFTs manufactured in this way is the field of flat panel displays typified by liquid crystal display devices. In this field, it is required to increase the size of the substrate in the manufacturing process in order to improve productivity. The size varies, but as an example 960x1100mm ² Is considered, and one side reaches 1000 mm. Such a requirement is not limited to liquid crystal display devices, but is a common problem in large-area integrated circuits formed using TFTs on a glass substrate.
[0010]
In order to improve productivity, it is necessary to reduce the number of TFT manufacturing processes and the processing time. In that case, it is considered that the production annealing cannot be improved with a furnace annealing apparatus premised on batch processing. If the furnace annealing apparatus is increased in size, not only the installation area is increased, but also the power consumption increases because the inside of the large-capacity furnace is uniformly heated.
[0011]
In view of productivity, the RTA method is considered a suitable method. The RTA method can be heated to a high temperature in a short time, and even a single wafer type has a potentially higher processing capacity than the furnace annealing method. However, it is necessary to increase the heating temperature instead of shortening the heating time, and it is necessary to heat the glass to a strain point or higher than the softening point in order to obtain a desired effect in the activation or gettering treatment. For example, the glass substrate is bent and deformed by its own weight only by performing a heat treatment at 800 ° C. for 60 seconds for the gettering process.
[0012]
An object of the present invention is to solve the above problems, and in a manufacturing process of a semiconductor device using a substrate having low heat resistance such as glass, an impurity added to the semiconductor film by a short heat treatment without deforming the substrate A method for performing heat treatment necessary for element activation and gettering treatment of a semiconductor film, a heat treatment apparatus that enables such heat treatment, and a method for manufacturing a semiconductor device using the heat treatment apparatus are provided. Objective.
[0013]
[Means for Solving the Problems]
In view of the above-described problems, the present invention provides heat treatment for gettering and activation of a semiconductor film formed on a substrate having low heat resistance such as glass without causing damage due to heat such as deformation of the substrate. A method capable of being performed in a short time and a heat treatment apparatus therefor are provided.
[0014]
The mechanism of gettering the metal element by phosphorus added without mass separation using phosphine in the semiconductor film formed on the substrate by ion doping can be estimated as follows. When phosphorus is selectively added to the semiconductor film, the added region (gettering region) becomes amorphous. Next, the gettering region is crystallized from amorphous by heating the semiconductor film. At this time, phosphorus added to the gettering region is located between lattices formed by the semiconductor film. In addition, in a region where phosphorus is not added by heat treatment (a gettering region), a compound formed by a metal element (referred to as a metal compound) is disconnected (this state is referred to as release). Subsequently, the metal element moves (this state is called diffusion), and the metal element and phosphorus are combined (this state is called trapping). Thus, it is considered that the metal element can be removed or reduced in the gettering region.
[0015]
Gettering includes a process of releasing a metal element from a metal compound in the gettering region, diffusion of the metal element, and capturing of the metal element by phosphorus in the gettering region. The release energy of the metal element is estimated to be about several hundred degrees Celsius, and it has been found that it can be easily released by heat treatment at around 500 degrees Celsius. On the other hand, when the heat treatment is performed at a high temperature, the diffusion rate of the metal element is increased, but the metal element is hardly gettered. The reason for this is considered to be that when the temperature is raised, phosphorus is taken in between the lattices and cannot be bonded to the metal element.
[0016]
For this reason, in order to improve the gettering effect, it is necessary to promote the diffusion of the metal element while performing the heat treatment at a low temperature. The method is characterized in that the gettering region is heated to a temperature higher than that of the gettering region by repeating the radiation of the lamp light source in pulses. For this purpose, the structure of the gettering region and the gettering region is devised, Covered A light absorption film is formed on the gettering region. The light absorption film may be a gate electrode. For example, a tantalum nitride film can be used as a part of the gate electrode. The tantalum nitride film is heated by receiving radiation from the lamp light source.
[0017]
By heating the gettering region to a relatively high temperature, the metal compound is easily released and can diffuse into the gettering region. Then, the gettering region to which phosphorus is added can be reached and segregated in that region. At this time, a high gettering effect can be obtained by heating so that phosphorus is taken in between the lattices of the silicon network and is not bonded in a 4-coordination manner, that is, activation does not proceed so much.
[0018]
The reason for heating the semiconductor film that is the object to be processed by irradiating the lamp light source in a pulsed manner multiple times is that the gettering region is rapidly heated before the heat is transmitted to the glass substrate or the gettering region. This is to enable rapid cooling. Of course, it is possible to use laser light as the light source, but considering the irradiation time optimal for activation and gettering, it is preferable to use a halogen lamp or the like as the light source because the irradiation area can be easily enlarged. . The present invention is characterized in that gettering and activation are performed in this way.
[0019]
As described above, the heat treatment method of the present invention is a heat treatment method in which the object to be processed is heated by irradiating the pulsed light of the lamp light source in a plurality of times, and the radiation per time of the lamp light source is It lasts for 0.1 to 20 seconds and is characterized by repeating radiation from the lamp light source a plurality of times. Or it is characterized by repeating the radiation from a lamp light source in pulses so that the maximum temperature holding time of the object to be processed is 0.5 to 5 seconds. Further, by increasing or decreasing the supply amount of the refrigerant as the lamp light source blinks, the heat treatment effect of the semiconductor film to be processed is enhanced and the substrate is prevented from being damaged by heat.
[0020]
A heat treatment apparatus according to the present invention that enables such a heat treatment method includes a lamp light source, a power source that blinks the lamp light source in a pulsed manner, a stage on which a substrate is placed, and radiation from the lamp light source to an object to be processed. It is characterized by comprising a process chamber capable of irradiating and means for supplying a refrigerant to the process chamber and increasing or decreasing its supply amount.
[0021]
As the lamp light source, a halogen lamp, a metal halide lamp, a xenon lamp, a high-pressure mercury lamp, a high-pressure sodium lamp, an excimer lamp, or the like can be applied.
[0022]
Further, another configuration of the heat treatment apparatus of the present invention is capable of irradiating an object to be processed with a lamp light source, a power source for blinking the lamp light source in a pulsed manner, a stage on which a substrate is placed, and radiation from the lamp light source. A processing chamber, a transfer means capable of moving the stage in one direction in the processing chamber, and a means for supplying a refrigerant to the processing chamber as the lamp light source blinks and for increasing or decreasing the supply amount. It is characterized by.
[0023]
A method for manufacturing a semiconductor device of the present invention using the heat treatment method as described above includes a step of forming a semiconductor film on a light-transmitting substrate, a step of forming a second insulating film on the semiconductor film, and a second insulating film. A step of forming a light-absorbing first conductive film thereon, a step of forming a light-reflective second conductive film on the first conductive film, and a semiconductor film doped with one conductivity type impurity A step of forming a semiconductor region of a mold and a step of activating a semiconductor region of one conductivity type by irradiating pulsed radiation emitted from a lamp light source a plurality of times from the translucent substrate side. .
[0024]
In another structure, a first step of forming an amorphous semiconductor film on one main surface of the light-transmitting substrate, and a crystal element is formed by adding a metal element to the amorphous semiconductor film and then crystallizing the amorphous semiconductor film. A second step of forming, a third step of forming a conductive film overlying a part of the crystalline semiconductor film above the crystalline semiconductor film, and a semiconductor region in which phosphorus is added to the crystalline semiconductor film And a fifth step of intermittently repeating radiation from the lamp light source a plurality of times from a surface opposite to the one main surface of the translucent substrate.
[0025]
The object to be processed is held in a refrigerant, and irradiation from the lamp light source is repeated several times so that the maximum temperature of the object to be processed is 600 to 800 ° C. and the holding time is 30 to 600 seconds. The processed material can be efficiently heated to complete the heat treatment. At this time, by matching the wavelength of the electromagnetic wave radiated from the lamp light source with the absorption band of the object to be processed, only the object to be processed can be selectively heated. Specifically, heat treatment can be performed on a semiconductor film formed over a glass substrate having a strain point of 700 ° C. or lower.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The concept of the heat treatment apparatus of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing a configuration of a heat treatment apparatus according to the present invention. A processing chamber 101 is preferably made of quartz and includes a lamp light source 102 as means for heating an object 106 to be processed. The lamp light source 102 is provided outside the processing chamber 101, and is provided with a reflecting plate 103 for efficiently irradiating the workpiece 106 with radiant heat. In addition, a refrigerant inlet 104 is provided for cooling the object to be processed 106, and the refrigerant is also introduced at the same time when heating is performed. As the refrigerant 105, an inert gas such as nitrogen or helium, or a liquid can be used. Such a refrigerant is preferably highly purified. In any case, the radiant heat of the lamp light source 102 of Absorption rate But A small medium is desirable.
[0027]
The lamp light source is turned on in pulses by its power supply and control circuit. FIG. 2 is a diagram illustrating a method of controlling the workpiece heated by the lamp light source and the flow rate of the refrigerant flowing into the processing chamber. Initially, the workpiece placed at room temperature is rapidly heated by a lamp light source. During the temperature raising period, heating is performed to a set temperature (for example, 1100 ° C.) at a temperature raising rate of 100 to 200 ° C./second. For example, if heating is performed at a temperature rising rate of 150 ° C./second, heating can be performed to 1100 ° C. in less than 7 seconds. Thereafter, the lamp is kept at the set temperature for a certain time, and the lamp light source is turned off. The holding time is 0.5 to 5 seconds. Therefore, the continuous lighting time of the lamp light source is 0.1 seconds or more and does not exceed 20 seconds. The refrigerant decreases the flow rate as the lamp light source is turned on, and increases the flow rate at which the lamp light source is turned off. The temperature drop rate is controlled by controlling the flow rate at this time. The cooling rate is 50 to 150 ° C./second. For example, when cooling is performed at a rate of 100 ° C./second, the cooling can be performed from 1100 ° C. to 300 ° C. in 8 seconds.
[0028]
The present invention is characterized in that such heating and cooling cycles are repeated a plurality of times. By shortening the actual heating time and irradiating light selectively absorbed by the semiconductor film from the lamp light source, it is possible to selectively heat only the semiconductor film without heating the substrate as much. It becomes. The pulsed radiation as shown in FIG. 2 heats the semiconductor film, stops heating before the heat propagates to the substrate side, and cools it from the surroundings with a coolant, so that the temperature of the substrate does not increase so much. Therefore, it is possible to prevent the deformation of the substrate, which has been a problem in the conventional RTA apparatus.
[0029]
As shown in FIG. 4, the object to be processed has a semiconductor film 203 formed on a light-transmitting substrate 201 such as glass, and a conductive layer is further provided thereon. This conductive layer may be a single layer, but preferably has a structure in which a light-absorbing first conductive film 205 and a heat-conductive second conductive film 206 are provided. In addition, a first insulating film 202 and a second insulating film 204 may be formed on the substrate side of the semiconductor film 203 and the opposite surface thereof.
[0030]
Pulsed radiation from the lamp light source is emitted from the substrate 201 side. The pulsed radiation is repeatedly and repeatedly emitted in a pulsed manner as will be described with reference to FIG. The substrate is filled with a refrigerant 207 using nitrogen gas or the like. As shown in the graph inserted in FIG. 4, the temperature distribution of the object to be processed by the irradiation of the pulsed radiation is different in the regions A and B.
[0031]
A part of the pulsed radiation is absorbed by the semiconductor film 203 and converted into heat, except for what is reflected at each interface. Light reaching the light-absorbing first conductive film 205 in the B region is absorbed there and converted into heat. A part of the generated heat is transmitted to the semiconductor film 203 through the second insulating film 204. On the other hand, the region A transmits from the second insulating film 204 to the space filled with the refrigerant 207. Therefore, the temperature rising in the A region and the B region is different even if pulsed radiation is repeated with the same intensity. That is, a temperature gradient can be generated in the semiconductor film in a direction parallel to the substrate surface (referred to as a horizontal direction for convenience).
[0032]
Such a temperature gradient can be effectively used when gettering the channel formation region using the B region as a channel formation region and the A region as an impurity semiconductor region. Specifically, when an n-type semiconductor region doped with phosphorus is provided in the A region, gettering that segregates metal elements contained in the B region into the A region by repeating pulsed radiation as shown in FIG. Can do.
[0033]
In particular, this gettering action can be applied for the purpose of removing the metal element from the channel formation region after crystallization by adding a metal element.
[0034]
In any case, when a conductive film is formed over the semiconductor film, the region (B region in FIG. 4) becomes higher in temperature than the other regions (A region in FIG. 4). The mode shown in FIG. 4 can be seen by being replaced with a semiconductor film, a gate insulating film (second insulating film 204), and a gate electrode (first conductive film 205, second conductive film 206) formed over a glass substrate. . In that case, when the pixel portion and the driver circuit portion provided in the periphery thereof are formed on the same substrate as in a liquid crystal display device, the effect of heat treatment may not be obtained uniformly. The density of TFTs formed is different between the pixel portion and the drive circuit portion, and the latter is formed at a much higher density. In that case, the drive circuit section becomes hot even when pulsed radiation of the same intensity is repeated.
[0035]
As shown in FIGS. 6A to 6C, as a method for obtaining a uniform heat treatment effect, means for partially attenuating the light intensity on the side on which pulsed radiation from the lamp light source is incident is used. . FIG. 6A shows a translucent film formed of a thin metal film such as chromium on the side where pulsed radiation 406 is incident on a light-transmitting substrate 401 on which a pixel portion 402 and a driver circuit portion 403 are formed. 405 is the position of the drive circuit 403 In An example in which pulsed radiation is attenuated is also shown. FIG. 6B shows an example in which a slit portion 407 is provided instead of the semi-transmissive film 405, and pulsed radiation can be similarly attenuated. FIG. 6C shows an example in which an opening 410 is formed in accordance with the pixel portion and a slit portion 409 is formed in accordance with the driver circuit portion on the metal mask 408. The rate at which the pulsed radiation is attenuated is appropriately set, and can be easily adjusted by adjusting the transmittance of the semipermeable membrane and the aperture ratio of the slit portion.
[0036]
As described above, by using the present invention, a method for activating an impurity element added to a semiconductor film or performing a gettering process on a semiconductor film by a short heat treatment even when a substrate having low heat resistance such as glass is used. And such heat treatment may be possible. Such heat treatment can be incorporated into the manufacturing process of the semiconductor device.
[0037]
【Example】
[Example 1]
As an example of the heat treatment apparatus of the present invention, a configuration of a single wafer heat treatment apparatus is shown in FIG. The processing chamber 301 is made of quartz, and a cooling means 305 by water cooling is provided around it. A reflection plate 303 is added to the lamp light source 302 so that the pulsed radiation is efficiently diffused to the workpiece 317. In the case of using a rod-shaped halogen lamp, a plurality of lamps are installed as shown in FIG. 5 so that the object 317 is irradiated with pulsed radiation with uniform intensity. Radiation (for example, including a wavelength of 0.5 μm to 3 μm) is turned on in pulses by the light source control unit 304.
[0038]
Nitrogen gas is supplied as a refrigerant from the refrigerant supply source 306 to the processing chamber 301. The amount of nitrogen gas supplied to the processing chamber 301 can be controlled by the flow rate control means 307. The refrigerant supplied to the processing chamber is discharged to the outside through the exhaust port 311 so that the processing chamber is always filled with clean nitrogen gas. The temperature detector 309 is a temperature sensor 308 using a radiation thermometer, and is provided to monitor the temperature of an object to be processed that is heated by pulsed radiation from a lamp light source. For this purpose, the temperature sensor 308 is attached to a part of the stage 318.
[0039]
The control unit 310 controls the operation of the light source control unit 304 and the flow rate control unit 307, and can synchronize the blinking of the lamp light source and the increase / decrease in the supply amount of the refrigerant as shown in FIG. Further, the control means 310 receives a signal from the temperature detector 309, detects the temperature of the object to be processed, and determines whether there is any abnormality.
[0040]
The object to be processed is placed on the substrate holder 316 in the load / unload chamber 315 and is transferred to the processing chamber 301 by the transfer means 314 in the transfer chamber 313. A gate valve 312 is provided between the transfer chamber 313 and the processing chamber 301 so that the processing chamber 301 is filled with a refrigerant during heat treatment.
[0041]
In order to activate the impurity element added to the semiconductor film, the following procedure is used. It is assumed that the semiconductor film is formed on one main surface of the glass substrate. The object to be processed on which the semiconductor film set in the load / unload chamber 315 is formed is taken out of the substrate holder 316 by the transfer means 314 in the transfer chamber 313 and set on the stage 318 in the process chamber 301. At this time, the workpiece is set so that the semiconductor film is positioned on the surface opposite to the lamp light source 302. That is, the radiation is incident on the semiconductor film through the glass substrate.
[0042]
Thereafter, the gate valve 312 is closed. Volume 18 × 30 × 1.5cm ^Three In order to replace the processing chamber with nitrogen gas as the refrigerant, the refrigerant is constantly supplied to the processing chamber at a rate of 1 to 2 liters / min by the flow rate control means 307. Increase the supply rate of 10-20 liters / min and hold for a certain time.
[0043]
The supply amount of nitrogen gas is reduced to 2 liters / min almost simultaneously with the lighting of the lamp light source. Heating by the lamp light source is considered to be based on the temperature detected by the temperature sensor 308, and is heated to 1100 ° C. at a rate of 100 to 200 ° C./second. Thereafter, the temperature is controlled to be maintained for 0.5 to 5 seconds. Cooling is performed by turning off the lamp light source and increasing the flow rate of nitrogen gas to 10 liters / min. The cooling rate is 50 to 150 ° C./second and the cooling is performed to 300 to 400 ° C. Furthermore, as shown in FIG. 2, a holding period (2) of about 5 to 60 seconds can be provided in that state. FIG. 3 shows a graph plotting the time change of the temperature detected by the temperature sensor. The data in FIG. 3 shows two data when held at 1100 ° C. for 4.2 seconds and when held for 0.75 seconds. Tables 1 and 2 are numerical data corresponding to the graph of FIG. 3, and show the temperature and the rate of change of each measurement time.
[0044]
[Table 1]

[0045]
[Table 2]

[0046]
The same applies to both the case where the impurity element added to the semiconductor film is activated and the case where gettering is performed.However, by repeatedly irradiating such pulsed radiation a plurality of times, the activation rate can be increased without bending the substrate. It is possible to improve. Also, gettering is possible.
[0047]
[Example 2]
As another example of the heat treatment apparatus of the present invention, FIG. 16 shows a configuration of an in-line heat treatment apparatus corresponding to a large area substrate. The processing chamber 1301 is made of quartz, and a cooling means 1305 by water cooling is provided around it. A reflection plate is added to the lamp light source 1302 so as to collect light by the optical lens 1324 and irradiate the object to be processed. A rod-like halogen lamp is used for the lamp light source 1302, and a cylindrical lens can be used as the optical lens 1324, so that linear light can be irradiated to the object to be processed. The lamp light source is turned on in pulses by a light source control unit 1304.
[0048]
Nitrogen gas or helium gas is supplied as a refrigerant from the refrigerant supply source 1306 to the processing chamber 1301. The supply amount of nitrogen gas to the processing chamber 1301 can be controlled by the flow rate control means 1307. The refrigerant supplied to the processing chamber is discharged to the outside through the exhaust port 1311 so that the processing chamber is always filled with clean nitrogen gas.
[0049]
The control unit 1310 controls the operation of the light source control unit 1304, the flow rate control unit 1307, the workpiece 1317 in the processing chamber, and the transfer unit 1323 of the stage 1318. As shown in FIG. Increase / decrease is synchronized, and the timing at which the stage 1318 moves is controlled.
[0050]
The object to be processed is placed on the stage and is set on the substrate holder 1316 in the load chamber 1315. Then, it is transferred to the processing chamber 1301 by the transfer means 1314 in the carry-in chamber 1313. A gate valve 1312 is provided between the carry-in chamber 1313 and the processing chamber 1301, and the processing chamber 1301 is filled with a refrigerant during heat treatment.
[0051]
The workpiece 1317 placed on the stage 1318 is irradiated with pulsed radiation from the lamp light source 1302 while being moved by the transfer means 1323 of the processing chamber 1301. Thus, the entire surface of the object to be processed can be heat-treated. After the heat treatment, the workpiece 1317 is moved to the carry-out chamber 1320 together with the stage 1318 by the transfer means 1321, and then stored in the substrate holder 1326 in the unload chamber 1322.
[0052]
The heating method is performed in the same manner as in the first embodiment. However, in the case of the apparatus configured as shown in FIG. 16, the object to be processed moves, so it is necessary to coordinate the pulsed radiation with the timing of the movement. Of course, the flow rate of the nitrogen gas used as the refrigerant is similarly controlled. The workpiece is moved during the holding period (2) shown in FIG. 2, and is moved stepwise. The movement distance may be set appropriately, but the movement is performed so that the same region of pulsed radiation is irradiated multiple times.
[0053]
With such a structure, heat treatment of a large-area substrate can be performed without enlarging the apparatus so much. The same applies to the case where the impurity element added to the semiconductor film is activated or gettering, but it is possible to activate without bending the substrate by repeatedly irradiating such pulsed radiation a plurality of times. It is possible to improve the rate. Also, gettering is possible.
[0054]
[Example 3]
Next, an example of a method for manufacturing a TFT using the present invention will be described with reference to FIGS. In FIG. 7A, a crystalline semiconductor film containing silicon as a main component is formed over a light-transmitting substrate 501 made of aluminoborosilicate glass or barium borosilicate glass. The crystalline semiconductor film can be obtained by crystallizing an amorphous semiconductor film by a laser annealing method. Further, the heat treatment apparatus described in Embodiment 1 or Embodiment 2 can be used to irradiate pulsed radiation. The thickness of the crystalline semiconductor film is formed in the range of 25 to 80 nm. In manufacturing the TFT, the semiconductor films 503 to 505 divided into islands are formed by etching to a predetermined size for element isolation. In addition, between the substrate 501 and the semiconductor film, a first insulating film 502 in which one or a plurality selected from silicon nitride, silicon oxide, and silicon nitride oxide is combined is formed with a thickness of 50 to 200 nm.
[0055]
As an example of the first insulating film 502, SiH is formed by plasma CVD. _Four And N ₂ A silicon oxynitride film is formed to a thickness of 50 to 200 nm using O. As another form, SiH is formed by plasma CVD. _Four And NH _Three And N ₂ A silicon oxynitride film made of O is 50 nm, SiH _Four And N ₂ A two-layer structure in which a silicon oxynitride film manufactured from O is stacked to a thickness of 100 nm, or a two-layer structure in which a silicon oxide film manufactured using a silicon nitride film and TEOS (Tetraethyl Ortho Silicate) is stacked may be used. .
[0056]
A silicon oxide film 506 is formed with a thickness of 100 nm on the semiconductor films 503 to 505 by a plasma CVD method. Further, a resist mask 507 is formed as shown in FIG. 7A, and an n-type impurity (donor) is added by an ion doping method to form a first n-type semiconductor region 508 in the semiconductor film 504. Typically, phosphorus is added as an n-type impurity (donor), and the average value of the phosphorus concentration of the first n-type semiconductor region 508 is 1 × 10. ¹⁷ ~ 1x10 ¹⁹ / Cm ^Three The range. Here, the silicon oxide film 506 is used as a mask for controlling the phosphorus concentration.
[0057]
Accordingly, after doping, the silicon oxide film 506 is removed with hydrofluoric acid or the like, and a second insulating film 509 is formed with a thickness of 80 nm. The second insulating film 509 is used as a gate insulating film and is formed using a plasma CVD method or a sputtering method. As the second insulating film 509, SiH _Four And N ₂ O to O ₂ A silicon oxynitride film formed by adding Si can reduce a fixed charge density in the film and is a preferable material for a gate insulating film. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and an insulating film such as a silicon oxide film or a tantalum oxide film may be used as a single layer or a stacked structure.
[0058]
Then, a first conductive film and a second conductive film for forming a gate electrode are formed over the second insulating film 509. The first conductive film is formed using a light-absorbing conductive film. An example of such a conductive film is tantalum nitride, which is formed to a thickness of 50 to 100 nm. The second conductive film is formed to a thickness of 100 to 300 nm using a refractory metal such as tungsten or molybdenum. These materials are stable even in heat treatment at 400 to 600 ° C. in a nitrogen atmosphere, and the resistivity does not increase remarkably.
[0059]
Next, as shown in FIG. 7B, the first conductive film and the second conductive film are etched to form gate electrodes 510 to 512 (consisting of first conductive films 510a to 512a and second conductive films 510b to 512b). Form. Although there is no limitation on the etching method, it is preferable to use an ICP (Inductively Coupled Plasma) etching method. At this time, the etching gas is CF. _Four And Cl ₂ The mixed gas is used.
[0060]
After the gate electrode is formed, the semiconductor films 503 to 505 are doped with n-type impurities (donors) by ion doping using the gate electrode as a mask. Thus, second n-type semiconductor regions 513 to 515 are formed. The average phosphorus concentration of the second n-type semiconductor regions 513 to 515 is 1 × 10 ¹⁶ ~ 1x10 ¹⁸ / Cm ^Three However, it is added at a lower concentration than the first n-type semiconductor region. Accordingly, the first n-type semiconductor region formed in the semiconductor film 504 remains as it is.
[0061]
Subsequently, as shown in FIG. 7C, resist masks 516 and 517 are formed over the semiconductor films 503 and 505, and then an n-type impurity (donor) is doped again by an ion doping method. The average value of the phosphorus concentration in the third n-type semiconductor regions 518 to 520 is 1 × 10. ²⁰ ~ 1x10 ^{twenty one} / Cm ^Three The range. In this state, the first n-type semiconductor region 508 in the semiconductor film 504 remains in a region overlapping with the gate electrode. Further, the second n-type semiconductor region 515 in the semiconductor film 505 remains in a region overlapping with the mask 517.
[0062]
Then, as shown in FIG. 7D, a resist mask 521 is formed, and a p-type impurity (acceptor) is doped into the semiconductor film 503 forming the p-channel TFT. Typically, boron (B) is used. The impurity concentration of the first p-type semiconductor region 522 is 2 × 10. ²⁰ ~ 2x10 ^{twenty one} / Cm ^Three Then, boron of 1.5 to 3 times the maximum phosphorus concentration contained is added to reverse the conductivity type to p-type.
[0063]
Next, in FIG. 7E, heat treatment for activating the added impurity is performed. This heat treatment is performed by irradiating pulsed radiation a plurality of times using the heat treatment apparatus described in Example 1 or Example 2. Since radiation is emitted from the substrate side, even if the first n-type semiconductor region overlapping with the gate electrode is formed, the p-type and n-type impurity elements can be reliably activated including the region.
[0064]
Through the above steps, each semiconductor film is doped with an impurity for forming a source or drain region and an LDD region, and the process until activation is completed. After that, as shown in FIG. 7F, a protective insulating film 526 made of a silicon nitride film or a silicon oxynitride film is formed by a plasma CVD method. Then, heat treatment is performed at 350 to 450 ° C., preferably 410 ° C. The semiconductor film is hydrogenated by releasing hydrogen in the first interlayer insulating film at this temperature. Therefore, it is more suitable to perform this heat treatment in a furnace annealing furnace or a clean oven.
[0065]
The interlayer insulating film 527 is formed of an organic insulating material such as polyimide or acrylic to flatten the surface. Of course, a silicon oxide film formed using TEOS (Tetraethyl Ortho Silicate) by a plasma CVD method may be applied, but from the viewpoint of improving flatness, it is desirable to use the organic material.
[0066]
Next, contact holes are formed, and source or drain wirings 528 to 533 are formed using aluminum (Al), titanium (Ti), tantalum (Ta), or the like.
[0067]
The p-channel TFT 540 manufactured by the above process includes a channel formation region 523 and a first p-type semiconductor region 522 functioning as a source or drain region. The n-channel TFT 541 includes a channel formation region 524, a first n-type semiconductor region 508 overlapping with the gate electrode 511, and a third n-type semiconductor region 519 functioning as a source or drain region. The first n-type semiconductor region is an LDD region, and is formed so as to overlap with the gate electrode, thereby relaxing the high electric field region formed at the drain end and preventing the deterioration of the TFT due to the hot carrier effect. In the n-channel TFT 542, a second n-type semiconductor region 515 and a third n-type semiconductor region 520 functioning as a source or drain region are formed outside the channel formation region 525 and the gate electrode 512. The second n-type semiconductor region 515 is an LDD region and can reduce the off-current of the TFT. In the process shown in this embodiment, an optimum dimension can be set in order to reduce the off-current value.
[0068]
Through the above steps, a CMOS TFT in which an n-channel TFT and a p-channel TFT are complementarily combined can be obtained. In the process shown in this embodiment, an LDD can be designed in consideration of the characteristics required for each TFT, and can be made separately in the same substrate. Such a CMOS TFT makes it possible to form a drive circuit of a display device driven by active matrix. In addition, such an n-channel TFT or a p-channel TFT can be applied to a transistor forming the pixel portion. Further, it can be used as a TFT that realizes a thin film integrated circuit that replaces an LSI manufactured on a conventional semiconductor substrate. Although the TFT is shown here with a single gate structure, it is of course possible to adopt a multi-gate structure in which a plurality of gate electrodes are provided.
[0069]
In such a TFT manufacturing process, the heat treatment apparatus of the present invention can be used for activation. The heat treatment method of the present invention can be activated in a short time without damaging the substrate.
[0070]
[Example 4]
In this embodiment, as an example of a method for manufacturing a semiconductor device using the heat treatment apparatus of the present invention, a method for manufacturing a driver circuit and a pixel portion including an n-channel TFT and a p-channel TFT on the same substrate is shown in FIGS. 12 will be described.
[0071]
First, as shown in FIG. 10A, a first insulating film 602 is formed on a substrate 601 by a plasma CVD method using SiH. _Four And NH _Three And N ₂ A silicon oxynitride film made of O is 50 nm, SiH _Four And N ₂ A two-layer structure in which 100 nm of silicon oxynitride films made from O are stacked is formed. The substrate used here is suitably an alkali-free glass substrate such as aluminoborosilicate glass or barium borosilicate glass, and a substrate having a thickness of about 0.5 to 1.1 mm is used.
[0072]
The semiconductor films 603 to 606 formed thereon have a thickness of 40 nm, and polycrystalline silicon obtained by crystallizing amorphous silicon deposited by plasma CVD or low pressure CVD using laser annealing or solid phase growth. Is used. Alternatively, the heat treatment apparatus described in Example 1 or Example 2 can be used to obtain the same effect by crystallizing by pulsed radiation. Then, it is divided into islands through a light exposure process. Hereinafter, in this embodiment, a description will be given on the assumption that a p-channel TFT is formed in the semiconductor film 603 and an n-channel TFT is formed in the semiconductor films 604 and 605. The semiconductor film 606 is provided to form an auxiliary capacitor.
[0073]
A second insulating film 607 is formed with a thickness of 75 nm to cover these semiconductor films to form a gate insulating film. The second insulating film is a silicon oxide using TEOS (Tetraethyl Ortho Silicate) as a raw material by plasma CVD, or SiH _Four And N ₂ It is formed of silicon oxynitride using O as a raw material.
[0074]
Next, as illustrated in FIG. 10B, a first conductive film 608 and a second conductive film 609 are formed over the second insulating film. The first conductive film 608 is formed using tantalum nitride, and the second conductive film is formed using tungsten. This conductive film is for forming a gate electrode, and the thicknesses thereof are 30 nm and 300 nm, respectively.
[0075]
Thereafter, as shown in FIG. 10C, a resist pattern 610 for forming gate electrodes and data lines is formed by a light exposure process. A first etching process is performed using this resist pattern. Although there is no limitation on the etching method, an ICP (Inductively Coupled Plasma) etching method is preferably used. CF as an etching gas for tungsten and tantalum nitride _Four And Cl ₂ The plasma is generated by applying 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 0.5 to 2 Pa, preferably 1 Pa. At this time, 100 W RF (13.56 MHz) power is also applied to the substrate side (stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ When tungsten is mixed, tungsten and tantalum nitride can be etched at the same rate.
[0076]
Under the above etching conditions, the end portion can be tapered by the shape of the resist mask and the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is set to 15 to 45 °. In order to etch without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface on which the second insulating film is exposed by the overetching process is etched by about 20 to 40 nm. Thus, the first shape electrodes 611 to 614 (tantalum nitride 611a to 614a and tungsten 611b to 614b) and the first shape wiring 615 tantalum nitride (615a and tungsten 615b) made of tantalum nitride and tungsten are formed by the first etching process. .
[0077]
Then, a first doping process is performed to dope the semiconductor film with an n-type impurity (donor). The method is performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁴ / Cm ² Do as. As the impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In this case, the first shape electrodes 611 to 614 serve as masks for the element to be doped, the acceleration voltage is appropriately adjusted (for example, 20 to 60 keV), and the first impurity region is formed by the impurity element that has passed through the second insulating film. 616 to 619 are formed. The phosphorus (P) concentration in the first impurity regions 616 to 619 is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} / Cm ^Three To be in the range.
[0078]
Subsequently, a second etching process is performed as shown in FIG. The ICP etching method is used for etching, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ And 500 W of RF power (13.56 MHz) is supplied to the coil-type electrode at a pressure of 1 Pa to generate plasma. 50 W RF (13.56 MHz) power is applied to the substrate side (stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the tungsten film is anisotropically etched to leave the tantalum nitride film as the first conductive film. Thus, second shape electrodes 620 to 623 (tantalum nitride 620a to 623a, tungsten 620b to 623b) and second shape wiring 624 tantalum nitride (624a, tungsten 624b) made of tantalum nitride and tungsten are formed by the second etching process. . The portion of the second insulating film not covered with tantalum nitride is etched and thinned by about 10 to 30 nm by this etching process.
[0079]
The dose amount in the second doping process is smaller than that in the first doping process, and the n-type impurity (donor) is doped under the condition of a high acceleration voltage. For example, the acceleration voltage is 70 to 120 keV and 1 × 10 ¹³ / Cm ² The second impurity region is formed on the inner side of the first impurity region. Doping is performed by passing the exposed tantalum nitride 620a to 623a and adding an impurity element to the lower semiconductor film. Thus, second impurity regions 625 to 628 overlapping with the tantalum nitrides 620a to 623a are formed. This impurity region varies depending on the film thickness of tantalum nitride 620a to 623a, but its peak concentration is 1 × 10 5. ¹⁷ ~ 1x10 ¹⁹ / Cm ^Three It varies in the range. The depth distribution of the n-type impurity in this region is not uniform and is formed with a certain distribution.
[0080]
Next, as shown in FIG. 11B, a resist mask 629 covering the second shape electrode 621 is formed by an optical exposure process, and the exposed tantalum nitride film of the second shape electrode is selectively etched. The etching gas is Cl ₂ And SF ₆ The mixed gas is used. In this way, third shape electrodes 630 to 632 in which the end portions of tungsten and tantalum nitride coincide are formed. At the same time, the data line may be processed to form the third shape wiring 633 in the same manner.
[0081]
Then, resist masks 634 and 635 are formed as shown in FIG. 11C, and the semiconductor films 603 and 606 are doped with p-type impurities (acceptors). Typically, boron (B) is used. The impurity concentration of the first p-type semiconductor regions 636 and 637 is 2 × 10. ²⁰ ~ 2x10 ^{twenty one} / Cm ^Three Then, boron of 1.5 to 3 times the concentration of phosphorus contained is added to make the conductivity type p-type.
[0082]
Through the above steps, impurity regions are formed in the respective semiconductor films. The second shape electrode 621 and the third shape electrodes 630 to 632 function as gate electrodes. The third shape wiring 633 forms a data line. The gate electrode 632 serves as one electrode forming an additional capacitor, and forms a capacitor in a portion overlapping with the semiconductor film 606.
[0083]
After that, as shown in FIG. 12A, a protective insulating film 638 made of a silicon oxynitride film is formed to a thickness of 50 nm by plasma CVD. Then, heat treatment for activating the added impurities is performed. This heat treatment is performed by irradiating pulsed radiation a plurality of times using the heat treatment apparatus described in Example 1 or Example 2. Since radiation is emitted from the substrate side, even if the first n-type semiconductor region overlapping with the gate electrode is formed, the p-type and n-type impurity elements can be reliably activated including the region.
[0084]
The hydrogenation treatment is a treatment necessary for improving the characteristics of the TFT, and can be performed by a heat treatment method or a plasma treatment method in a hydrogen atmosphere. In addition, as shown in FIG. 12B, a silicon nitride film 640 is formed to a thickness of 50 to 100 nm, and heat treatment at 350 to 500 ° C. is performed, whereby hydrogen in the silicon nitride film 640 is released. By diffusing into the semiconductor film, it can be hydrogenated to compensate for defects.
[0085]
The interlayer insulating film 641 is formed of an organic insulating material such as polyimide or acrylic to flatten the surface. Needless to say, silicon oxide formed using TEOS by a plasma CVD method may be applied, but it is preferable to use the organic material from the viewpoint of improving flatness.
[0086]
Next, a contact hole reaching the second n-type semiconductor region or the first p-type semiconductor region of each semiconductor film from the surface of the interlayer insulating film 641 is formed, and wiring is formed using Al, Ti, Ta, or the like. In FIG. 12B, 642 and 645 are source lines, and 643 and 644 are drain lines. Reference numeral 647 denotes a pixel electrode, and reference numeral 646 denotes a connection electrode that connects the data line 633 and the second n-type semiconductor region 667 of the semiconductor film 605. Reference numeral 648 denotes a gate line, which is not shown in the drawing, but is connected to a third shape electrode 631 that functions as a gate electrode.
[0087]
Thus, a TFT for forming the driver circuit 650 and the pixel portion 651 is formed over the same substrate. Although two p-channel TFTs 652 and n-channel TFTs 653 are shown in the driver circuit 650, various functional circuits such as a shift register, a level shifter, a latch, and a buffer circuit can be formed using these TFTs. A cross-sectional structure taken along line BB ′ shown in FIG. 12B corresponds to a line BB ′ shown in the pixel structure shown in FIG.
[0088]
The p-channel TFT 652 of the driver circuit 650 includes a channel formation region 660 and a first p-type semiconductor region 661 that functions as a source region or a drain region. The n-channel TFT 653 includes a channel formation region 662, a first n-type semiconductor region 663 overlapping with the gate electrode 621, and a second n-type semiconductor region 664 functioning as a source region or a drain region.
[0089]
In the n-channel TFT 654 of the pixel portion 651, a channel formation region 665, a first n-type semiconductor region 666 outside the gate electrode 640, and second n-type semiconductor regions 667 to 669 functioning as a source or drain region are formed. ing. The auxiliary capacitor 655 is formed by the semiconductor film 606, the second insulating film 607, and the gate electrode 632. A first p-type semiconductor region 671 is formed in the semiconductor film 606 by the above process.
[0090]
The first n-type semiconductor region formed in the n-channel TFT is an LDD (Lightly Doped Drain) region. By forming the gate electrode so as to overlap with the n-channel TFT 653, the high electric field region formed at the drain end is relaxed, and deterioration due to the hot carrier effect can be suppressed. On the other hand, the off-state current can be reduced by providing an LDD region outside the gate electrode as in the n-channel TFT 654.
[0091]
The p-channel TFT 652 is formed with a single drain structure, but by adjusting the time of the third etching process, the end of the gate electrode is retracted to form an offset region between the channel formation region and the impurity region. You can also Such a configuration is also possible for the n-channel TFT 654, which is very effective for the purpose of reducing off-state current.
[0092]
As described above, an element substrate in which a pixel portion and a driver circuit are formed using TFTs can be formed over the same substrate. The manufacturing process of the element substrate shown in this embodiment makes it possible to form TFTs having different LDD region configurations on the same substrate using five photomasks.
[0093]
Similar to the third embodiment, the heat treatment apparatus of the present invention can be used for activation in such a TFT manufacturing process. The heat treatment method of the present invention can be activated in a short time without damaging the substrate.
[0094]
[Example 5]
In this embodiment, another example of a method for manufacturing a semiconductor film which can be applied to Embodiment 3 or Embodiment 4 will be described with reference to FIGS. The method for manufacturing a semiconductor film described with reference to FIG. 8 is a method in which a metal element is added to the entire surface of an amorphous silicon film to be crystallized. The metal element to be applied is one or a plurality selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au, and Ni is typically applied. These elements have been found to be capable of lowering the heat treatment temperature for crystallization and shortening the heat treatment time.
[0095]
First, in FIG. 8A, a substrate 551 is a glass substrate typified by Corning # 1773 glass substrate. On the surface of the substrate 551, a SiH film is formed as a first insulating film 552 by plasma CVD. _Four And N ₂ A silicon oxynitride film is formed to a thickness of 100 nm using O. The first insulating film 552 is provided so that alkali metal contained in the glass substrate does not diffuse into the semiconductor film formed in the upper layer.
[0096]
The amorphous silicon film 553 is formed by a plasma CVD method. SiH _Four Is introduced into the reaction chamber, decomposed by intermittent discharge or pulse discharge, and deposited on the substrate 551. As an example of the film forming conditions, high frequency power of 27 MHz is modulated and deposited to a thickness of 54 nm by intermittent discharge with a repetition frequency of 5 kHz and a duty ratio of 20%. Of course, a continuous discharge of 13.56 MHz may be used. In order to reduce impurities such as oxygen, nitrogen, and carbon in the amorphous silicon film 553 as much as possible, SiH _Four Is used with a purity of 99.9999% or more. The specifications of the plasma CVD apparatus are as follows: a reaction chamber having a reaction chamber volume of 13 liters, a complex molecular pump having a pumping speed of 300 liters / second in the first stage, and a pumping speed of 40 m in the second stage. ^Three / Hr dry pump is provided to prevent back diffusion of organic vapor from the exhaust system side, increase the ultimate vacuum in the reaction chamber, and incorporate the impurity element into the film during the formation of the amorphous semiconductor film As much as possible.
[0097]
Then, a nickel acetate layer solution containing 10 ppm of nickel in terms of weight is applied by a spinner to form a nickel-containing layer 554. In this case, in order to improve the familiarity of the solution, as the surface treatment of the amorphous semi-silicon film 553, an extremely thin oxide film is formed with an ozone-containing aqueous solution, and the oxide film is mixed with hydrofluoric acid and hydrogen peroxide water. After etching with a liquid to form a clean surface, it is treated again with an aqueous solution containing ozone to form an extremely thin oxide film. Since the surface of silicon is inherently hydrophobic, the nickel acetate salt solution can be uniformly applied by forming an oxide film in this way.
[0098]
Next, heat treatment is performed at 500 ° C. for 1 hour to release hydrogen in the amorphous silicon film. Then, crystallization is performed by heat treatment at 580 ° C. for 4 hours. Thus, a crystalline silicon film 555 shown in FIG. 8B is formed.
[0099]
Further, in order to increase the crystallization rate (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains, laser annealing is performed on the crystalline silicon film 555 with the laser light 556. The laser uses excimer laser light that oscillates at 30 Hz with a wavelength of 308 nm. The laser beam is 100 to 300 mJ / cm in the optical system. ² The laser processing is performed without melting the semiconductor film with an overlap ratio of 90 to 95%. A crystalline silicon film 557 can be obtained.
[0100]
A semiconductor film 558 is formed by dividing the crystalline silicon film 557 into island shapes. Such a semiconductor film can be applied to Embodiments 3 and 4 as they are.
[0101]
[Example 6]
In this embodiment, an example of a method for gettering the metal element remaining in the semiconductor film obtained in Embodiment 5 will be described with reference to FIG. The gettering described here is based on the method of gettering the metal element from the channel formation region of the TFT. FIG. 9 illustrates a state where a first insulating film 562, a semiconductor film 563, a second insulating film 567, a first conductive film 568, and a second conductive film 569 are formed over a substrate 561. As the semiconductor film 563, a semiconductor film manufactured by the method of Example 5 is applied, and the n-type semiconductor region 565 has 1 × 10 6. ²⁰ ~ 1x10 ^{twenty one} / Cm ^Three Of phosphorus has been added.
[0102]
In the semiconductor film 563, the n-type semiconductor region 565 can be regarded as a source or drain region in the TFT, and the channel 564 can be regarded as a channel formation region. Here, the metal element added for crystallization is 1 × 10 6 in the channel formation region. ¹⁷ ~ 1x10 ¹⁹ / Cm ^Three Remains at a moderate concentration. The heat treatment method of the present invention enables so-called gettering in which the metal element is segregated in the n-type semiconductor region 565.
[0103]
In this heat treatment method, pulsed radiation 570 is irradiated from the substrate side in accordance with the first embodiment. The pulsed radiation of the curve A shown in the graph of FIG. 3 is suitable for the pulsed radiation. That is, it is heated to 1100 ° C. at a rate of 100 to 200 ° C./second and maintained at that temperature for 4 seconds. The cooling rate is 50 to 150 ° C./second and the cooling is performed to 300 to 400 ° C. The effect of gettering can be confirmed by only irradiating such radiation once. More preferably, it is good to irradiate 2-10 times of pulsed radiation. Thus, the concentration of the metal element used in the crystallization step is 1 × 10. ¹⁷ / Cm ^Three It can be reduced to less than.
[0104]
Such a gettering method can be freely combined with the third to fourth embodiments. For example, in Example 4, gettering described in this example can be combined with heat treatment for activation.
[0105]
[Example 7]
In this embodiment, a process for manufacturing an active matrix liquid crystal display device from a substrate (referred to as an element substrate) on which a driving circuit and a pixel portion obtained in Embodiment 4 are formed will be described. FIG. 14 shows a state in which the element substrate 700 and the counter substrate 701 are bonded together with a sealing material. A columnar spacer 704 is formed on the element substrate 700. The columnar spacers 704 and 705 are preferably formed in accordance with the depression of the contact portion formed on the pixel electrode. The columnar spacer 704 is formed with a height of 3 to 10 μm although it depends on the liquid crystal material to be used. Since the concave portion corresponding to the contact hole is formed in the contact portion, disorder of the alignment of the liquid crystal can be prevented by forming a spacer in accordance with this portion. Thereafter, an alignment film 706 is formed and a rubbing process is performed. A transparent conductive film 702 and an alignment film 703 are formed on the counter substrate 701. After that, the element substrate 700 and the counter substrate 701 are bonded to each other with a sealant 707 and liquid crystal is injected to form a liquid crystal layer 708. An active matrix liquid crystal display device manufactured as described above can be completed.
[0106]
[Example 8]
In this embodiment, a process for manufacturing a light-emitting device driven by an active matrix from the TFT obtained in Embodiment 4 will be described with reference to FIGS.
[0107]
A glass substrate is used as the substrate 1601. On the glass substrate 1601, an n-channel TFT 1652 and a p-channel TFT 1653 are formed in the driver circuit portion 1650, and a switching TFT 1654 and a current control TFT 1655 are formed in the pixel portion 1651. These TFTs are formed using semiconductor layers 1603 to 1606, a second insulating film 1607 as a gate insulating film, gate electrodes 1608 to 1611, and the like.
[0108]
A first insulating film 1602 formed over the substrate 1601 is made of silicon oxynitride (SiO _x N _y A silicon nitride film or the like is formed to a thickness of 50 to 200 nm. The interlayer insulating film includes an inorganic insulating film 1618 formed of silicon nitride, silicon oxynitride, or the like, and an organic insulating film 1619 formed of acrylic or polyimide.
[0109]
The circuit configuration of the drive circuit unit 1650 differs between the gate signal side drive circuit and the data signal side drive circuit, but is omitted here. Wirings 1612 and 1613 are connected to the n-channel TFT 1652 and the p-channel TFT 1653, and a shift register, a latch circuit, a buffer circuit, or the like is formed using these TFTs.
[0110]
In the pixel portion 1651, the data wiring 1614 is connected to the source side of the switching TFT 1654, and the drain side wiring 1615 is connected to the gate electrode 1611 of the current control TFT 1655. The source side of the current control TFT 1655 is connected to the power supply wiring 1617, and the drain side electrode 1616 is connected to the anode of the EL element.
[0111]
An EL element having an anode, a cathode, and a layer containing an organic compound (hereinafter collectively referred to as an EL layer) from which electroluminescence is obtained is formed on the TFT of the pixel portion. Minescence in an organic compound includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state, and includes both.
[0112]
The EL element is provided after the banks 1620 and 1621 are formed using an organic resin such as acrylic or polyimide, preferably a photosensitive organic resin so as to cover the wiring. In this embodiment, the EL element 1656 includes an anode 1622 formed of ITO (indium tin oxide), an EL layer 1623, and a cathode formed using a material such as an alkali metal or alkaline earth metal such as MgAg or LiF. It consists of 1624. The banks 1620 and 1621 are formed so as to cover the end portion of the anode 1622 and are provided to prevent the cathode and the anode from being short-circuited at this portion.
[0113]
On the EL layer 1623, a cathode 1624 of an EL element is provided. As the cathode 1624, a material containing magnesium (Mg), lithium (Li), or calcium (Ca) having a low work function is used. An electrode made of MgAg (a material in which Mg and Ag are mixed at Mg: Ag = 10: 1) is preferably used. Other examples include MgAgAl electrodes, LiAl electrodes, and LiFAl electrodes.
[0114]
A stacked body including the EL layer 1623 and the cathode 1624 needs to be formed individually for each pixel. However, since the EL layer 1623 is extremely weak against moisture, a normal photolithography technique cannot be used. Further, the cathode 1624 manufactured using an alkali metal is easily oxidized. Accordingly, it is preferable to use a physical mask material such as a metal mask and selectively form the film by a vapor phase method such as a vacuum deposition method, a sputtering method, or a plasma CVD method. Further, a protective electrode for protecting from external moisture or the like may be stacked over the cathode 1624. As the protective electrode, it is preferable to use a low-resistance material containing aluminum (Al), copper (Cu), or silver (Ag).
[0115]
In order to obtain high luminance with low power consumption, an organic compound that emits light by triplet excitons (triplet compound) is used as a material for forming the EL layer. The singlet compound refers to a compound that emits light only through singlet excitation, and the triplet compound refers to a compound that emits light via triplet excitation.
[0116]
Examples of the triplet compound include organic compounds described in the following papers as typical materials. (1) T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p.437. (2) MABaldo, DFO ' Brien, Y.You, A.Shoustikov, S.Sibley, METhompson, SRForrest, Nature 395 (1998) p.151. This paper discloses an organic compound represented by the following formula. (3) MABaldo, S. Lamansky, PEBurrrows, METhompson, SRForrest, Appl. Phys. Lett., 75 (1999) p. 4. (4) T. Tsutsui, M.-J. Yang, M. Yahiro, K. Nakamura, T. Watanabe, T. tsuji, Y. Fukuda, T. Wakimoto, S. Mayaguchi, Jpn. Appl. Phys., 38 (12B) (1999) L1502.
[0117]
The triplet compound has higher luminous efficiency than the singlet compound, and the operating voltage (voltage required for causing the EL element to emit light) can be lowered to obtain the same light emission luminance.
[0118]
In FIG. 15, the switching TFT 1654 has a multi-gate structure, and the current control TFT 1655 is provided with an LDD that overlaps the gate electrode. Since TFTs using polycrystalline silicon exhibit a high operating speed, deterioration such as hot carrier injection is likely to occur. Therefore, as shown in FIG. 15, it is highly reliable to form TFTs having different structures (a switching TFT with sufficiently low off-current and a current control TFT resistant to hot carrier injection) having different structures depending on functions in the pixel. And is very effective in manufacturing a display device capable of good image display (high operation performance). An active matrix light-emitting device manufactured as described above can be completed.
[0119]
[Example 9]
17A to 17C show micrographs of a sample in which phosphorus is added to the crystalline semiconductor film by an ion doping method and the subsequent activation is performed using the heat treatment method of the present invention. The sample has a structure similar to that shown in FIG. 4, and a 100 nm silicon nitride oxide film, a 50 nm semiconductor film, and an 80 nm silicon nitride oxide film are stacked on a glass substrate, and a patterned 30 nm tantalum nitride film is formed thereon. A film and a 300 nm tungsten film are formed.
[0120]
As is well known, a region into which an impurity element has been implanted by ion doping is made amorphous by ion bombardment. The necessary heat treatment thereafter aims to recrystallize the amorphous region and activates the impurity element at the same time.
[0121]
The pulsed radiation to be irradiated was irradiated with radiation equivalent to the curve A (holding time 4 seconds) and the curve B (holding time 0.75 seconds) in FIG. FIG. 17A shows a sample irradiated with pulsed radiation of curve B once. A mottled pattern is observed in the region where the semiconductor film is exposed, and it is confirmed that crystallization has not progressed sufficiently. In this case, it is determined from the empirical rule that the dark portion is amorphous and the thin region is crystalline. FIG. 17B is a photograph of a sample irradiated with the same pulsed radiation four times, and it can be confirmed that the number of mottled patterns is similarly reduced. FIG. 17C shows a sample irradiated with pulsed radiation of curve A once, and it can be judged that most of the sample is crystallized.
[0122]
The above results show that the phosphorus added by the ion doping method can be activated without damaging the substrate by the heat treatment method of the present invention. Depending on the irradiation conditions, more preferable results can be obtained by irradiating a plurality of times than once.
[0123]
[Example 10]
Various kinds of semiconductor devices can be completed by using the present invention. Examples of semiconductor devices to which the present invention is applied include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers, television receivers, projectors, and the like. Examples of these are shown in FIGS.
[0124]
FIG. 18A illustrates a mobile phone which includes a display panel 2701, an operation panel 2702, and a connection portion 2703. The display panel 2701 includes a display device 2704 typified by a liquid crystal display device or an EL display device, and an audio output. A portion 2705, an antenna 2709, and the like are provided. The operation panel 2702 is provided with operation keys 2706, a power switch 2707, a voice input unit 2708, and the like. The present invention can be applied to the display device 2904 and a mobile phone can be completed.
[0125]
FIG. 18B illustrates a video camera which includes a main body 9101, a display device 9102 typified by a liquid crystal display device or an EL display device, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be applied to the display device 9102 and a video camera can be completed.
[0126]
FIG. 18C illustrates a mobile computer or a portable information terminal, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205 typified by a liquid crystal display device or an EL display device. . The present invention can be applied to the display device 9205 and a portable information terminal can be completed.
[0127]
FIG. 18D illustrates a television receiver which includes a main body 9401, a speaker 9402, a display device 9403 typified by a liquid crystal display device or an EL display device, a receiving device 9404, an amplifying device 9405, and the like. The present invention can be applied to the display device 9403 and a television receiver can be completed.
[0128]
FIG. 18E illustrates a portable book which includes a main body 9501, a display device 9503 typified by a liquid crystal display device or an EL display device, a storage medium 9504, operation switches 9505, and an antenna 9506, and is a minidisc (MD). Or data stored on a DVD or data received by an antenna. The present invention can be applied to the display device 9503 and a portable book can be completed.
[0129]
FIG. 19A illustrates a personal computer which includes a main body 9601, an image input portion 9602, a display device 9603 typified by a liquid crystal display device or an EL display device, and a keyboard 9604. The present invention can be applied to the display device 9601 and a personal computer can be completed.
[0130]
FIG. 19B shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The main body 9701, a display device 9702 typified by a liquid crystal display device or an EL display device, a speaker portion 9703, and a recording medium 9704 and an operation switch 9705. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 9702 and a player can be completed.
[0131]
FIG. 19C illustrates a digital camera which includes a main body 9801, a display device 9802 typified by a liquid crystal display device or an EL display device, an eyepiece portion 9803, operation switches 9804, and an image receiving portion (not shown). The present invention can be applied to the display device 9802 and a digital camera can be completed.
[0132]
FIG. 20A illustrates a front type projector that includes a projection device 3601 and a screen 3602. The present invention can be applied to the projection device 3601, and a front type projector can be completed.
[0133]
FIG. 20B illustrates a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, and a screen 3704. The present invention can be applied to a liquid crystal display device incorporated in the projection device 3702, and a rear projector can be completed.
[0134]
Note that FIG. 20C is a diagram illustrating an example of the structure of the projection devices 3601 and 3702 in FIGS. 20A and 20B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0135]
FIG. 20D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 20D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0136]
Although not shown here, the present invention can also be applied to display devices incorporated in navigation systems, refrigerators, washing machines, microwave ovens, fixed telephones, facsimiles, and the like. Thus, the application range of the present invention is very wide and can be applied to various products.
[0137]
[Example 11]
In this embodiment, an example in which the TFT used in the pixel portion of the liquid crystal display device is formed of an inverted stagger type TFT is shown in FIG. FIG. 21A is an enlarged top view of one of the pixels of the pixel portion provided on the element substrate. In FIG. 21A, a portion cut along a dotted line AA ′ is shown in FIG. ) Corresponding to the cross-sectional structure of the pixel portion.
[0138]
In FIG. 21B, reference numeral 851 denotes a substrate. First, a base insulating film (not shown) is formed over the substrate.
[0139]
In the pixel portion, the pixel TFT is an n-channel TFT. A gate electrode 852 is formed over a base insulating film provided over the substrate 851, and a first insulating film 853a made of silicon nitride and a second insulating film 853b made of silicon oxide are formed thereon. Further, on the second insulating film, second n-type impurity regions 854 to 856 serving as a source region or a drain region as an active layer, channel forming regions 857 and 858, the second n-type impurity region and the channel are formed. First n-type impurity regions 859 and 860 are formed between the formation regions. Further, the channel formation regions 857 and 858 are protected by insulating layers 861 and 862. After a contact hole is formed in the first interlayer insulating film 863 that covers the insulating layers 861 and 862 and the active layer, a wiring 864 connected to the second n-type impurity region 854 is formed, and the second n-type impurity region 856 is formed. A pixel electrode 865 made of Al, Ag, or the like is connected to the substrate, and a passivation film 866 is formed thereon. Reference numeral 870 denotes a pixel electrode adjacent to the pixel electrode 865.
[0140]
In this embodiment, the gate wiring of the pixel TFT in the pixel portion has a double gate structure. However, a multi-gate structure such as a triple gate structure may be used in order to reduce variation in off current. Further, a single gate structure may be used in order to improve the aperture ratio.
[0141]
Further, the capacitor portion of the pixel portion is formed of a capacitor wiring 871 and a second n-type impurity region 856 using the first insulating film and the second insulating film as a dielectric.
[0142]
Note that the pixel portion illustrated in FIG. 21 is merely an example, and it is needless to say that the pixel portion is not particularly limited to the above configuration.
[0143]
The heat treatment apparatus of the present invention can be applied to heat treatment when manufacturing the TFT of the pixel portion shown in FIG. 21, for example, activation of an impurity element contained in the second n-type impurity region and gettering. This heat treatment is performed by irradiating pulsed radiation a plurality of times using the heat treatment apparatus described in Example 1 or Example 2. Pulsed radiation may be emitted from the substrate side or from the opposite side.
[0144]
Further, according to Embodiment 7, a liquid crystal display device can be completed from the element substrate of this embodiment. In addition, the liquid crystal display device thus manufactured can be used as a display portion of various electronic devices shown in Embodiment 10.
[0145]
[Example 12]
This example shows the characteristics of an n-channel TFT manufactured using the semiconductor film subjected to the gettering process shown in Example 6. The TFT has a single drain structure, and has a channel length of 10 μm and a channel width of 8 μm. The reduction effect of the catalytic element by the gettering can be seen as the substitute characteristic when the off-current value can be seen as a substitute characteristic, and the value is 1 pA or less.
[0146]
As for the gettering conditions, the maximum heating temperature is 690 to 730 ° C., and the holding time is 300 seconds, and this is repeated three times.
[0147]
FIG. 22 shows the distribution (variation) of the off-current values of 94 samples as a cumulative frequency graph. In the graph, for comparison, data of a sample subjected to a gettering treatment at 550 ° C. for 4 hours using a furnace annealing furnace is also shown, but it is shown that there is no significant difference between the two. . Good gettering is also possible by the heat treatment method of the present invention, and it takes less time than gettering using a conventional furnace annealing furnace.
[0148]
【The invention's effect】
By using the heat treatment method of the present invention, the impurity element added to the semiconductor film can be activated and gettering can be performed in a short time without causing damage to the substrate and without causing deformation. The heat treatment apparatus of the present invention enables such heat treatment. Furthermore, by using such a heat treatment method, the productivity of the semiconductor device can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a heat treatment method according to the present invention.
FIG. 2 is a diagram for explaining timing of blinking of a lamp light source and supply amount of refrigerant.
FIG. 3 is a graph showing a temperature change in an irradiated region due to pulsed radiation from a lamp light source.
FIG. 4 is a view for explaining the heat treatment mechanism of the present invention.
FIG. 5 is a diagram illustrating a configuration of a heat treatment apparatus according to the present invention.
6A and 6B illustrate a heat treatment method of the present invention.
FIG. 7 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor film.
FIG. 9 is a cross-sectional view illustrating a gettering method.
10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device including a driver circuit portion and a pixel portion.
11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device including a driver circuit portion and a pixel portion.
12 is a cross-sectional view illustrating a manufacturing process of a semiconductor device including a driver circuit portion and a pixel portion. FIG.
FIG. 13 is a top view illustrating a structure of a pixel portion.
FIG. 14 illustrates a structure of a liquid crystal display device obtained by the present invention.
FIG. 15 illustrates a structure of a light-emitting device obtained by the present invention.
FIG. 16 illustrates a structure of a heat treatment apparatus according to the present invention.
FIG. 17 is a micrograph of a semiconductor film that has been activated by the heat treatment method of the present invention.
FIG 18 illustrates an example of a semiconductor device.
FIG 19 illustrates an example of a semiconductor device.
FIG. 20 is a diagram illustrating a configuration of a projector.
FIGS. 21A and 21B are a top view and a cross-sectional view of a pixel portion. FIGS.
FIG. 22 is a cumulative frequency graph showing the distribution of TFT off-current in a plurality of samples.

Claims (9)

Forming an amorphous semiconductor film on a light-transmitting substrate ;
Adding a metal element to the amorphous semiconductor film;
By performing heat treatment, the amorphous semiconductor film is crystallized to form a crystalline semiconductor film,
A light-absorbing gate electrode is formed on the crystalline semiconductor film via an insulating film ;
Add phosphorus to a part of the crystalline semiconductor film using the gate electrode as a mask,
By heating the semiconductor film using a radiation lamp light source from the light transmitting substrate side, characterized by gettering the metal element to said portion of said crystalline semiconductor film doped with phosphorus A method for manufacturing a semiconductor device. Forming an amorphous semiconductor film on a light-transmitting substrate;
Adding a metal element to the amorphous semiconductor film;
By performing heat treatment, the amorphous semiconductor film is crystallized to form a crystalline semiconductor film,
A light-absorbing gate electrode is formed on the crystalline semiconductor film through an insulating film;
Add phosphorus to a part of the crystalline semiconductor film using the gate electrode as a mask,
The metal element is gettered to the part of the crystalline semiconductor film to which phosphorus is added by performing radiation of the lamp light source a plurality of times from the translucent substrate side and heating the crystalline semiconductor film. A method for manufacturing a semiconductor device. Forming an amorphous semiconductor film on a light-transmitting substrate ;
Adding a metal element to the amorphous semiconductor film ;
By performing heat treatment, the amorphous semiconductor film is crystallized to form a crystalline semiconductor film,
A light-absorbing gate electrode is formed on the crystalline semiconductor film via an insulating film;
Add phosphorus to a part of the crystalline semiconductor film using the gate electrode as a mask,
Wherein a light-transmitting substrate side radiation lamp light source performs intermittent several times, by heating the crystalline semiconductor film, and gettering the metal element to said portion of said crystalline semiconductor film added with phosphorus,
A method for manufacturing a semiconductor device, characterized in that intermittent multiple times of radiation from the lamp light source is 0.1 to 20 seconds per time . Forming an amorphous semiconductor film on a light-transmitting substrate ;
Adding a metal element to the amorphous semiconductor film;
By performing heat treatment, the amorphous semiconductor film is crystallized to form a crystalline semiconductor film,
A light-absorbing gate electrode is formed on the crystalline semiconductor film via an insulating film ;
Add phosphorus to a part of the crystalline semiconductor film using the gate electrode as a mask,
Holding the translucent substrate in a coolant;
Wherein a light-transmitting substrate side radiation lamp light source performs intermittent several times, by heating the crystalline semiconductor film, and gettering the metal element to said portion of said crystalline semiconductor film added with phosphorus,
The intermittent multiple radiation from the lamp source Ri 0.1-20 Byodea per,
A method for manufacturing a semiconductor device, wherein radiation of the lamp light source is cut off and a supply amount of the refrigerant is increased . Forming an amorphous semiconductor film on a light-transmitting substrate ;
Adding a metal element to the amorphous semiconductor film;
By performing heat treatment, the amorphous semiconductor film is crystallized to form a crystalline semiconductor film,
A light-absorbing gate electrode is formed on the crystalline semiconductor film via an insulating film ;
Add phosphorus to a part of the crystalline semiconductor film using the gate electrode as a mask,
Holding the translucent substrate in a coolant;
Wherein a light-transmitting substrate side radiation lamp light source performs intermittent several times, by heating the crystalline semiconductor film, and gettering the metal element to said portion of said crystalline semiconductor film added with phosphorus,
Intermittent radiation from the lamp light source turns on the lamp light source and decreases the supply amount of the refrigerant. The lamp light source is turned on for 0.1 to 20 seconds per time, and the lamp light source is turned off. And a process for increasing the supply amount of the refrigerant is one cycle. 6. The method for manufacturing a semiconductor device according to claim 1, wherein activation is performed simultaneously with the gettering by radiation of the lamp light source. 7. The method for manufacturing a semiconductor device according to claim 1, wherein a light-reflective gate electrode is formed in contact with the light-absorbing gate electrode. According to claim 1 or claim 7, wherein the metal element semiconductor, wherein Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, that is one or more kinds selected from Au Device fabrication method. In any one of claims 1 to 8, wherein the lamp light source, a halogen lamp, a metal halide lamp, a xenon lamp, a high pressure mercury lamp, a semiconductor device which is characterized in that one either high-pressure sodium lamp or excimer lamp Manufacturing method.

Images