JP2003332342A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology wherein a semiconductor film having a crystalline structure is obtained by using a metal element for promoting crystallization of the semiconductor film, and then fluctuation among devices can be reduced by effectively eliminating the metal element remaining in the film. <P>SOLUTION: A process for forming a gettering site comprises the steps of: forming a semiconductor film containing a rare gas element; forming a semiconductor film having an amorphous structure containing a high-concentration rare gas element, amorphous silicon film as a major example, on the surface of a second semiconductor film by treating the film for generating plasma of a rare gas element, carbon, or oxygen; and gettering the semiconductor film. Or it is also possible to form the gettering site composed of an amorphous silicon film laminated by repeating film formation and plasma treatment. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device using a gettering technique. In particular, the present invention is
The present invention relates to a method for manufacturing a semiconductor device using a semiconductor film having a crystal structure which is manufactured by adding a metal element which promotes crystallization of a semiconductor film.

[0002] In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, light-emitting devices, semiconductor circuits, and electronic devices are all semiconductor devices.

[0003]

2. Description of the Related Art A thin film transistor (hereinafter referred to as a TFT) is used as a typical semiconductor device using a semiconductor film having a crystal structure.
Is known). The TFT is drawing attention as a technique for forming an integrated circuit on an insulating substrate such as glass, and a drive circuit integrated liquid crystal display device and the like are being put to practical use. In the conventional technique, a semiconductor film having a crystalline structure is obtained by subjecting an amorphous semiconductor film deposited by a plasma CVD method or a low pressure CVD method to a heat treatment or a laser annealing method (a technique of crystallizing a semiconductor film by laser light irradiation). It is made by.

The semiconductor film having a crystal structure produced in this manner is an aggregate of a large number of crystal grains, and its crystal orientation is oriented in an arbitrary direction and cannot be controlled, which is a factor limiting the characteristics of the TFT. ing. In order to solve such a problem, the technique disclosed in JP-A-7-183540 is to add a metal element such as nickel that promotes crystallization of a semiconductor film to produce a semiconductor film having a crystal structure. In addition to the effect of lowering the heating temperature required for crystallization, it is possible to enhance the orientation of crystal orientation in a single direction. When a TFT is formed of a semiconductor film having such a crystal structure, not only the field effect mobility is improved, but also the subthreshold coefficient (S value) is reduced, and the electrical characteristics can be dramatically improved. ing.

The use of a metal element that promotes crystallization makes it possible to control the nucleation during crystallization.
The film quality obtained is uniform compared to other crystallization methods in which nucleation is random, and ideally, it is desirable to completely remove the metal element or reduce it to an allowable range. However, since the metal element that promotes crystallization is added, there is a problem that the metal element remains in the film or the film surface of the semiconductor film having a crystal structure, and the characteristics of the obtained device are varied. . One example thereof is a problem that the off-current increases in the TFT and the TFTs vary among the individual elements. That is, the metal element that promotes crystallization becomes an unnecessary existence once the semiconductor film having the crystal structure is formed.

Gettering using phosphorus is effectively used as a method for removing a metal element that promotes crystallization from a specific region of a semiconductor film having a crystal structure. For example, by adding phosphorus to the source / drain region of the TFT and performing heat treatment at 450 to 700 ° C., the metal element can be easily removed from the channel formation region.

[0007]

Phosphorus is an ion doping method (a method of dissociating PH ₃ or the like with plasma and accelerating the ions with an electric field to implant them into a semiconductor. Basically, mass separation of ions is performed. However, the phosphorus concentration required for gettering is 1 × 10 ²⁰ / cm ³ or more. The addition of phosphorus by the ion doping method brings about amorphization of the semiconductor film having a crystal structure, but an increase in the phosphorus concentration is a problem because it hinders recrystallization by subsequent annealing. Further, the addition of a high concentration of phosphorus causes an increase in the processing time required for doping, which lowers the throughput in the doping process, which is a problem.

Further, the concentration of boron required to invert the conductivity type is 1.5 to 3 times that of phosphorus added to the source / drain regions of the p-channel TFT, which causes recrystallization. Along with the difficulty, the resistance of the source / drain region is increased, which is a problem.

Further, if the gettering is not sufficient in the substrate and the gettering varies, each TFT is
There was a slight difference in characteristics, that is, variation. In the case of a transmissive liquid crystal display device, if the TFTs arranged in the pixel portion have variations in electrical characteristics, variations in the voltage applied to each pixel electrode occur, which causes variations in the amount of transmitted light.
This causes display unevenness and appears in the eyes of the observer.

Further, in the light emitting device using the OLED, the TFT is an essential element for realizing the active matrix driving system. Therefore, in a light emitting device using an OLED, at least a TFT that functions as a switching element and a TFT that supplies a current to the OLED are provided in each pixel. Pixel circuit configuration,
And electrically connected to the OLED regardless of the driving method,
In addition, the on-current (I
_Since the brightness of the pixel is determined by ( _on ), there is a problem that, for example, when the white display is performed on the entire surface, the brightness varies unless the on-current is constant.

The present invention is a means for solving such a problem, which is obtained by obtaining a semiconductor film having a crystal structure using a metal element that promotes crystallization of the semiconductor film, and then remaining in the film. It is an object of the present invention to provide a technique for effectively removing a metal element.

[0012]

The gettering technique is positioned as a main technique in the technique of manufacturing an integrated circuit using a single crystal silicon wafer. Gettering is known as a technique in which metal impurities taken into a semiconductor are segregated at gettering sites by some energy to reduce the impurity concentration in the active region of the device.
It is the extrinsic gettering (Extrinsic G
ettering and Intrinsic gettering
There are two main categories: Gettering). The extrinsic gettering is one in which a gettering effect is brought about by externally applying a strain field or a chemical action. This is a ring getter that diffuses a high concentration of phosphorus from the back surface of a single crystal silicon wafer, and the gettering using phosphorus described above can be regarded as a type of extrinsic gettering.

On the other hand, intrinsic gettering is known to utilize the strain field of lattice defects involving oxygen generated inside a single crystal silicon wafer.
The present invention uses the gettering mechanism different from the above-mentioned extrinsic gettering or intrinsic gettering, and adopts the following means for applying to a semiconductor film having a crystal structure with a thickness of about 10 to 200 nm. To do.

According to the present invention, a step of forming a first semiconductor film having a crystal structure by using a metal element on an insulating surface, a step of forming a film (barrier layer) which serves as an etching stopper, and a rare gas element are used. A step of forming a second semiconductor film (gettering site) containing the same, a step of gettering the gettering site with a metal element by heat treatment, a step of removing the second semiconductor film, and a step of removing the barrier layer. And the process.

As a method of forming the second semiconductor film,
Although there are sputtering method and plasma CVD method, plasma C
Since the VD method can clean the inside of the film forming chamber (also referred to as a chamber) with a gas, it requires less maintenance than the sputtering method and can be said to be suitable for mass production.
However, when the second semiconductor film containing the rare gas element is formed by the plasma CVD method, film peeling (also called peeling) is likely to occur due to the heat treatment performed later. Further, in the plasma CVD method, it was difficult to include a large amount of rare gas element in the second semiconductor film.

Therefore, according to the present invention, after the second semiconductor film is formed, a high concentration rare gas element is added to the surface of the second semiconductor film by performing a process of generating plasma of the rare gas element. Is characterized by. By doing this, plasma
A second semiconductor film containing a rare gas element in a high concentration can be obtained regardless of the conditions for forming the second semiconductor film by a CVD method. Therefore, the second semiconductor film can be formed with high throughput without causing peeling, and the rare gas element can be contained at a high concentration on the surface thereof.

Specifically, plasma CVD is used, and monosilane, monosilane and hydrogen are used as source gases in the film forming chamber.
Monosilane and argon, monosilane and argon and nitrogen,
Alternatively, monosilane, argon, and hydrogen are introduced to obtain a film thickness of 1n.
After forming an amorphous silicon film of m to 10 nm,
The plasma treatment of argon may be repeated once or twice or more to form a second semiconductor film (gettering site) including a stack.

Structure 1 of the invention relating to the manufacturing method disclosed in this specification includes a first step of forming a first semiconductor film having an amorphous structure on an insulating surface and a first step of having the amorphous structure. A second step of adding a metal element to the semiconductor film, a third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a first step having the crystal structure. A fourth step of forming a barrier layer on the surface of the semiconductor film, and forming a semiconductor film containing a rare gas element on the barrier layer by introducing a gas containing a rare gas and silane into a deposition chamber by a plasma CVD method. The treatment for forming a film and the treatment for removing a gas containing silane from the film forming chamber on the surface of the semiconductor film to generate plasma only as a rare gas to add a rare gas element once or twice or more. Rare gas elements on the surface by alternating A fifth step of concentration to form a high second semiconductor film than the lower, heat treatment is performed, the second
A sixth step of removing or reducing the metal element in the first semiconductor film having a crystalline structure by gettering the metal element to the semiconductor film of, and a seventh step of removing the second semiconductor film, An eighth step of removing the barrier layer, the method for manufacturing a semiconductor device.

If throughput is important,
The second semiconductor film (gettering site) may be a single layer, and an amorphous silicon film having a thickness of 1 nm to 10 nm may be formed, and then plasma treatment of argon may be performed, which is an example of the manufacturing method disclosed in this specification. Configuration 2 includes a first step of forming a first semiconductor film having an amorphous structure on an insulating surface, and a second step of adding a metal element to the first semiconductor film having the amorphous structure. A third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a fourth step of forming a barrier layer on the surface of the first semiconductor film having the crystal structure. And a step of introducing a gas containing silane into the film forming chamber by a plasma CVD method to form an amorphous semiconductor film on the barrier layer, and silane from the film forming chamber on the surface of the semiconductor film. Introduce noble gas by removing gas containing The heat treatment is performed by a fifth step of forming a second semiconductor film containing a rare gas element by performing plasma treatment to generate a plasma and adding the rare gas element once or alternately. A first semiconductor film having a crystalline structure by gettering the metal element into the second semiconductor film.
Removing or reducing the metal element in the semiconductor film of
A method for manufacturing a semiconductor device, comprising: a step, a seventh step of removing the second semiconductor film, and an eighth step of removing the barrier layer.

It is also a feature of the present invention that the above film forming process and the plasma process can be performed in the same film forming chamber. Note that it is possible to perform the treatments in different processing chambers, but there is a possibility that the throughput is lowered and impurities are mixed.
Also, instead of adding a rare gas element by plasma treatment,
Although a rare gas element can be added by a doping device, there is a possibility that the throughput is lowered and impurities are mixed in like manner.

The film was formed by the plasma CVD method under the condition that film peeling (also called peeling) is unlikely to occur due to the heat treatment to be performed later and the second semiconductor film contains a large amount of a rare gas element. After that, if a rare gas plasma treatment is performed, the rare gas element can be contained in a higher concentration.

As such film forming conditions, monosilane and a rare gas element are used as a source gas, and the ratio (monosilane: rare gas) is 0.1: 99.9 to 1: 9, preferably 1:99 to. Control at 5:95, pressure is 1.333
Pa (0.01 Torr) to 66.65 Pa (0.5T
orr), preferably 53.32 Pa (0.4 Tor
It is a condition to be less than r). When the film forming pressure is higher than 66.65 Pa, a film is not formed but becomes powdery, or a film forming defect such as a hemispherical float is generated in the film. Furthermore, the RF power density is 0.0017W
/ Cm ^{2 to} 0.48 W / cm ² is desirable. Note that when the RF power is higher than 0.48 W / cm ² , the film is not formed into a powder, but is liable to be a powder, or a film-forming defect such as a hemispherical floating in the film is likely to occur. Further, disilane or trisilane may be used instead of monosilane.

By forming the second semiconductor film under the above conditions, the adhesion with the barrier layer can be enhanced, and peeling does not occur due to the heat treatment performed after the film formation. In addition, a gettering site containing a rare gas element in a high concentration and having a high gettering ability can be formed. Therefore, the second semiconductor film to be the gettering site can be thinned.

The second gettering site is also provided.
Plasma CVD as another process for forming the semiconductor film of
Method using monosilane and phosphine as source gases
(PH ₃) And a rare gas element, or
Orchid and phosphine (PH₃) And hydrogen, or source gas
As monosilane and phosphine (PH₃) And nitrogen
It has an amorphous structure containing phosphorus or a noble gas.
A semiconductor film may be formed.

A rare gas element may be added to the barrier layer. The barrier layer to which the rare gas element is added can also function as a gettering site. Specifically, a rare gas plasma may be generated to add the rare gas element to the surface of the barrier layer.

Structure 3 of the invention relating to the manufacturing method disclosed in this specification includes a first step of forming a semiconductor film having an amorphous structure on an insulating surface and a metal element in the semiconductor film having the amorphous structure. And a third step of crystallizing the semiconductor film to form a semiconductor film having a crystal structure, and a fourth step of forming a barrier layer on the surface of the semiconductor film having the crystal structure. A fifth step of generating plasma to add a rare gas element to the surface of the barrier layer, and a heat treatment to getter the metal element into the barrier layer to obtain the metal in the semiconductor film having a crystalline structure. A method for manufacturing a semiconductor device, comprising: a sixth step of removing or reducing an element; and a seventh step of removing the barrier layer.

After the plasma treatment of the rare gas element is performed on the barrier layer, the treatment of forming a semiconductor film containing the rare gas element and the plasma treatment of the rare gas element may be repeated. When plasma treatment is performed before film formation, adhesion is improved and peeling is less likely to occur.

Structure 4 of the invention relating to the manufacturing method disclosed in this specification is the first step of forming a first semiconductor film having an amorphous structure on an insulating surface and the first step having the amorphous structure. A second step of adding a metal element to the semiconductor film, a third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a first step having the crystal structure. A fourth step of forming a barrier layer on the surface of the semiconductor film, a fifth step of generating plasma to add a rare gas element to the surface of the barrier layer, and a film formation on the barrier layer by a plasma CVD method. A process of introducing a gas containing a rare gas and silane into the chamber to form a semiconductor film containing a rare gas element, and removing the gas containing silane from the film formation chamber with respect to the surface of the semiconductor film As the only gas, plasma is generated and the rare gas element is added. The second step of forming a second semiconductor film in which the concentration of the rare gas element on the surface is higher than that of the lower layer by performing the heat treatment once or twice or more, and heat treatment is performed. A seventh step of gettering the metal element to the semiconductor film to remove or reduce the metal element in the first semiconductor film having a crystalline structure;
And a ninth step of removing the barrier layer, and a method of manufacturing a semiconductor device.

Further, instead of the plasma treatment of the rare gas element, the plasma treatment of a gas containing carbon may be performed.

Structure 4 of the invention relating to the manufacturing method disclosed in this specification includes a first step of forming a first semiconductor film having an amorphous structure on an insulating surface and a first step of having the amorphous structure. A second step of adding a metal element to the semiconductor film, a third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a first step having the crystal structure. A fourth step of forming a barrier layer on the surface of the semiconductor film, and forming a semiconductor film containing a rare gas element on the barrier layer by introducing a gas containing a rare gas and silane into a deposition chamber by a plasma CVD method. A film forming process and a process of removing a gas containing a rare gas and silane from the film forming chamber on the surface of the semiconductor film and then introducing a gas containing carbon to generate plasma to add carbon. Second half by alternating once or twice or more A fifth step of forming a body film and heat treatment are performed to getter the metal element to the second semiconductor film to remove or reduce the metal element in the first semiconductor film having a crystalline structure. The sixth step, and the second
And a seventh step of removing the semiconductor film, and an eighth step of removing the barrier layer.

Further, instead of plasma treatment of rare gas element, plasma treatment of gas containing oxygen may be performed. The gettering using oxygen of the present invention utilizes the mechanism by which the precipitation of SiO ₂ promotes the precipitation of metal elements (such as nickel).

Structure 5 of the invention relating to the manufacturing method disclosed in this specification includes a first step of forming a first semiconductor film having an amorphous structure on an insulating surface and a first step having the amorphous structure. A second step of adding a metal element to the semiconductor film, a third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a first step having the crystal structure. A fourth step of forming a barrier layer on the surface of the semiconductor film, and forming a semiconductor film containing a rare gas element on the barrier layer by introducing a gas containing a rare gas and silane into a deposition chamber by a plasma CVD method. A treatment for forming a film, and a treatment for removing a gas containing a rare gas and silane from the film forming chamber on the surface of the semiconductor film, and then introducing a gas containing oxygen to generate plasma to add oxygen. Second half by alternating once or twice or more A fifth step of forming a body film and heat treatment are performed to getter the metal element to the second semiconductor film to remove or reduce the metal element in the first semiconductor film having a crystalline structure. The sixth step, and the second
And a seventh step of removing the semiconductor film, and an eighth step of removing the barrier layer.

In each of the above constitutions, the metal element is
Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, P
It is characterized by being one or more selected from t, Cu, and Au. When these metal elements are added to the semiconductor film having an amorphous structure, good crystallization is achieved.

In the present specification, the barrier layer refers to a layer having a film quality or a film thickness that allows a metal element to pass therethrough in the gettering step and also serving as an etching stopper in the step of removing the layer serving as the gettering site. ing. The barrier layer is a silicon oxide film or a silicon oxynitride film with a film thickness of 1 nm to 10 nm.

Further, in the present invention, the step of forming a film (barrier layer) to be a part of an etching stopper or a gettering site is performed by oxidizing the surface of the semiconductor film having a crystalline structure by irradiation with laser light, and then further. The step of oxidizing the surface of the semiconductor film having a crystalline structure with a solution containing ozone, the step of oxidizing the surface of the semiconductor film having a crystalline structure with a solution containing ozone, or the step of oxidizing the crystal structure by irradiation of ultraviolet rays in an oxygen atmosphere A step of oxidizing the surface of the semiconductor film included may be performed. Further, as another step of forming the barrier layer, a step of oxidizing the surface of the semiconductor film having a crystal structure by oxygen plasma treatment (a step of oxidizing with oxygen radicals) can also be mentioned. As another step of forming the barrier layer, a step of depositing an oxide film or an oxynitride film having a thickness of about 1 to 10 nm by a plasma CVD method, a sputtering method, an evaporation method, or the like may be used. As another step of forming the barrier layer, a thin oven may be formed on the surface of the semiconductor film having a crystalline structure by heating at about 200 to 350 ° C. using a clean oven. As another step of forming the barrier layer, any one of the above-mentioned forming methods or a combination of these methods may be formed.

In each of the above structures, the rare gas element is one or more selected from He, Ne, Ar, Kr, and Xe, and dangling bond can be obtained by incorporating these ions in the semiconductor film. A gettering site can be formed by forming a lattice strain or a lattice strain.

According to the present invention, it is possible to obtain a semiconductor film having a crystal structure in which a metal element that sufficiently promotes crystallization is reduced or removed, and in a TFT having the semiconductor film as an active layer, the electrical characteristics are improved, especially when the TFT is turned off. It is possible to reduce the current and the variation among the individual elements.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

(Embodiment Mode 1) A typical TFT manufacturing procedure using the present invention will be briefly described below with reference to FIG. Here, an example is shown in which a plasma CVD apparatus is used to perform a film formation process for the second semiconductor film and an argon plasma process for the surface of the second semiconductor film.

In FIG. 1A, 10 is a substrate having an insulating surface, 11 is an insulating film serving as a blocking layer, and 12 is a semiconductor film having an amorphous structure.

In FIG. 1A, the substrate 10 can be a glass substrate, a quartz substrate, a ceramic substrate, or the like. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this step may be used.

First, as shown in FIG. 1A, a base insulating film 1 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is formed on a substrate 10.
1 is formed. A typical example is 2 as the base insulating film 11.
The first silicon oxynitride film, which has a layered structure and is formed by using SiH ₄ , NH ₃ , and N ₂ O as reaction gases, has a thickness of 50 to 1
A structure is employed in which a second silicon oxynitride film formed by using 00 nm, SiH ₄ , and N ₂ O as reaction gases is laminated to a thickness of 100 to 150 nm. Further, as one layer of the base insulating film 11, a silicon nitride film (SiN film) having a film thickness of 10 nm or less, or a second silicon oxynitride film (SiN film).
It is preferable to use _x O _y film (X»Y)). At the time of gettering, nickel tends to move to a region having a high oxygen concentration. Therefore, it is extremely effective to use a silicon nitride film as a base insulating film which is in contact with the semiconductor film. Also, the first
A three-layer structure in which a silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used.

Next, the first semiconductor film 12 having an amorphous structure is formed on the base insulating film. First semiconductor film 12
Uses a semiconductor material containing silicon as a main component. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied, and a plasma CVD method or a low pressure CVD method is used.
Method or sputtering method to a thickness of 10 to 100 nm. In order to obtain a semiconductor film having a good crystal structure by the subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the film of the first semiconductor film 12 having an amorphous structure should be 5 × 10 5.
^{It is} preferable to reduce it to ¹⁸ / cm ³ (atomic concentration measured by secondary ion mass spectrometry (SIMS)) or less. These impurities become a factor that hinders later crystallization, and also becomes a factor that increases the density of trap centers and recombination centers even after crystallization. Therefore, not only high-purity material gas is used, but also ultra-high vacuum-compatible CV equipped with a mirror surface treatment (electrolytic polishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.
It is desirable to use the D device.

Next, as a technique for crystallizing the first semiconductor film 12 having an amorphous structure, here, Japanese Patent Laid-Open No. 8-7832 is used.
Crystallization is performed using the technique described in Japanese Patent No. The technique described in the publication is a crystal structure that expands from an added region as a starting point by selectively adding a metal element that promotes crystallization to an amorphous silicon film (also called an amorphous silicon film) and performing heat treatment. To form a semiconductor film having First, a nickel acetate salt solution containing 1 to 100 ppm by weight of a metal element (nickel in this case) having a catalytic action for promoting crystallization on the surface of the first semiconductor film 12 having an amorphous structure is spinnered. The nickel-containing layer 13 is formed by coating. (FIG. 1B) As a means other than the method of forming the nickel-containing layer 13 by coating, a method of forming an extremely thin film by a sputtering method, a vapor deposition method, or a plasma treatment may be used. In addition, although the example of coating the entire surface is shown here, a nickel-containing layer may be selectively formed by forming a mask.

Then, heat treatment is performed to perform crystallization.
In this case, in crystallization, silicide is formed in a portion of the semiconductor film which is in contact with a metal element that promotes crystallization of a semiconductor, and crystallization proceeds with the silicide as a nucleus. Thus, the first semiconductor film 14 having the crystal structure shown in FIG. 1C is formed. Note that the oxygen concentration contained in the first semiconductor film 14 after crystallization is preferably 5 × 10 ¹⁸ / cm ³ or less. Here, heat treatment for dehydrogenation (450 ° C.,
After 1 hour, heat treatment for crystallization (550 ° C. to 65 ° C.)
For 4 to 24 hours at 0 ° C. Further, when crystallization is performed by irradiation with intense light, any one of infrared light, visible light, or ultraviolet light or a combination thereof can be used, but typically, a halogen lamp, a metal halide, or the like. Light emitted from a lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp is used. The lamp light source is 1 to 60 seconds,
It is preferable to turn on the light for 30 to 60 seconds, repeat the operation 1 to 10 times, and instantaneously heat the semiconductor film to about 600 to 1000 ° C. Note that, if necessary, heat treatment for releasing hydrogen contained in the first semiconductor film 14 having an amorphous structure may be performed before irradiation with strong light. Also,
Crystallization may be performed by simultaneously performing heat treatment and intense light irradiation. Considering the productivity, it is desirable to perform crystallization by irradiating strong light.

The first semiconductor film 1 thus obtained
In 4, the metal element (here, nickel) remains. It is not evenly distributed in the membrane,
If the average concentration is exceeded, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ . Of course, even in such a state, it is possible to form various semiconductor elements including a TFT, but the element is removed by the gettering method of the present invention described below.

Then, in order to increase the crystallization rate (ratio of the crystal component in the total volume of the film) and repair the defects left in the crystal grains, laser light is applied to the first semiconductor film 14 having the crystal structure. Is preferably irradiated. When irradiated with laser light, a thin oxide film (not shown) is formed on the surface. As the laser light, excimer laser light having a wavelength of 400 nm or less emitted from a laser light source that is pulsed, or the second harmonic wave or the third harmonic wave of a YAG laser may be used. As the laser light, a solid-state laser capable of continuous oscillation may be used, and the second to fourth harmonics of the fundamental wave may be used. Typically, the second harmonic (532 nm) of the Nd: YVO ₄ laser (fundamental wave 1064 nm) or the third harmonic
A harmonic wave (355 nm) may be applied.

Since the oxide film formed by the irradiation of the laser beam after the crystallization is insufficient, an oxide film (called chemical oxide) is further formed with an ozone-containing aqueous solution (typically ozone water). And total 1-10 nm
The barrier layer 15 made of the oxide film is formed, and the second semiconductor film 16a containing a rare gas element is formed on the barrier layer 15. (Fig. 1 (D))

Here, the oxide film formed when the first semiconductor film 14 having a crystal structure is irradiated with laser light is also regarded as a part of the barrier layer. The barrier layer 15 functions as an etching stopper when only the second semiconductor film 16 is selectively removed in a later step. Further, instead of the ozone-containing aqueous solution, the chemical oxide can be similarly formed by treating with an aqueous solution in which sulfuric acid, hydrochloric acid, nitric acid and the like are mixed with hydrogen peroxide solution. As another method of forming the barrier layer 15, ozone may be generated by irradiation of ultraviolet rays in an oxygen atmosphere to oxidize the surface of the semiconductor film having the crystal structure. As another method for forming the barrier layer 15, plasma C is used.
A barrier layer may be formed by depositing an oxide film of about 1 to 10 nm by the VD method, the sputtering method, the vapor deposition method, or the like. As another method of forming the barrier layer 15, a clean oven may be used and heated to about 200 to 350 ° C. to form a thin oxide film. The barrier layer 15 formed by any one of the above methods or a combination of those methods.
Must have a film quality or a film thickness that allows nickel in the first semiconductor film to move to the second semiconductor film in later gettering.

The second semiconductor film 16a containing a rare gas element formed on the barrier layer is formed by the plasma CVD method,
Alternatively, it is formed by a sputtering method and the film thickness is 10 nm to 300 n.
m gettering site is formed. As rare gas elements, helium (He), neon (Ne), argon (A
One or more selected from r), krypton (Kr), and xenon (Xe) are used. Of these, argon (Ar), which is an inexpensive gas, is preferable.

Here, the PCVD method is used, monosilane and argon are used as source gases, and the ratio (monosilane: argon) is 0.1: 99.9 to 1: 9, preferably,
A film is formed by controlling 1:99 to 5:95. The RF power density during film formation is 0.0017 W / cm ^{2 to} 0.4.
It is desirable to set it to 8 W / cm ² . The higher the RF power density, the better the film formation rate, which is preferable. The pressure during film formation is 1.333 Pa (0.01
Torr) to 66.65 Pa (0.5 Torr), preferably less than 53.32 Pa (0.4 Torr). The higher the pressure, the better the film forming rate, which is preferable. The film forming temperature is 300 ° C to 5 ° C.
It is desirable to set the temperature to 00 ° C. Thus, the film contains argon at a concentration of 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²² / cm ³ , preferably 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ³ , and a gettering effect is obtained. The obtained second semiconductor film is plasma C
The film can be formed by the VD method. Furthermore, by setting the conditions for forming the second semiconductor film, it is possible to reduce the damage given to the barrier layer during the film formation, the occurrence of variation in the thickness of the first semiconductor film and the first semiconductor film. It is possible to prevent the occurrence of defects such as formation of holes in the film.

There are two meanings of containing the rare gas element ion which is an inert gas in the film. One is to form dangling bonds to give strain to the semiconductor film, and the other is to give strain to the lattice of the semiconductor film. In order to give strain to the lattice of the semiconductor film, it is remarkably obtained when an element having an atomic radius larger than that of silicon such as argon (Ar), krypton (Kr), and xenon (Xe) is used. Further, by containing a rare gas element in the film, not only lattice strain but also dangling bonds are formed, which contributes to the gettering action.

Then, the atmosphere in the chamber is set to argon only, plasma processing is performed, and argon is added.
Region 1 containing a high concentration of argon on the surface of the second semiconductor film
6b is formed. (Fig. 1 (E))

After the second semiconductor film is formed and plasma treatment is performed, heat treatment is performed to perform gettering for reducing or removing the concentration of the metal element (nickel) in the first semiconductor film. To do. (FIG. 1 (F)) As the heat treatment for gettering, a treatment of irradiating strong light, a heat treatment using a furnace, or a step of introducing the substrate into a heated gas,
It can be heated by leaving it for a few minutes and then taking it out. By this gettering, the metal element moves in the direction of the arrow in FIG. 1F (that is, the direction from the substrate side to the surface of the second semiconductor film), and the first metal layer is covered with the barrier layer 15.
The metal element contained in the semiconductor film 14 is removed or the concentration of the metal element is reduced. The distance that the metal element moves during gettering may be a distance of about the thickness of the first semiconductor film, and gettering can be completed in a relatively short time. Here, all of nickel is moved to the second semiconductor film 16 so that nickel is not segregated in the first semiconductor film 14, and almost no nickel contained in the first semiconductor film 14 exists, that is, the nickel concentration in the film is 1 ×. 10 ¹⁸ / c
Sufficient gettering is performed to m ³ or less, preferably 1 × 10 ¹⁷ / cm ³ or less. Not only the second semiconductor film but also the barrier layer 15 functions as a gettering site.

The second semiconductor film may be partially crystallized depending on the condition of the gettering heat treatment or the thickness of the second semiconductor film. When the second semiconductor film is crystallized, dangling bonds, lattice distortion, and dangling bonds are reduced, which leads to a reduction in gettering effect. Therefore, heat treatment in which the second semiconductor film is not crystallized is preferable. Or the thickness of the second semiconductor film. In any case, the second semiconductor film, that is, the amorphous silicon film containing a rare gas element is less likely to be crystallized than the amorphous silicon film containing no rare gas element, and thus is optimal as a gettering site. Is.

Depending on the conditions of this gettering heat treatment, the defects left in the crystal grains can be repaired at the same time as the gettering, that is, the crystallinity can be improved.

In this specification, gettering means that the metal element in the gettered region (here, the first semiconductor film) is released by thermal energy and moves to the gettering site by diffusion. . Therefore,
Gettering depends on the processing temperature, and the higher the temperature, the shorter the gettering. However, if the heat treatment temperature for gettering is high, the semiconductor film having an amorphous structure that serves as a gettering site may be crystallized and the gettering efficiency may be reduced. It is preferable to perform the heat treatment within a time period during which the crystallization does not occur.

When a treatment of irradiating strong light is used, irradiation may be continued within a range that the substrate can withstand, for example, a lamp light source for heating is turned on for about 3 minutes, and the semiconductor film is momentarily heated to 700 ° C. Allow to heat. Alternatively, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The light emission intensity of the lamp light source is arbitrary, but it is instantaneously 600 to 1000 ° C., preferably 700 to 750.
The semiconductor film is heated to about ° C.

When heat treatment is performed, the temperature is 450 to 800 ° C. in an inert atmosphere, typically in a nitrogen atmosphere,
The heat treatment may be performed for 24 hours, for example, at 550 ° C. for 4 hours. When the substrate is introduced into a furnace preheated to 450 to 800 ° C., it may be placed in the furnace preheated to 700 ° C. for 3 minutes for heat treatment. In addition to the heat treatment, strong light may be irradiated.

Next, the barrier layer 15 is etched by an etching stopper.
Select only the second semiconductor film indicated by 16 as a par
And then removing the barrier layer 15 to remove the first semiconductor film.
14 using a known patterning technique.
The conductor layer 17 is formed. (FIG. 1G) Second semiconductor film
As a method of selectively etching only ClF, ClF ₃
Dry etching without plasma or
Drazine and tetraethylammonium hydroxide
Id (chemical formula (CH₃)_FourAqueous solution containing (NOH)
Can be performed by wet etching with Lucari solution
It In addition, after removing the second semiconductor film, the surface of the barrier layer is removed.
Nickel concentration on the surface was measured by TXRF.
The barrier layer should be removed because the
Should be removed with an etchant containing hydrofluoric acid.
Good. Also, after removing the barrier layer, remove the resist
A thin oxide film on the surface with ozone water before forming the mask.
Is preferably formed.

After the step of forming the semiconductor layer 17 having a desired shape is completed, the surface of the semiconductor layer is washed with an etchant containing hydrofluoric acid to form an insulating film containing silicon as a main component to serve as the gate insulating film 18. It is desirable that the surface cleaning and the formation of the gate insulating film be continuously performed without exposing to the atmosphere.

Next, after cleaning the surface of the gate insulating film 18, the gate electrode 19 is formed. Then, in the semiconductor
A source region 20 and a drain region 21 are added by appropriately adding an impurity element imparting a type (P, As, etc.), here phosphorus.
To form. After the addition, heat treatment, strong light irradiation, or laser light irradiation is performed to activate the impurity element. At the same time as activation, plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor layer can be recovered. Especially room temperature to 300
It is very effective to activate the impurity element by irradiating the second harmonic wave of the YAG laser from the front surface or the back surface in the atmosphere of ° C. The YAG laser is a preferable activation means because it requires less maintenance.

In the subsequent steps, the interlayer insulating film 23 is formed,
Hydrogenation is performed to form a contact hole reaching the source region and the drain region, and a source electrode 24 and a drain electrode 25 are formed to complete a TFT (n-channel TFT). (Fig. 1 (H))

The concentration of the metal element contained in the channel formation region 22 of the TFT thus obtained is 1 × 10 ¹⁷ / cm ^3.
It can be less than.

Further, the present invention is not limited to the TFT structure of FIG. 1H, and if necessary, a low concentration drain (LDD: LDD: LDD region) between the channel forming region and the drain region (or source region). Lightly Doped Drain) structure. In this structure, a region where an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region which is formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. Furthermore, a so-called GOLD (Gate-drain) is formed in which the LDD region is arranged so as to overlap the gate electrode via a gate insulating film.
Overlapped LDD) structure.

Although the n-channel TFT is used for the description here, it is needless to say that the p-channel TFT can be formed by using the p-type impurity element instead of the n-type impurity element.

Although the top gate type TFT has been described as an example here, the present invention can be applied regardless of the TFT structure. For example, a bottom gate type (reverse stagger type) TFT or a forward stagger type TFT can be applied. It is possible to apply.

Although an example using a semiconductor film containing a rare gas element is shown here, a semiconductor film further containing a phosphorus element may be used, and instead of the semiconductor film containing a rare gas element, phosphorus element and A semiconductor film containing a rare gas element may be used. When forming a semiconductor film containing a phosphorus element and a rare gas element, phosphine may be added to the film formation gas. For example, a film may be formed using monosilane, phosphine (PH ₃ ) and argon.

(Embodiment Mode 2) Here, FIG. 2 shows an example in which a semiconductor film containing a rare gas element and plasma treatment are repeated a plurality of times to form gettering sites composed of laminated layers.

First, according to the first embodiment, an insulating film 31 serving as a blocking layer, a first semiconductor film, and
A metal element is added and heat treatment is performed to form the first semiconductor film 34 having a crystal structure. (Fig. 2 (A))

Then, according to the first embodiment, laser light is irradiated, and a barrier layer 35 made of an oxide film is formed from an ozone-containing aqueous solution. Then, a second semiconductor film 36a containing a rare gas element is formed. (Fig. 2 (B))

Then, according to the first embodiment, the atmosphere in the chamber is set to argon only, plasma processing is performed to add argon, and a region 36b containing high concentration of argon is formed on the surface of the second semiconductor film. (Fig. 2
(C))

Then, again, a third semiconductor film 36c containing a rare gas element is formed. (FIG. 2D) By doing so, the region 36b containing a high concentration of argon can be contained and a gettering site containing a rare gas element in a high concentration can be formed. In addition, the second semiconductor film and the third
The film thickness of the semiconductor film can be reduced, and peeling can be made less likely to occur.

Further, plasma treatment is performed again and argon is added to form a region 36d containing a high concentration of argon on the surface of the third semiconductor film. (FIG. 2E) The film formation and the plasma treatment can be repeated in the same chamber.

After the third semiconductor film is formed and plasma treatment is performed, heat treatment is performed to perform gettering for reducing or removing the concentration of the metal element (nickel) in the first semiconductor film. To do. (FIG. 2F) As heat treatment for gettering, intense light irradiation treatment, heat treatment using a furnace, or introducing a substrate into heated gas,
It can be heated by leaving it for a few minutes and then taking it out. By this gettering, the metal element moves in the direction of the arrow in FIG. 2F (that is, the direction from the substrate side to the surface of the second semiconductor film) and the first metal layer is covered with the barrier layer 35.
The metal element contained in the semiconductor film 34 is removed or the concentration of the metal element is reduced. The distance that the metal element moves during gettering may be a distance of about the thickness of the first semiconductor film, and gettering can be completed in a relatively short time. Here, the second semiconductor film 36b and the third semiconductor film 36b and the third semiconductor film 36b are prevented from segregating nickel into the first semiconductor film 31.
Of the first semiconductor film 31 is almost absent, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably 1 × 1.
Sufficient gettering is performed so as to be 0 ¹⁷ / cm ³ or less.
Note that not only the second semiconductor film and the third semiconductor film but also the barrier layer 35 functions as a gettering site.

Then, using the barrier layer 35 as an etching stopper, the second semiconductor films 36a and 36c are formed.
After selectively removing only the third semiconductor film, the barrier layer 3
5 is removed, and a semiconductor layer having a desired shape is formed on the first semiconductor film 34 by using a known patterning technique.

The subsequent steps are the TF according to the first embodiment.
All you have to do is complete T. Here, since it is the same as the process shown in the first embodiment, detailed description will be omitted.

Although the example of forming the gettering site by repeating the film formation of the semiconductor film containing a rare gas element and the plasma treatment twice is shown here, the gettering site may be formed by repeating the gettering site twice or more. Good.

The present inventor conducted the following experiment.

After performing argon plasma treatment on the substrate, a material gas of SiH ₄ (flow rate of 100 sccm) / Ar (flow rate of 500 sccm) was used by plasma CVD to form an amorphous silicon film having a thickness of 20 nm at a substrate temperature of 300 ° C. and 20 W. After the film formation, the argon plasma treatment and the formation of the amorphous silicon film with a film thickness of 20 nm were repeated twice, and finally the argon plasma treatment was performed, and the result of measuring the Ar / Si concentration ratio by TXRF is shown in FIG. Shown in. In addition, the film forming pressure is 0.2 Torr,
It was measured as 0.4 Torr and 0.6 Torr, respectively, and is indicated by a circle in FIG.

In addition, as a comparative example, after performing argon plasma treatment on the substrate, the material gas is changed to SiH ₄ (flow rate 100 sccm) / Ar (flow rate 50) by the plasma CVD method.
0 sccm), substrate temperature 300 ° C., 50 n at 20 W
After forming an amorphous silicon film with a thickness of m, TX
The result of measuring the Ar / Si concentration ratio by RF is shown in FIG. The film forming pressures are 0.2 Torr and 0.4, respectively.
As measured as Torr and 0.6 Torr, respectively, as shown in FIG.
The inside is indicated by a cross.

From FIG. 4, it can be seen that, as compared with the single layer (marked with X) which is the comparative example, the sample (marked with ◯) which is subjected to the argon plasma treatment after lamination can contain a high concentration of argon on the surface. Can be read.

(Embodiment 3) Here, FIG. 3 shows an example in which a plasma treatment is performed on an oxide film and a barrier layer made of the oxide film is used as a gettering site.

Further, the present inventor conducted the following experiment.

SiH ₄ , NH ₃ , and N ₂ on a glass substrate
A first silicon oxynitride film having a film thickness of 50 nm formed by using O as a reaction gas, and a _second silicon oxynitride film having a film thickness of 50 nm formed by using SiH ₄ and N ₂ O as reaction gases are laminated. The base insulating film described above was formed, and three amorphous silicon films having different oxygen concentrations were laminated in a thickness of 150 nm. Note that amorphous silicon films having different oxygen concentrations were formed by different CVD devices. Then, a solution containing nickel (100 ppm) was applied by spin coating, followed by heat treatment at 500 ° C. for 1 hour, and then heat treatment at 550 ° C. for 8 hours to examine how nickel diffused. . The results obtained by SIMS analysis of nickel concentration and oxygen concentration are shown in FIG.

From these results (FIG. 5), a large amount of nickel tends to gather in the region where the oxygen content is high, the oxygen concentration is very high between layers having different oxygen concentrations, and nickel is also detected at a high concentration. The natural oxide film formed at the interface from the surface has the ability to getter. In addition, the gettering effect was similarly confirmed for the oxide film formed by ozone water.

First, according to the first embodiment, the insulating film 41 to be the blocking layer and the first semiconductor film are formed on the substrate 40. (FIG. 3 (A)) Next, according to the first embodiment, a metal element is added. (Fig. 3 (B)) Then,
According to the first embodiment, heat treatment is performed to form first semiconductor film 44 having a crystalline structure. (Fig. 3 (C))

Then, according to the first embodiment, laser light is irradiated, and a barrier layer 45a made of an oxide film is further formed with an ozone-containing aqueous solution. (Fig. 3 (D))

Then, the atmosphere in the chamber is set to argon only and plasma treatment is performed to form a barrier layer 45b to which high-concentration argon is added. (Fig. 3 (E))

Next, heat treatment is performed to perform gettering for reducing or removing the concentration of the metal element (nickel) in the first semiconductor film. (FIG. 3 (F)) The heat treatment for performing gettering includes a treatment of irradiating strong light,
Heating may be performed by heat treatment using a furnace, or by putting the substrate in a heated gas, leaving it for a few minutes, and then taking it out. By this gettering, the direction of the arrow in FIG. 3F (that is, the direction from the substrate side to the barrier layer surface).
Barrier layer 4 to which the metal element has moved and argon has been added
The metal element contained in the first semiconductor film 44 covered with 5b is removed or the concentration of the metal element is reduced.

Then, the barrier layer 45b is removed, and a semiconductor layer having a desired shape is formed on the first semiconductor film 44 by using a known patterning technique.

The subsequent steps are the TF according to the first embodiment.
All you have to do is complete T. Here, since it is the same as the process shown in the first embodiment, detailed description will be omitted.

Further, this embodiment mode can be freely combined with Embodiment Modes 1 and 2. For example, after the plasma treatment of argon is added to the barrier layer, the second semiconductor film containing a rare gas is formed, and the plasma treatment of argon may be further performed to add high concentration of argon to the surface. By performing plasma treatment, adhesion between films can be improved and peeling can be suppressed.

The present invention having the above structure will be described in more detail with reference to the following embodiments.

(Example) [Example 1] An example of the present invention will be described with reference to Figs. Here, a pixel portion and TFTs (n-channel type TFT and p-type TFT) of a driving circuit provided around the pixel portion are provided on the same substrate.
A method of simultaneously producing channel type TFTs will be described in detail.

First, the base insulating film 101 is formed over the substrate 100 to obtain a first semiconductor film having a crystal structure, and then the semiconductor layers 102 to 106 separated into islands by etching into a desired shape. To form.

As the substrate 100, a glass substrate (# 17
37) and plasma C is used as the base insulating film 101.
By the VD method, the film formation temperature is 400 ° C., the source gases SiH ₄ , NH ₃ ,
Silicon oxynitride film 101a made of N ₂ O (composition ratio Si = 32%, O = 27%, N = 24%, H = 17
%) Is formed to 50 nm (preferably 10 to 200 nm).
Next, after cleaning the surface with ozone water, the oxide film on the surface is removed with dilute hydrofluoric acid (diluted by 1/100). Then, the film formation temperature is 400 ° C. by the plasma CVD method, and the source gas is SiH ₄ , N ₂
A silicon oxynitride film 101b made of O (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) was used as 1
A semiconductor film having an amorphous structure (here, amorphous) is formed by laminating a film having a thickness of 00 nm (preferably 50 to 200 nm) and forming the film by a plasma CVD method at a film forming temperature of 300 ° C. and a film forming gas SiH ₄ without exposing to the atmosphere. Silicon film) 54 nm
Is formed (preferably 25 to 80 nm).

Although the base film 101 has a two-layer structure in this embodiment, it may have a single-layer structure of the insulating film or a structure in which two or more layers are laminated. The material of the semiconductor film is not limited, but is preferably silicon or silicon germanium (Si _x Ge _1-x (X = 0.0001 to 0.0).
2)) Using alloys or the like, known means (sputtering method, LP
It may be formed by a CVD method, a plasma CVD method, or the like. Further, the plasma CVD apparatus may be a single wafer type apparatus or a batch type apparatus. Alternatively, the base insulating film and the semiconductor film may be successively formed in the same film formation chamber without exposure to the air.

Then, after cleaning the surface of the semiconductor film having an amorphous structure, an extremely thin oxide film of about 2 nm is formed on the surface with ozone water. Next, a slight amount of impurity element (boron or phosphorus) is doped to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used, the doping condition is an acceleration voltage of 15 kV, and diborane is hydrogen at 1%.
Flow rate of diluted gas to 30 sccm, dose amount 2 × 10 ¹²
Boron was added to the amorphous silicon film at a rate of / cm ² .

Then, a nickel acetate salt solution containing 10 ppm by weight of nickel is applied by a spinner. Instead of coating, a method of spattering nickel element over the entire surface by a sputtering method may be used.

Next, heat treatment is performed for crystallization to form a semiconductor film having a crystal structure. For this heat treatment, heat treatment of an electric furnace or irradiation of strong light may be used. When it is performed by heat treatment in an electric furnace, it is 4 to 24 at 500 to 650 ° C.
You can do it in time. Here, after the heat treatment for dehydrogenation (500 ° C., 1 hour), the heat treatment for crystallization (5
50 ° C., 4 hours) to obtain a silicon film having a crystal structure. Although crystallization is performed here by heat treatment using a furnace, crystallization may be performed by a lamp annealing apparatus that can perform crystallization in a short time. Although a crystallization technique using nickel as a metal element that promotes crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.

Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, the crystallization rate is increased,
Irradiation with laser light (XeCl: wavelength 308 nm) for repairing defects left in crystal grains is performed in the air or an oxygen atmosphere. As the laser light, excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of YAG laser are used. Here, the repetition frequency is 10 to 1
Using pulsed laser light of about 000 Hz, the laser light is condensed to 100 to 500 mJ / cm ² by an optical system, and 90 to
Irradiation may be performed with an overlap ratio of 95% to scan the surface of the silicon film. Here, the repetition frequency 3
Irradiation with laser light was performed in the atmosphere at 0 Hz and an energy density of 470 mJ / cm ² . Since it is performed in the air or in an oxygen atmosphere, an oxide film is formed on the surface by laser light irradiation. Note that although an example using a pulsed laser is shown here, a continuous wave laser may be used, and continuous wave generation is possible in order to obtain crystals with a large grain size when crystallizing an amorphous semiconductor film. It is preferable to use a solid laser and apply the second to fourth harmonics of the fundamental wave. Typically, the second harmonic (532 nm) or the third harmonic (355 nm) of the Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. When using a continuous wave laser,
Laser light emitted from a continuous oscillation YVO ₄ laser with an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method in which a YVO ₄ crystal and a non-linear optical element are put in a resonator to emit a higher harmonic wave. Then, preferably, a rectangular or elliptical laser beam is formed on the irradiation surface by an optical system, and the object to be processed is irradiated. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, the semiconductor film may be moved relative to the laser light at a speed of about 10 to 2000 cm / s for irradiation.

Next, in addition to the oxide film formed by the laser light irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm. In this example, the barrier layer was formed using ozone water, but the method of oxidizing the surface of the semiconductor film having a crystal structure by irradiation of ultraviolet rays in an oxygen atmosphere or the surface of the semiconductor film having a crystal structure by oxygen plasma treatment was used. 1 to 10 nm by oxidation method, plasma CVD method, sputtering method, vapor deposition method, etc.
A barrier layer may be formed by depositing a certain amount of oxide film. Further, the oxide film formed by laser light irradiation may be removed before forming the barrier layer.

Next, an amorphous silicon film containing an argon element, which becomes a gettering site, is formed on the barrier layer by a plasma CVD method so as to have a thickness of 10 nm to 400 nm.
After being formed to a thickness of nm, an argon plasma treatment is performed. The film forming conditions of this embodiment are the flow ratio of monosilane and argon (S
iH ₄ : Ar) is 1:99, and the film forming pressure is 6.665.
Pa (0.05 Torr), and RF power density of 0.
The temperature is 087 W / cm ² and the film forming temperature is 350 ° C.

Then, the resultant is placed in a furnace heated to 650 ° C. and heat-treated for 3 minutes to perform gettering to reduce the nickel concentration in the semiconductor film having a crystalline structure. A lamp annealing device may be used instead of the furnace.

Then, the barrier layer is used as an etching stopper to selectively remove the amorphous silicon film containing the argon element which is the gettering site, and then the barrier layer is selectively removed with dilute hydrofluoric acid. In addition, at the time of gettering,
Since nickel tends to move to a region having a high oxygen concentration, it is desirable to remove the barrier layer made of an oxide film after gettering.

Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also referred to as a polysilicon film), a mask made of a resist is formed, and an etching treatment is performed into a desired shape. Forming a semiconductor layer separated into islands. After forming the semiconductor layer, the resist mask is removed.

Then, after removing the oxide film with an etchant containing hydrofluoric acid, the surface of the silicon film is washed at the same time.
An insulating film containing silicon as its main component is formed to be the gate insulating film 303. Here, 115 n is formed by the plasma CVD method.
m thickness of silicon oxynitride film (composition ratio Si = 32%,
O = 59%, N = 7%, H = 2%).

Next, as shown in FIG. 6A, a first conductive film 108a having a film thickness of 20 to 100 nm and a second conductive film 1 having a film thickness of 100 to 400 nm are formed on the gate insulating film 107.
08b is formed by stacking. In this embodiment, a tantalum nitride film having a thickness of 50 nm and a thickness of 370 are formed on the gate insulating film 107.
nm tungsten films are sequentially stacked.

As the conductive material for forming the first conductive film and the second conductive film, Ta, W, Ti, Mo, Al, Cu
It is formed of an element selected from the above or an alloy material or a compound material containing the above element as a main component. A semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus as the first conductive film and the second conductive film,
You may use AgPdCu alloy. Further, the structure is not limited to the two-layer structure.
A three-layer structure in which a Si) film and a titanium nitride film having a film thickness of 30 nm are sequentially laminated may be used. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum may be used instead of the aluminum-silicon alloy (Al-Si) film of the second conductive film. An alloy film of titanium (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film.
Further, it may have a single layer structure.

Next, as shown in FIG. 6B, masks 110 to 115 made of resist are formed by a light exposure process, and a first etching process for forming gate electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. ICP (In
It is advisable to use an inductively coupled plasma etching method. Using ICP etching method,
Etching conditions (electric power applied to the coil type electrode,
By appropriately adjusting the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc., the film can be etched into a desired tapered shape. As the etching gas, chlorine-based gas represented by Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ or the like or CF ₄ , SF ₆ , NF _{3 is used.}
A fluorine-based gas typified by, for example, or O ₂ can be appropriately used.

In this embodiment, 150 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil type electrode area size (here, a quartz disk provided with a coil) is a disk having a diameter of 25 cm. The W film is etched under the first etching condition so that the end portion of the first conductive layer is tapered. The etching rate for W under the first etching condition is 200.39 nm / m
Etching rate for in and TaN is 80.32 nm
/ Min, and the selection ratio of W to TaN is about 2.5.
Is. In addition, depending on the first etching condition, W
The taper angle of is about 26 °. Thereafter, the masks 110 to 115 made of resist are not removed, and the second etching condition is changed to CF ₄ and Cl _{2 as} etching gas, and the gas flow rate ratio of each is 30/30 (sccm).
With a pressure of 1 Pa, RF (1 W
(3.56 MHz) Power was applied to generate plasma and etching was performed for about 30 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / min, Ta
The etching rate for N is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased at a rate of about 10 to 20%.

In the first etching process, the shape of the mask made of resist is made suitable,
The edges of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 °.

Thus, the first shape conductive layers 117 to 121 (first conductive layers 117a to 121a and second conductive layer 117b) formed of the first conductive layer and the second conductive layer are formed by the first etching treatment. ~ 121b) are formed. The insulating film 107 to be a gate insulating film is etched by about 10 to 20 nm, and becomes a gate insulating film 116 in which a region which is not covered with the first shape conductive layers 117 to 121 is thinned.

Next, a second etching process is performed without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, and the gas flow rate ratios thereof are set to 24/12/24 (sccm).
700W RF (13.56MH) on coil type electrode with pressure of Pa
z) Applying electric power to generate plasma for etching 2
It went for 5 seconds. RF of 10W on the substrate side (sample stage)
(13.56MHz) Apply power and apply substantially negative self-bias voltage. In the second etching treatment, the etching rate for W is 227.3 nm / min, the etching rate for TaN is 32.1 nm / min, and
The selection ratio of W to aN is 7.1, and the insulating film 116 is
Etching rate for SiON is 33.7 nm
/ Min, and the selection ratio of W to SiON is 6.8.
It is 3. As described above, when SF ₆ is used as the etching gas, the selection ratio with the insulating film 116 is high, so that film loss can be suppressed. In this embodiment, the insulating film 116 is reduced in thickness by about 8 nm.

The taper angle of W became 70 ° by this second etching treatment. By this second etching process, second conductive layers 124b to 129b are formed. On the other hand, the first conductive layer is hardly etched,
Of the conductive layers 124a to 129a. Note that the first conductive layers 124a to 129a are the first conductive layers 117a to 12a.
It is almost the same size as 2a. Actually, the width of the first conductive layer is about 0.3 μm as compared with that before the second etching process.
In some cases, the line width may recede by about 0.6 μm, but there is almost no change in size.

Further, instead of the two-layer structure, a three-layer structure in which a tungsten film with a film thickness of 50 nm, an alloy of aluminum and silicon (Al-Si) film with a film thickness of 500 nm, and a titanium nitride film with a film thickness of 30 nm are sequentially laminated is provided. In this case, as the first etching condition of the first etching process, BCl ₃ , Cl ₂ and O ₂ are used as source gases, and the gas flow rate ratio of each is set to 65/10/5 (sccm). The RF power (13.56 MHz) of 300 W is applied to the (sample stage), and the RF power (13.56 MHz) of 450 W is applied to the coil-shaped electrode at a pressure of 1.2 Pa to generate plasma for 117 seconds. Etching may be performed. As the second etching condition of the first etching process, CF ₄ , Cl _2, and O ₂ are used, and the gas flow rate ratio of each is 25/2.
5/10 (sccm), 20W of RF (13.56MHz) power was also applied to the substrate side (sample stage),
RF of 500 W (13.
56MHz) Power is generated and plasma is generated for about 30
It suffices to perform the etching for about a second. BCl ₃ and Cl ₂ are used as the second etching treatment, and the gas flow rate ratio of each is set to 20/60 (sccm), and the substrate side (sample stage)
RF (13.56 MHz) power of 100 W is applied to the coil, and a pressure of 1.2 Pa is applied to the coil-shaped electrode to generate R of 600 W.
It suffices to apply F (13.56 MHz) power to generate plasma and perform etching.

Next, after removing the resist mask, the first doping process is performed to obtain the state of FIG. 6 (D). The doping treatment may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are a dose amount of 1.5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60.
~ 100 keV. Phosphorus (P) or arsenic (As) is typically used as the impurity element imparting n-type. In this case, the first conductive layer and the second conductive layer 124
~ 128 serves as a mask for the impurity element imparting n-type, and the first impurity regions 130 to 134 are formed in a self-aligned manner. 1 × in the first impurity regions 130 to 134
An impurity element imparting n-type is added within a concentration range of 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . Here, a region having the same concentration range as the first impurity region is also called an n ⁻ region.

Although the first doping process is performed after removing the resist mask in this embodiment, the first doping process may be performed without removing the resist mask.

Next, as shown in FIG. 7A, masks 135 to 137 made of resist are formed and a second doping process is performed. A mask 135 is a mask that protects a channel formation region of a semiconductor layer forming a p-channel TFT of a drive circuit and a peripheral region thereof, and a mask 136 is a semiconductor layer forming one of n-channel TFTs of the drive circuit. The mask is a mask that protects the channel formation region and its peripheral region, and the mask 137 is a mask that protects the channel formation region of the semiconductor layer forming the TFT of the pixel portion, the peripheral region thereof, and the region serving as the storage capacitor.

The condition of the ion doping method in the second doping process is that the dose amount is 1.5 × 10 ¹⁵ atoms / cm ² and the accelerating voltage is 60 to 100 keV, and phosphorus (P) is doped. Here, the second conductive layers 124 b to 1
Impurity regions are formed in each semiconductor layer in a self-aligned manner using 26b as a mask. Of course, it is not added to the region covered with the masks 135 to 137. Thus, the second impurity regions 138 to 140 and the third impurity region 142 are formed. 1 × 10 ²⁰ is formed in the second impurity regions 138 to 140.
An impurity element imparting n-type is added in a concentration range of 1 × 10 ²¹ / cm ³ . Here, a region having the same concentration range as the second impurity region is also called an n ⁺ region.

Further, the third impurity region is formed at a lower concentration than the second impurity region by the first conductive layer, and has a concentration of 1 × 1.
An impurity element imparting n-type is added in the concentration range of 0 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . Note that the third impurity region has a concentration gradient in which the impurity concentration increases toward the end portion of the tapered portion because doping is performed by passing through the portion of the first conductive layer having a tapered shape. . Here, a region having the same concentration range as the third impurity region is also called an n ⁻ region. Further, in the region covered with the masks 136 and 137, the impurity element is not added in the second doping treatment,
The first impurity regions 144 and 145 are formed.

Next, the masks 135 made of resist are formed.
After removing 137, a mask 1 newly made of resist
46 to 148 are formed and a third doping process is performed as shown in FIG.

In the drive circuit, by the third doping process, a fourth impurity element imparting p-type conductivity is added to the semiconductor layer forming the p-channel TFT and the semiconductor layer forming the storage capacitor. Impurity region 149,
150 and fifth impurity regions 151 and 152 are formed.

Further, in the fourth impurity regions 149 and 150,
Is 1 × 10²⁰~ 1 x 10^{twenty one}/cm³P-type in the concentration range of
The impurity element to be added is added. In addition, the fourth failure
Phosphorus (P) was added to the pure regions 149 and 150 in the previous step.
Added region (n^-Region), but the
Conductive because the concentration of pure element is 1.5 to 3 times that of pure element
The mold is p-type. Here, the fourth impurity region and
P in the same concentration range ⁺Also called a region.

The fifth impurity regions 151 and 152 are formed in a region overlapping the tapered portion of the second conductive layer 125a, and have a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. An impurity element imparting p-type is added. Here, a region having the same concentration range as the fifth impurity region is also called ap ⁻ region.

By the steps up to this point, each semiconductor layer is n-doped.
An impurity region having a conductivity type of p-type or p-type is formed. The conductive layers 124 to 127 become gate electrodes of the TFT. In addition, the conductive layer 128 serves as one electrode which forms a storage capacitor in the pixel portion. Further, the conductive layer 129 forms a source wiring in the pixel portion.

Next, an insulating film (not shown) is formed to cover almost the entire surface. In this embodiment, a silicon oxide film having a film thickness of 50 nm is formed by the plasma CVD method. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Then, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating the back surface with a YAG laser or an excimer laser, a heat treatment using a furnace, or a combination of these methods. By the method.

In this embodiment, an example in which the insulating film is formed before the activation is shown, but after the activation is performed,
It may be a step of forming an insulating film.

Next, a step of hydrogenating the semiconductor layer is performed by forming a first interlayer insulating film 153 made of a silicon nitride film and performing heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). (FIG. 7C) This step is a step of terminating the dangling bond of the semiconductor layer by hydrogen contained in the first interlayer insulating film 153. The semiconductor layer can be hydrogenated regardless of the presence of an insulating film (not shown) made of a silicon oxide film. However, in this embodiment, since the material containing aluminum as the main component is used as the second conductive layer, it is important to set the heat treatment conditions that the second conductive layer can withstand in the hydrogenation step. Plasma hydrogenation (using hydrogen excited by plasma) may be performed as another means of hydrogenation.

Then, a second interlayer insulating film 154 made of an organic insulating material is formed on the first interlayer insulating film 153. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed. Next, a contact hole reaching the source wiring 129, a contact hole reaching the conductive layers 127 and 128, and a contact hole reaching each impurity region are formed. In this embodiment, a plurality of etching processes are sequentially performed.
In this embodiment, after etching the second interlayer insulating film using the first interlayer insulating film as an etching stopper, the first interlayer insulating film is etched using an insulating film (not shown) as an etching stopper, and then the insulating film (illustrated). Not etched).

After that, wirings and pixel electrodes are formed using Al, Ti, Mo, W or the like. As a material of these electrodes and pixel electrodes, it is desirable to use a material having excellent reflectivity such as a film containing Al or Ag as a main component, or a laminated film thereof. Thus, the source or drain electrodes 155 to 160, the gate wiring 162, the connection wiring 161,
The pixel electrode 163 is formed.

As described above, the n-channel TFT 20
1, p-channel TFT 202, n-channel TFT 2
The pixel portion 207 including the driver circuit 206 including the pixel 03, the pixel TFT 204 including the n-channel TFT, and the storage capacitor 205 can be formed over the same substrate. (FIG. 8) In this specification, such a substrate is referred to as an active matrix substrate for convenience. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the pixel portion 207, the pixel TFT 204
The (n-channel TFT) has a channel forming region 167,
It has a first impurity region (n ⁻ region) 145 formed outside the conductive layer 127 forming the gate electrode and a second impurity region (n ⁺ region) 140 functioning as a source region. Further, a fourth impurity region 150 and a fifth impurity region 152 are formed in the semiconductor layer functioning as one electrode of the storage capacitor 205. The storage capacitor 205 has an insulating film (same film as the gate insulating film) 116 as a dielectric.
The second electrode 128 and the semiconductor layers 150, 152, 168
It is formed by.

In the drive circuit 206, the n-channel TFT 201 (first n-channel TFT) is the channel formation region 164 and the conductive layer 12 forming the gate electrode.
4 and a third impurity region (n
^- has a second impurity region (n ⁺ region) 138 functioning as a region) 142 and a source region or a drain region.

In the drive circuit 206, the p-channel TFT 202 has a channel forming region 165 and a fifth impurity region (p ⁻ region) 151 which overlaps with a part of the conductive layer 125 forming the gate electrode via an insulating film. A fourth impurity region (p
⁺ Area) 149.

In the drive circuit 206, the n-channel TFT 203 (second n-channel TFT) has a channel forming region 166 and a conductive layer 1 for forming a gate electrode.
A first impurity region (n ⁻ region) 144 and a second impurity region (n ⁺ region) 139 functioning as a source region or a drain region are provided outside 26.

A drive circuit 206 may be formed by appropriately combining these TFTs 201 to 203 to form a shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like. For example, when forming a CMOS circuit, an n-channel TFT 201 and a p-channel TFT
It may be formed by connecting 202 complementarily.

In particular, for a buffer circuit having a high driving voltage,
The structure of the n-channel TFT 203 is suitable for the purpose of preventing deterioration due to the hot carrier effect.

For a circuit in which reliability is the highest priority,
The structure of the n-channel TFT 201 having the GOLD structure is suitable.

Since the reliability can be improved by improving the flatness of the surface of the semiconductor film, G
In the TFT having the OLD structure, sufficient reliability can be obtained even if the area of the impurity region overlapping the gate electrode and the gate insulating film is reduced. Specifically, in the GOLD structure TFT, sufficient reliability can be obtained even if the size of the gate electrode tapered portion is reduced.

In the GOLD structure TFT, the parasitic capacitance increases as the gate insulating film becomes thinner. However, if the size of the tapered portion of the gate electrode (first conductive layer) is reduced to reduce the parasitic capacitance, The f-characteristics are also improved, the higher speed operation is possible, and the TFT has sufficient reliability.

In addition, although an example of manufacturing an active matrix substrate for forming a reflection type display device is shown in this embodiment, when the pixel electrode is formed of a transparent conductive film, the number of photomasks is increased by one, but the transmission is increased. Mold display device can be formed.

[Embodiment 2] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 9 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state of FIG. 8, an alignment film is formed on the active matrix substrate of FIG. 8 and rubbing treatment is performed. In this embodiment, before forming the alignment film, the organic resin film such as the acrylic resin film was patterned to form the columnar spacers for holding the substrate distance at desired positions. Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, a counter substrate is prepared. The counter substrate is provided with a color filter in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Further, a light-shielding layer was also provided in the drive circuit portion. A flattening film was provided to cover the color filter and the light shielding layer. Next, a counter electrode made of a transparent conductive film is formed on the flattening film in the pixel portion, an alignment film is formed on the entire surface of the counter substrate, and rubbing treatment is performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded together with a sealant. A filler is mixed in the sealing material, and the two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. After that, a liquid crystal material is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device is completed. Then, if necessary, the active matrix substrate or the counter substrate is cut into a desired shape. Further, an optical film such as a polarizing plate or a retardation plate is appropriately provided by using a known technique. Then, using a known technique, the FP
Paste C.

The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG.

A pixel portion 304 is arranged in the center of the active matrix substrate 301. A source signal line driver circuit 302 for driving a source signal line is arranged above the pixel portion 304. A gate signal line driver circuit 303 for driving a gate signal line is arranged on the left and right of the pixel portion 304. In the example shown in this embodiment,
Although the gate signal line driving circuit 303 is arranged symmetrically with respect to the pixel portion, it may be arranged on only one side and may be appropriately selected by the designer in consideration of the substrate size of the liquid crystal module and the like. However, considering the operational reliability of the circuit, the driving efficiency, etc., the bilaterally symmetrical arrangement shown in FIG. 9 is desirable.

Input of a signal to each drive circuit is performed by a flexible print circuit (FPC) 3
It starts from 05. The FPC 305 opens a contact hole in the interlayer insulating film and the resin film so as to reach the wiring arranged up to a predetermined position on the substrate 301, and
After forming 09, it is pressure-bonded through an anisotropic conductive film or the like. In this embodiment, the connection electrode is made of ITO.

A sealant 307 is applied to the periphery of the drive circuit and the pixel portion along the outer periphery of the substrate, and a constant gap (distance between the substrate 301 and the counter substrate 306 is formed by a spacer 310 formed on the active matrix substrate in advance. ) Is maintained, the counter substrate 306 is attached. After that, a liquid crystal element is injected from a portion where the sealant 307 is not applied and is sealed with a sealant 308. The liquid crystal module is completed through the above steps.

Although an example in which all the driving circuits are formed on the substrate is shown here, several ICs may be used as a part of the driving circuits.

Further, this embodiment can be freely combined with the first embodiment.

[Embodiment 3] In Embodiment 1, an example of a reflection type display device in which the pixel electrode is formed of a metal material having reflectivity is shown, but in this embodiment, the pixel electrode is made of a light-transmitting conductive material. An example of a transmissive display device formed of a film is shown.

Example 1 is performed up to the step of forming the interlayer insulating film.
Since it is the same as, it is omitted here. After the interlayer insulating film is formed according to Example 1, the pixel electrode 601 made of a light-transmitting conductive film is formed. As the light-transmitting conductive film, ITO (indium oxide-tin oxide alloy), indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like may be used.

After that, a contact hole is formed in the interlayer insulating film 600. Next, the connection electrode 6 overlapping the pixel electrode
02 is formed. The connection electrode 602 is connected to the drain region through a contact hole. At the same time as the connection electrode, the source electrode or drain electrode of another TFT is also formed.

Although an example in which all the driving circuits are formed on the substrate is shown here, several ICs may be used as a part of the driving circuits.

The active matrix substrate is formed as described above. Using this active matrix substrate, a liquid crystal module was manufactured according to Example 2, provided with a backlight 604 and a light guide plate 605, and covered with a cover 606, an active matrix type as shown in a partial sectional view of FIG. The liquid crystal display device is completed. The cover and the liquid crystal module are attached to each other with an adhesive or an organic resin. When the substrate and the counter substrate are attached to each other, they may be surrounded by a frame and filled with an organic resin between the frame and the substrate for adhesion. Since it is a transmissive type, the polarizing plate 603 is attached to both the active matrix substrate and the counter substrate.

Further, this embodiment can be freely combined with the first embodiment or the second embodiment.

[Embodiment 4] In this embodiment, an example of manufacturing a light emitting display device having an organic light emitting device (OLED: Organic Light Emitting Device) is shown in FIG.

The OLED has a layer containing an organic compound (organic light emitting material) capable of obtaining luminescence generated by applying an electric field (hereinafter, referred to as an organic light emitting layer), an anode and a cathode. There is. Luminescence in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission when returning to a ground state from a triplet excited state (phosphorescence). One of the above-mentioned light emissions may be used, or both of the light emissions may be used.

In this specification, all the layers formed between the anode and the cathode of the OLED are defined as the organic light emitting layer.
The organic light emitting layer specifically includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, an OLED has a structure in which an anode, a light emitting layer, and a cathode are laminated in this order, and in addition to this structure, an anode / hole injection layer /
It may have a structure in which a light emitting layer / cathode or an anode / hole injection layer / light emitting layer / electron transport layer / cathode are laminated in this order.

FIG. 11A is a top view of a module having an OLED, a so-called EL module, FIG. 11B.
11A is a cross-sectional view taken along the line AA ′ in FIG. A pixel portion 902, a source side driver circuit 901, and a gate side driver circuit 903 are formed over a substrate 900 having an insulating surface (eg, a glass substrate, a crystallized glass substrate, a plastic substrate, or the like). These pixel parts and drive circuits are
It can be obtained according to the above embodiment.

Further, 918 is a sealing material, and 919 is DLC.
A protective film formed of a film or the like, the pixel portion and the driver circuit portion are covered with a sealant 918, and the sealant is a protective film 91.
It is covered with 9. Furthermore, a cover material 9 is formed by using an adhesive material.
It is sealed with 20. The cover material 920 may be a base material of any composition such as plastic, glass, metal, or ceramics. The shape of the cover material 920 and the shape of the support are not particularly limited, and may be flat, curved, bendable, or film-like. The cover material 920 is preferably made of the same material as the substrate 900, for example, a glass substrate, in order to withstand deformation due to heat or external force. In this embodiment,
A recess shape (depth of 3 to 10 μm) shown in FIG. 11 is processed by a sandblast method or the like. Further processed and desiccant 9
It is desirable to form a recess (depth of 50 to 200 μm) in which 21 can be installed. In addition, when manufacturing an EL module by multi-sided cutting, after bonding the substrate and the cover material,
It may be divided using a CO ₂ laser or the like so that the end faces coincide with each other.

Although not shown here, in order to prevent the background from being reflected by the reflection of the metal layer used (here, the cathode or the like), a circular polarizing plate including a retardation plate (λ / 4 plate) and a polarizing plate is used. A so-called circular polarization means may be provided on the substrate 900.

Reference numeral 908 denotes wiring for transmitting a signal input to the source side driving circuit 901 and the gate side driving circuit 903, which is a video signal or a clock signal from an FPC (flexible printed circuit) 909 serving as an external input terminal. To receive. In addition, the light emitting device of this embodiment is
Digital drive may be used, analog drive may be used, and the video signal may be a digital signal or an analog signal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to this FPC. The light emitting device in this specification includes not only the light emitting device main body but also F
It also includes the state where a PC or PWB is attached. In addition, a complicated integrated circuit (memory, CPU, controller, D
A / A converter, etc.) can be formed, but it is difficult to manufacture with a small number of masks. Therefore, the memory,
I equipped with CPU, controller, D / A converter, etc.
C chip is a COG (chip on glass) type or TAB (ta
It is preferable to mount by a pe automated bonding) method or a wire bonding method.

Next, the sectional structure will be described with reference to FIG. An insulating film 910 is provided over a substrate 900, a pixel portion 902 and a gate side driver circuit 903 are formed above the insulating film 910, and the pixel portion 902 is electrically connected to a current control TFT 911 and its drain. And a plurality of pixels including the pixel electrode 912. Actually, multiple TFTs are built in one pixel,
Here, for simplification, only the current control TFT 911 is shown. The gate side driver circuit 903 is formed using a CMOS circuit in which an n-channel TFT 913 and a p-channel TFT 914 are combined.

These TFTs (911, 913, 914)
Is included in the n-channel TFT 20 of the first embodiment.
1. It may be manufactured according to the p-channel TFT 202 of the first embodiment. In addition, here, the top gate type TFT
However, the structure is not limited to the TFT structure, and it is also possible to use, for example, a bottom gate type TFT.

In the case of a display device having an OLED, a driving method in which a circuit is designed so that a constant voltage is applied to the OLED to supply a current, or a constant current is supplied to the OLED is applied to the OLED. There are a driving method in which a circuit is designed to adjust the applied voltage, a driving method in which a circuit is designed to supply a constant current to the OLED, and the like. Connected to the OLED and supplying a current to the OLED (in the present specification, this TFT 911 is referred to as a current control TFT)
The on-current (I _on ) of the pixel determines the brightness of the pixel. Therefore, there is a problem in that the luminance varies if the ON current of each TFT is not constant. These problems can be solved by the present invention.

In this embodiment, the switching TFT
An n-channel TFT is used for the current control TFT 911.
Although a p-channel TFT is used for the above, the present invention is not limited to this structure. Switching TFT and current control TFT
May be a p-channel TFT or an n-channel TFT. However, when the anode of the OLED is used as the pixel electrode, the driving TFT is preferably a p-channel TFT, and when the cathode of the OLED is used as the pixel electrode,
The driving TFT is preferably an n-channel TFT.

Further, in the first embodiment, the second doping is performed using the mask 137 shown in FIG. 7A in order to reduce the off current value of the pixel portion, but in the present embodiment, the number of masks is increased. For reduction, the second doping is performed without forming a mask.

The pixel electrode 912 electrically connected to the electrode electrically connected to one impurity region of the current control TFT 911 functions as the anode of the OLED. As the anode, a conductive film having a high work function, typically an oxide conductive film is used. As the oxide conductive film, indium oxide, tin oxide, zinc oxide, or a compound thereof may be used. In addition, a bank 91 is provided at both ends of the pixel electrode 912.
5 is formed, and the EL layer 916 and the cathode 917 of the OLED are formed on the pixel electrode 912.

As the EL layer 916, an EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light emitting layer, a charge transporting layer, or a charge injecting layer. For example, a low molecular weight organic EL material or a high molecular weight organic EL material may be used. Further, as the EL layer, a thin film formed of a light emitting material (singlet compound) that emits light (fluorescence) by singlet excitation or a thin film formed of a light emitting material (triplet compound) that emits light (phosphorescence) by triplet excitation can be used. Further, it is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used as these organic EL materials and inorganic materials.

The cathode 917 also functions as a wiring common to all pixels, and is electrically connected to the FPC 909 via the connection wiring 908. As a material used for the cathode 917, it is preferable to use a metal having a low work function (typically, a metal element belonging to Group 1 or 2 of the periodic table) or an alloy containing these. Since the smaller the work function is, the higher the luminous efficiency is, the alloy material containing Li (lithium), which is one of the alkali metals, is preferable as the material used for the cathode. Furthermore, the pixel portion 9
02 and the elements included in the gate side drive circuit 903 are all covered with the cathode 917, the sealing material 918, and the protective film 919.

As the sealing material 918, it is preferable to use a material that is as transparent or semi-transparent to visible light as possible. Further, it is desirable that the sealing material 918 be a material that does not allow moisture and oxygen to pass therethrough as much as possible.

Further, after completely covering the OLED with the sealing material 918, at least Al as shown in FIG.
It is preferable to provide a protective film 919 consisting of a single layer or a laminate selected from an ON film, an AlN film, an Al ₂ O ₃ film, or a DLC film on the surface (exposed surface) of the seal material 918. Further, a protective film may be provided on the entire surface including the back surface of the substrate. Here, it is necessary to take care so that the protective film is not formed on the portion where the external input terminal (FPC) is provided. The protective film may not be formed using a mask, or the external input terminal portion may be covered with a tape such as a masking tape used in a CVD apparatus so that the protective film is not formed.

The OLED having the above structure is used as the sealing material 9
By enclosing the OLED with the protective film 18 and the protective film, the OLED can be completely shielded from the outside, and it is possible to prevent intrusion of substances such as moisture and oxygen that promote deterioration due to oxidation of the EL layer from the outside. Therefore, a highly reliable light emitting device can be obtained.

Further, it is possible to reduce variations in the electrical characteristics of the TFTs (TFTs that supply current to the OLED arranged in the driving circuit or the pixels) arranged so that a constant current flows through the pixel electrodes, and it is possible to reduce the luminance. Variation can be reduced.

Further, the pixel electrode may be used as a cathode, the EL layer and the anode may be laminated, and light may be emitted in a direction opposite to that shown in FIG.

In this embodiment, the TF in which the variation in the electric characteristics obtained in the embodiment 1 is reduced and the reliability is high.
Since T is used, it is possible to form an OLED with less variation in brightness than conventional elements. Further, a high-performance electric appliance can be obtained by using a light-emitting device having such an OLED as a display portion.

The present embodiment can be freely combined with the first embodiment.

[Embodiment 5] Various modules (active matrix type liquid crystal module, active matrix type EL) are formed in the driving circuit and the pixel portion formed by implementing the present invention.
Module, active matrix type EC module)
Can be used for. That is, by implementing the present invention, all electronic devices incorporating them are completed.

Examples of such electronic equipment include video cameras, digital cameras, head mounted displays (goggles type displays), car navigations, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.). ) And the like. Examples of these are shown in FIGS. 12 and 13.

FIG. 12A shows a personal computer, which has a main body 2001, an image input section 2002, and a display section 20.
03, keyboard 2004 and the like.

FIG. 12B shows a video camera, which includes a main body 2101, a display portion 2102, a voice input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
Including 6 etc.

FIG. 12C shows a mobile computer (mobile computer), which includes a main body 2201, a camera portion 2202, an image receiving portion 2203, operation switches 2204, a display portion 2205, and the like.

FIG. 12D shows a goggle type display, which includes a main body 2301, a display portion 2302 and an arm portion 230.
Including 3 etc.

FIG. 12E shows a player that uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, and has a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, operation switches 2405 and the like. This player uses a DVD (D
optical Versatile Disc), CD
It is possible to play music, watch movies, play games, and use the internet.

FIG. 12F shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown) and the like.

FIG. 13A shows a mobile phone, which is a main body 29.
01, voice output unit 2902, voice input unit 2903, display unit 2904, operation switch 2905, antenna 290
6. Image input unit (CCD, image sensor, etc.) 2907
Including etc.

[0192] FIG. 13B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006.
Including etc.

FIG. 13C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103 and the like.

By the way, the display shown in FIG. 13C is a medium-sized or large-sized display, for example, a screen size of 5 to 20 inches. Further, in order to form a display portion having such a size, it is preferable to use a substrate whose one side is 1 m and perform multi-chambering for mass production.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic device manufacturing methods in all fields. In addition, the electronic device of this embodiment can be realized by using a configuration including any combination of Embodiment Modes 1 to 3 and Embodiments 1 to 4.

[0196]

According to the present invention, it is possible to obtain a semiconductor film having a crystal structure in which a metal element that sufficiently promotes crystallization is reduced or removed, and a TFT using the semiconductor film as an active layer.
In the above, it is possible to improve the electrical characteristics and reduce the variation between individual elements. In particular, in a liquid crystal display device, display unevenness due to variations in TFT characteristics can be reduced.

In addition, in a semiconductor device having an OLED, the on-current (I) of a TFT (a TFT that supplies a current to an OLED arranged in a driving circuit or a pixel) arranged so that a constant current flows through a pixel electrode. It is possible to reduce the variation of ( _on ) and the variation of the luminance.

Further, according to the present invention, not only the metal element which promotes crystallization but also other metal elements (Fe, C
u) can also be removed or reduced.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first embodiment.

FIG. 2 is a process cross-sectional view showing a second embodiment.

FIG. 3 is a process sectional view showing a third embodiment.

FIG. 4 is a diagram showing an argon / silicon concentration ratio comparing a single layer and a laminated layer.

FIG. 5 SI showing the relationship between oxygen concentration and nickel concentration
It is a figure which shows MS analysis.

FIG. 6 is a diagram showing a process sectional view.

FIG. 7 is a diagram showing a process sectional view.

FIG. 8 is a diagram showing a process cross-sectional view.

FIG. 9 is a diagram showing a top view of a liquid crystal display device.

FIG. 10 is a sectional structural view of an active matrix liquid crystal display device.

11A and 11B are a top view and a cross-sectional view of a light-emitting device.

FIG. 12 is a diagram showing an example of an electronic device.

FIG. 13 illustrates an example of an electronic device.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/336 H01L 29/78 627G 29/786 627Z F term (reference) 2H092 JA24 KA01 KA02 KA05 KA10 5F045 AA08 AB03 AC01 AC16 AD07 AE17 AE19 AF07 BB12 BB14 CA15 HA12 HA16 5F052 AA02 AA17 AA24 BA02 BB02 BB03 BB07 CA10 DA02 DA03 DB02 DB03 DB07 EA12 EA15 EA16 FA06 DD15DD08EE02 DD01 DD021717 0202 EE14 EE15 EE23 EE28 FF04 FF30 FF35 GG01 GG02 GG13 GG33 GG34 GG43 GG45 GG47 HJ01 HJ12 HJ13 HJ23 HL02 HL03 HL04 HM15 NN02 NN03 NN04 NN24 NN27 NN72 PP01 PP02 PP03 PP04 PP06 PP10 PP13 PP29 PP34 PP35 PP40 QQ11 QQ23 QQ25 QQ28

Claims (10)

[Claims] 1. A first step of forming a first semiconductor film having an amorphous structure on an insulating surface, and a second step of adding a metal element to the first semiconductor film having an amorphous structure. A third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a fourth step of forming a barrier layer on the surface of the first semiconductor film having the crystal structure A step of forming a semiconductor film containing a rare gas element on the barrier layer by introducing a gas containing a rare gas and silane into a film formation chamber by a plasma CVD method, A process of removing a gas containing silane from the film forming chamber to generate plasma by using only a rare gas and adding a rare gas element
A fifth step of forming a second semiconductor film in which the concentration of the rare gas element on the surface is higher than that of the lower layer by performing the same or two or more times, and heat treatment is performed to form the second semiconductor film on the second semiconductor film. A sixth step of removing or reducing the metal element in the first semiconductor film having a crystalline structure by gettering the metal element, a seventh step of removing the second semiconductor film, and removing the barrier layer And an eighth step of manufacturing the semiconductor device. 2. A first step of forming a first semiconductor film having an amorphous structure on an insulating surface, and a second step of adding a metal element to the first semiconductor film having the amorphous structure. A third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a fourth step of forming a barrier layer on the surface of the first semiconductor film having the crystal structure A step of generating plasma and adding a rare gas element to the surface of the barrier layer; and introducing a gas containing a rare gas and silane into the film forming chamber by plasma CVD on the barrier layer. A process of forming a semiconductor film containing a rare gas element, and removing a gas containing silane from the film formation chamber on the surface of the semiconductor film to generate plasma only as a rare gas and add the rare gas element Processing and 1
A sixth step of forming a second semiconductor film in which the concentration of the rare gas element on the surface is higher than that of the lower layer by performing the same or two or more times, and heat treatment is performed to form the second semiconductor film on the second semiconductor film. A seventh step of removing or reducing the metal element in the first semiconductor film having a crystalline structure by gettering the metal element, an eighth step of removing the second semiconductor film, and removing the barrier layer 9. A method for manufacturing a semiconductor device, comprising: 3. The flow ratio (SiH ₄ :) of a noble gas and monosilane to be introduced into the film forming chamber when the plasma is generated in the film forming process according to claim 1 or 2.
(Noble gas) is controlled to 0.1: 99.9 to 1: 9, and
The pressure in the film forming chamber is set to 1.333 Pa to 66.
A method for manufacturing a semiconductor device, wherein the pressure is 65 Pa. 4. A first step of forming a first semiconductor film having an amorphous structure on an insulating surface, and a second step of adding a metal element to the first semiconductor film having the amorphous structure. A third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a fourth step of forming a barrier layer on the surface of the first semiconductor film having the crystal structure A step of forming an amorphous semiconductor film on the barrier layer by introducing a gas containing silane into the film formation chamber by a plasma CVD method, and a process of forming an amorphous semiconductor film on the surface of the semiconductor film from the film formation chamber. A second semiconductor film containing a rare gas element is formed by performing the treatment of removing the gas containing silane and introducing the rare gas to generate plasma to add the rare gas element once or twice alternately. And a heat treatment to form the second semiconductor. A sixth step of removing or reducing the metal element in the first semiconductor film having a crystal structure by gettering the metal element, a seventh step of removing the second semiconductor film, and the barrier layer And an eighth step of removing. 5. A first step of forming a semiconductor film having an amorphous structure on an insulating surface, a second step of adding a metal element to the semiconductor film having an amorphous structure, and crystallizing the semiconductor film. And a fourth step of forming a barrier layer on the surface of the semiconductor film having a crystalline structure, and generating a plasma to form a rare film on the surface of the barrier layer. A fifth step of adding a gas element, a sixth step of performing a heat treatment to remove or reduce the metal element in the semiconductor film having a crystalline structure by gettering the metal element in the barrier layer, and the barrier A seventh step of removing the layer, and a method for manufacturing a semiconductor device. 6. A first step of forming a first semiconductor film having an amorphous structure on an insulating surface, and a second step of adding a metal element to the first semiconductor film having the amorphous structure. A third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a fourth step of forming a barrier layer on the surface of the first semiconductor film having the crystal structure A step of forming a semiconductor film containing a rare gas element on the barrier layer by introducing a gas containing a rare gas and silane into a film formation chamber by a plasma CVD method, After removing a gas containing a rare gas and silane from the film forming chamber, a process of introducing a gas containing carbon to generate plasma to add carbon is performed once or alternately twice. The fifth step of forming the semiconductor film of and heat treatment, The sixth step of removing or reducing the metal element in the first semiconductor film having a crystalline structure by gettering the metal element into the second semiconductor film, and the seventh step of removing the second semiconductor film. A method of manufacturing a semiconductor device, comprising: a step; and an eighth step of removing the barrier layer. 7. A first step of forming a first semiconductor film having an amorphous structure on an insulating surface, and a second step of adding a metal element to the first semiconductor film having the amorphous structure. A third step of crystallizing the first semiconductor film to form a first semiconductor film having a crystal structure, and a fourth step of forming a barrier layer on the surface of the first semiconductor film having the crystal structure A step of forming a semiconductor film containing a rare gas element on the barrier layer by introducing a gas containing a rare gas and silane into a film formation chamber by a plasma CVD method, After removing a gas containing a rare gas and silane from the film forming chamber, a gas containing oxygen is introduced to generate plasma to add oxygen, and the treatment is alternately performed once or twice or more. The fifth step of forming the semiconductor film of and heat treatment, The sixth step of removing or reducing the metal element in the first semiconductor film having a crystalline structure by gettering the metal element into the second semiconductor film, and the seventh step of removing the second semiconductor film. A method of manufacturing a semiconductor device, comprising: a step; and an eighth step of removing the barrier layer. 8. The method for manufacturing a semiconductor device according to claim 1, wherein the barrier layer is a silicon oxide film or a silicon oxynitride film having a film thickness of 1 nm to 10 nm. 9. The metal element according to claim 1, wherein the metal element is Fe, Ni, Co, Ru, Rh, Pd, or O.
A method for manufacturing a semiconductor device, which is one or more selected from s, Ir, Pt, Cu, and Au. 10. The method according to any one of claims 1 to 9,
The method for manufacturing a semiconductor device, wherein the rare gas element is one or more selected from He, Ne, Ar, Kr, and Xe.