JP3969902B2 - Manufacturing method of interposer for chip size package - Google Patents

Description

【００５６】
表１から明らかなように、アウター側ビアホール１０およびインナー側ビアホール１１の両方をレーザ加工によって形成した比較例１は、実施例１に比べて約８倍の作業時間がかかっており、また、片方のインナー側ビアホール４１をレーザ加工によって形成した比較例２は、実施例１に比べて約４倍の作業時間がかかっていることがわかる。
【００５７】
【発明の効果】
以上述べたように、本発明のチップサイズパッケージ用インターポーザーの製造方法によれば、アウター側絶縁体層およびインナー側絶縁体層の両方を感光性ポリイミドによって形成するので、電極などを形成するためのアウター側ビアホールおよびインナー側ビアホールを、フォトレジストによって一度にファインピッチで多数形成することができる。そのため、短時間で精度のよいアウター側ビアホールおよびインナー側ビアホールを形成することができ、作業性よく生産することができる。したがって、本発明のチップサイズパッケージ用インターポーザーの製造方法により得られるチップサイズパッケージ用インターポーザーは、精度よくアウター側ビアホールおよびインナー側ビアホールが形成されて、効率的に製造されるので、安価に提供され、有用に使用される。
【図面の簡単な説明】
【図１】 本発明のチップサイズパッケージ用インターポーザーの製造方法により得られるチップサイズパッケージ用インターポーザーの一実施形態を示す断面図である。
【図２】 図１に示すインターポーザーを製造するための、アウター側絶縁体層を形成するための工程図であって、
（ａ）は、支持板にアウター側前駆体層を形成する工程を示す断面図、
（ｂ）は、アウター側前駆体層をフォトマスクを介して露光させる工程を示す断面図、
（ｃ）は、現像処理によってアウター側前駆体層にアウター側ビアホールを形成する工程を示す断面図、
（ｄ）は、アウター側前駆体層を硬化させることによって感光性ポリイミドからなるアウター側絶縁体層を形成する工程を示す断面図である。
【図３】 図２に続いて図１に示すインターポーザーを製造するための、導電体層をセミアディティブ法により形成するための工程図であって、
（ｅ）は、アウター側絶縁体層上に下地を形成する工程を示す断面図、
（ｆ）は、下地上にめっきレジストを形成する工程を示す断面図、
（ｇ）は、下地上に導電体層を形成する工程を示す断面図、
（ｈ）は、めっきレジストを除去する工程を示す断面図、
（ｉ）は、めっきレジストが形成されていた部分の下地を除去する工程を示す断面図である。
【図４】 図３に続いて図１に示すインターポーザーを製造するための、インナー側絶縁体層およびインナー側電極を形成するための工程図であって、
（ｊ）は、導電体層上にインナー側前駆体層を形成する工程を示す断面図、
（ｋ）は、インナー側前駆体層をフォトマスクを介して露光させる工程を示す断面図、
（ｌ）は、現像処理によってインナー側前駆体層にインナー側ビアホールを形成する工程を示す断面図、
（ｍ）は、インナー側前駆体層を硬化させることによって感光性ポリイミドからなるインナー側絶縁体層を形成する工程を示す断面図、
（ｎ）は、インナー側ビアホールにインナー側電極を形成する工程を示す断面図である。
【図５】 図４に続いて図１に示すインターポーザーを製造するための、支持板を除去するため、およびアウター側電極を形成するための工程図であって、
（ｏ）は、支持板を除去する工程を示す断面図、
（ｏ’）は、アウター側絶縁体層に露出する下地を除去する工程を示す断面図、
（ｐ）は、アウター側電極を形成する工程を示す断面図である。
【図６】 従来のチップサイズパッケージ用インターポーザーを示す断面図である。
【図７】 図６に示すインターポーザーを製造するための工程図であって、
（ａ）は、導電体層にインナー側絶縁体層を形成する工程を示す断面図、
（ｂ）は、インナー側絶縁体層に接着剤層を形成する工程を示す断面図、
（ｃ）は、導電体層を所定の回路パターンに形成する工程を示す断面図、
（ｄ）は、導電体層における所定の回路パターンとされた面にアウター側絶縁体層を形成する工程を示す断面図、
（ｅ）は、アウター側絶縁体層にアウター側ビアホールをレーザ加工によって形成する工程を示す断面図、
（ｆ）は、インナー側絶縁体層にインナー側ビアホールをレーザ加工によって形成する工程を示す断面図である。
【図８】 比較例２のインターポーザーを製造するための工程図であって、
（ａ）は、導電体層にインナー側絶縁体層を形成する工程を示す断面図、
（ｂ）は、インナー側絶縁体層に接着剤層を形成する工程を示す断面図、
（ｃ）は、導電体層を所定の回路パターンに形成する工程を示す断面図、
（ｄ）は、導電体層における所定の回路パターンとされた面にアウター側前駆体層を形成する工程を示す断面図である。
【図９】 図８に続いて比較例２のインターポーザーを製造するための工程図であって、
（ｅ）は、アウター側前駆体層をフォトマスクを介して露光させる工程を示す断面図、
（ｆ）は、現像処理によってアウター側前駆体層にアウター側ビアホールを形成する工程を示す断面図、
（ｇ）は、アウター側前駆体層を硬化させることによって感光性ポリイミドからなるアウター側絶縁体層を形成する工程を示す断面図、
（ｈ）は、インナー側絶縁体層にインナー側ビアホールをレーザ加工によって形成する工程を示す断面図である。[0001]
BACKGROUND OF THE INVENTION
  The present inventionManufacturing method of interposer for chip size packageSpecifically, an interposer for chip size package for electrically connecting a semiconductor chip and an external circuit board when mounting the semiconductor chipーIt relates to a manufacturing method.
[0002]
[Prior art]
In recent years, as electronic components have become lighter and shorter, packages for mounting semiconductor chips are also becoming thinner and smaller, and high-density semiconductor chips can be mounted almost as they are. Development of chip size packages (also called chip scale packages) is underway.
[0003]
In the chip size package, for example, as shown in FIG. 6, an interposer 3 is interposed between the semiconductor chip 1 and the external circuit board 2, and the conductive path 4 formed in the interposer 3 is interposed. The electrodes of the semiconductor chip 1 and the electrodes of the external circuit board 2 are electrically connected. The semiconductor chip 1 is sealed with a sealing material 5.
[0004]
Such an interposer 3 is conventionally manufactured by the following method. That is, as shown in FIG. 7A, first, after inner layer insulator layer 7 such as polyimide is laminated on one surface of conductor layer 6 such as copper foil, as shown in FIG. 7B. Then, the adhesive layer 8 is laminated on the inner side insulator layer 7. Next, as shown in FIG. 7C, the conductor layer 6 is formed into a predetermined circuit pattern by a known method, and then, as shown in FIG. 7D, the predetermined circuit pattern in the conductor layer 6 is formed. The outer insulating layer 9 made of polyimide or the like is laminated on the surface thus formed. And as shown in FIG.7 (e), while forming the outer side via hole 10 by laser processing in the outer side insulator layer 9, as shown in FIG.7 (f), in the inner side insulator layer 7, The inner via hole 11 is formed by laser processing.
[0005]
Then, as shown in FIG. 6, after forming the outer side electrode 12 and the inner side electrode 13 in the outer side via hole 10 and the inner side via hole 11, respectively, the inner side electrode 13 is made to correspond to the electrode of the semiconductor chip 1, While adhering the adhesive layer 8 to the semiconductor chip 1 and connecting the outer side electrode 12 to the electrode of the external circuit board 2, the electrode of the semiconductor chip 1 is connected to the interposer 3 as described above. It is connected to the electrode of the external circuit board 2 through the conductive passage 4, that is, the inner side electrode 13, the conductor layer 6 and the outer side electrode 12.
[0006]
[Problems to be solved by the invention]
However, in the method as described above, the outer side via hole 10 and the inner side via hole 11 need to be formed at a fine pitch. Therefore, the holes are formed one by one by laser processing. Therefore, there is a problem that it cannot be efficiently produced.
[0007]
  The present invention has been made in view of such problems, and the object of the present invention is to be able to efficiently produce holes while accurately forming holes in a fine pitch in an insulator layer.Of interposer for chip size packageMadeHow to makeTo provide a law.
[0008]
[Means for Solving the Problems]
  To achieve the above object, the present inventionOf interposer for chip sizeIsA step of forming a precursor of photosensitive polyimide in a layer form on a support plate made of stainless steel having a thickness of 10 to 100 μm and forming an outer precursor layer, and exposing the outer precursor layer through a photomask The step of forming the outer via hole in the outer precursor layer by heating the exposed portion to a predetermined temperature and then developing, and heating the outer precursor layer in which the outer via hole is formed And a step of forming an outer insulator layer, a step of forming a conductor layer on which the predetermined circuit pattern is formed on the outer insulator layer, and a precursor of photosensitive polyimide. Forming a layer on the conductor layer to form an inner side precursor layer; and exposing the inner side precursor layer through a photomask; By developing after heating the light portion to a predetermined temperature, by forming the inner via hole in the inner precursor layer, and by heating the inner precursor layer in which the inner via hole is formed It includes a step of curing to form an inner insulator layer and a step of removing the support plate after the step of forming the inner insulator layer.It is characterized by.
[0009]
  In addition, the present inventionOf interposer for chip sizeIsA step of forming a precursor of photosensitive polyimide in a layer form on a support plate made of stainless steel having a thickness of 10 to 100 μm to form an inner side precursor layer, and exposing the outer side precursor layer through a photomask The step of forming the inner side via hole in the inner side precursor layer by developing the exposed portion after heating to a predetermined temperature and heating the inner side precursor layer in which the inner side via hole is formed And a step of forming an inner insulator layer, a step of forming a conductor layer on which the predetermined circuit pattern is formed on the inner insulator layer, and a precursor of photosensitive polyimide. Forming a layer on the conductor layer and forming the outer precursor layer; and exposing the outer precursor layer through a photomask; By heating the light portion to a predetermined temperature and then developing it, by forming the outer via hole in the outer precursor layer and heating the outer precursor layer in which the outer via hole is formed It is characterized by including a step of curing to form an outer insulator layer and a step of removing the support plate after the step of forming the outer insulator layer.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
  Of the present inventionChip size package interposer obtained by manufacturing method of chip size package interposerIs a conductor layer andOuter side insulator layer and inner side insulator layerAndBoth outer-side insulator layer and inner-side insulator layerIs formed of photosensitive polyimide.More specifically, an interposer for chip size package as shown in FIG.IsIllustrated.
[0012]
  That is, in FIG. 1, this interposer 20 is provided on both sides of a conductor layer 21 on which a predetermined circuit pattern is formed.AThe outer insulator layer 22 and,IAn inner insulator layer 23 is laminated, and an outer via hole 24 and an inner via hole 25 are formed in the outer insulator layer 22 and the inner insulator layer 23, respectively.
[0013]
A bump-shaped outer side electrode 26 is formed in the outer-side via hole 24, and the inner-side via hole 25 is flat (bump-shaped when the electrode is formed, but becomes flat when connected to the semiconductor chip 18. ), And the interposer 20 is interposed between the semiconductor chip 18 and the external circuit board 16, and the inner side electrode is formed on the electrode (not shown) of the semiconductor chip 18. 27, and the outer side electrode 26 is connected to the electrode 17 of the external circuit board 16, so that the semiconductor chip 18 can be mounted almost in its size. The semiconductor chip 18 is sealed with a sealing material 19.
[0014]
  Next, taking a method of manufacturing such a chip size package interposer 20 as an example,Of interposer for chip size packageMadeHow to makeExplain the law.
[0015]
In this method, first, the outer side insulator layer 22 is formed of photosensitive polyimide. FIG. 2 shows a process of forming the outer insulator layer 22 from photosensitive polyimide. In order to form the outer insulating layer 22, first, as shown in FIG. 2A, a photosensitive polyamic acid (polyamic acid) resin, which is a precursor of photosensitive polyimide, is layered on a support plate 32. Then, the outer precursor layer 22p is formed.
[0016]
The support plate 32 supports the outer insulator layer 22 and ensures the rigidity of the conductor layer 21 and the inner insulator layer 23 laminated thereon, thereby improving the workability when forming them. While improving, by preventing the thermal contraction at the time of hardening of the outer side insulator layer 22 and the inner side insulator layer 23, the arrangement | positioning of the outer side via hole 24 and the inner side via hole 25 with a sufficient precision is ensured.
[0017]
  Such a support plate 32 requires a certain degree of rigidity.,WhenIn particular, in terms of stiffness (waist strength), low linear expansion coefficient, ease of removal, and, as will be described later, can be a cathode for forming the conductor layer 21 by electrolytic plating., SuTenresForI can. The thickness of the support plate 32Is 10-100μmis there.
[0018]
The photosensitive polyamic acid resin can be obtained by blending a polyamic acid resin and a photosensitizer, and the polyamic acid resin can be obtained by reacting an acid dianhydride and a diamine.
[0019]
Examples of the acid dianhydride include 3,3 ′, 4,4′-oxydiphthalic dianhydride (ODPA), 2,2-bis (3,4-dicarboxyphenyl) hexafluoropropane dianhydride ( 6FDA), dianhydride of ester compound (TMEG) of ethylene glycol and trimellitic acid, 3,3 ′, 4,4′-benzophenonetetracarboxylic dianhydride (BTDA), 3,3 ′, 4,4 '-Biphenyltetracarboxylic dianhydride (BPDA), 2,2', 3,3'-biphenyltetracarboxylic dianhydride, 2,2 ', 3,3'-benzophenonetetracarboxylic dianhydride, 2 , 2-bis (2,3-dicarboxyphenyl) hexafluoropropane dianhydride, bis (2,3-dicarboxyphenyl) methane dianhydride, bis (3,4-dicarboxyphenyl) methan Emissions dianhydride, bis (2,3-carboxyphenyl) sulfone dianhydride, bis (3,4-carboxyphenyl) sulfone dianhydride include pyromellitic dianhydride. They may be used alone or in combination of two or more.
[0020]
Examples of the diamine include 4,4′-diaminodiphenyl ether (DDE), 3,4′-diaminodiphenyl ether (34DDE), 3,3′-diaminodiphenyl ether, bisaminopropyltetramethyldisiloxane (APDS), 1,3. -Bis (3-aminophenoxy) benzene (APB), 1,3-bis (4-aminophenoxy) benzene, m-phenylenediamine (MPD), p-phenylenediamine (PPD), 4,4'-diaminodiphenylpropane 3,3′-diaminodiphenylpropane, 4,4′-diaminodiphenylmethane, 3,3′-diaminodiphenylmethane, 4,4′-diaminodiphenyl sulfide, 3,3′-diaminodiphenyl sulfide, 4,4′-diamino Diphenyl sulfone, 3,3′-diamino Diphenylsulfone, 1,4-bis (4-aminophenoxy) benzene, 2,2′-bis [4- (4-aminophenoxy) phenyl] propane, hexamethylenediamine, 1,8-diaminooctane, 1,12 -Diaminododecane, 4,4'-diaminobenzophenone and the like. They may be used alone or in combination of two or more.
[0021]
The polyamic acid resin contains an appropriate organic solvent, such as N-methyl-2-pyrrolidone, N, N-dimethyl, in such a ratio that the acid dianhydride and diamine are substantially equimolar. What is necessary is just to make it obtain as a solution of a polyamic acid resin by making it react for a predetermined time under normal temperature normal pressure in organic solvents, such as acetamide and N, N- dimethylformamide.
[0022]
Moreover, as a photosensitizer mix | blended with polyamic acid resin, it is preferable to use a 1, 4- dihydropyridine derivative, for example, and especially 1-ethyl-3,5-dimethoxycarbonyl-4- (2-nitrophenyl)-. 1,4-dihydropyridine, 1,2,6-trimethyl-3,5-dimethoxycarbonyl-4- (2-nitrophenyl) -1,4-dihydropyridine, 2,6-dimethyl-3,5-diacetyl-4- Examples include (2-nitrophenyl) -1,4-dihydropyridine, 1-carboxyethyl-3,5-dimethoxycarbonyl-4- (2-nitrophenyl) -1,4-dihydropyridine, and the like. They may be used alone or in combination of two or more. Of these 1,4-dihydropyridine derivatives, 1-ethyl-3,5-dimethoxycarbonyl-4- (2-nitrophenyl) -1,4-dihydropyridine, 1,2,6-trimethyl-3, 5-dimethoxycarbonyl-4- (2-nitrophenyl) -1,4-dihydropyridine.
[0023]
Such a photosensitizer is usually blended in the range of 0.1 to 1.0 mol with respect to the total of acid dianhydride and diamine, that is, 1 mol of polyamic acid. If it is more than 1.0 mol, the physical properties of the outer insulator layer 22 after curing may be reduced, and if it is less than 0.1 mol, the formability of the outer via hole 24 may be reduced. Furthermore, you may mix | blend an epoxy resin, bisallyl nadic imide, maleimide, etc. with the photosensitive polyamic acid resin obtained in this way as needed. The photosensitive polyamic acid resin for forming such an outer precursor layer 22p has a glass transition temperature (Tg) after imidation of 250 ° C. or higher, and preferably 300 ° C. or higher.
[0024]
And in order to form the photosensitive polyamic acid resin obtained in this way on the support plate 32 in layers, and to form the outer side precursor layer 22p, for example, on the support plate 32, photosensitive polyamic acid is formed. After coating the resin with a constant thickness by a known method, the organic solvent may be dried at about 80 to 130 ° C., for example. Alternatively, a dry film of a photosensitive polyamic acid resin obtained by drying an organic solvent with a certain thickness may be formed in advance, and this dry film may be bonded to the support plate 32. Although the thickness of the outer side precursor layer 22p is not specifically limited, For example, about 5-30 micrometers is suitable.
[0025]
Next, the outer via hole 24 is formed in the outer precursor layer 22p thus formed. The outer via hole 24 may be formed by exposing through a photomask, heating the exposed portion to a predetermined temperature, and developing.
[0026]
The irradiation beam irradiated through the photomask may be any irradiation beam as long as it can sensitize the photosensitive polyamic acid resin, such as ultraviolet rays, electron beams, or microwaves. The exposed portion of the body layer 22p is solubilized (positive type) in the next development processing by heating at, for example, 130 ° C. or more and less than 150 ° C., for example, by heating at 150 ° C. or more and 180 ° C. or less. In the next development process, it is insolubilized (negative type).
[0027]
The development treatment may be performed by a known method such as an immersion method or a spray method using a known developer such as an alkali developer. Examples of the alkaline developer include aqueous solutions of alkaline inorganic compounds such as sodium hydroxide and potassium hydroxide, such as aqueous solutions of alkaline organic compounds such as propylamine, butylamine, monoethanolamine, tetramethylammonium hydroxide, and choline. It is used, and organic solvents such as alcohols and various surfactants are blended as necessary.
[0028]
The outer via hole 24 may be formed in a positive or negative pattern by such a series of exposure, heating, and development processes. Of these, it is preferable to form the outer via hole 24 with a negative pattern. FIG. 2B and FIG. 2C show an example in which the outer via hole 24 is formed with a negative pattern. That is, first, as shown in FIG. 2B, the photomask 28 is disposed at a position corresponding to the electrode 17 of the external circuit board 16 in the outer-side precursor layer 22p and a position facing the photomask 28. The outer precursor layer 22p is irradiated with an irradiation beam through the mask 28. Next, as described above, after heating at a predetermined temperature of a negative type, and performing a predetermined development process, as shown in FIG. 2C, the unexposed portion of the outer precursor layer 22p, that is, The outer side via hole 24 is formed by dissolving the portion masked by the photomask 28 in the developer.
[0029]
And as shown in FIG.2 (d), the outer side precursor layer 22p in which the outer side via-hole 24 was formed is hardened (imidized) by finally heating to 250 degreeC or more, for example, Thus, the outer insulating layer 22 made of photosensitive polyimide is formed.
[0030]
Thus, if the outer side via hole 24 is formed in the outer side insulator layer 22, it is not necessary to form the outer side via hole 24 later by laser processing, and the outer side via hole 24 is formed as in laser processing. Since a large number of outer via holes 24 can be formed at a fine pitch at a time without forming them one by one, the working time can be greatly reduced, and the cost can be reduced by improving workability and efficient production. Can be achieved.
[0031]
Next, the conductor layer 21 in which a predetermined circuit pattern is formed is formed on the outer insulating layer 22 formed in this way.
[0032]
The conductor layer 21 is not particularly limited as long as it has conductivity. For example, gold, silver, copper, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium. Furthermore, for example, known metals used as conductors for circuit boards, such as alloys of various metals as described above, such as solder, nickel-tin, gold-cobalt, and the like can be used. The thickness of the conductor layer 21 is not particularly limited, but for example, about 5 to 20 μm is appropriate.
[0033]
In order to form the conductor layer 21 on which the predetermined circuit pattern is formed on the outer insulator layer 22, any known method such as a subtractive method, an additive method, or a semi-additive method may be used. . In the subtractive method, first, a conductor layer 21 is laminated on the entire surface of the outer insulating layer 22, and then an etching resist corresponding to a predetermined circuit pattern is formed on the conductor layer 21. The conductor layer 21 is etched using the etching resist as a resist, and then the etching resist is removed. In addition, in the additive method, first, a plating resist is formed on a portion other than a portion where a predetermined circuit pattern is formed on the outer-side insulator layer 22, and then an outer-side insulator on which no plating resist is formed. The conductor layer 21 is formed on the layer 22 by plating, and then the plating resist is removed. Further, in the semi-additive method, first, a conductive thin film as a base is formed on the outer insulating layer 22, and then a portion other than a portion where a predetermined circuit pattern is formed is plated on the base. After the resist is formed, the conductor layer 21 is formed on the base on which no plating resist is formed, and thereafter, the plating resist and the base on which the plating resist is laminated are removed.
[0034]
Of these, the semi-additive method is preferably used. Next, a method for forming the conductor layer 21 by the semi-additive method will be described in more detail. FIG. 3 shows a process of forming the conductor layer 21 by the semi-additive method. First, as shown in FIG. 3 (e), a thin film of a conductor serving as a base 29 is formed on the entire surface of the outer insulating layer 22 and on the wall surface and bottom surface of the outer via hole 24. For the formation of the base 29, for example, a known vacuum deposition method such as a sputtering deposition method, a resistance heating deposition method, an electron beam heating deposition method, or an electroless plating method is used. Preferably, a sputtering deposition method is used. It is done. The conductor used as the base 29 is not particularly limited as long as it has conductivity and can improve the adhesion between the outer insulator layer 22 and the conductor layer 21. When the conductor layer 21 is copper, chromium or copper is preferably used. In addition, the thickness of the base 29 is not particularly limited, but for example, about 500 to 5000 mm is appropriate, and the base 29 is not limited to one layer and may be formed as a multilayer structure such as two layers. For example, when forming as a two-layer structure of chromium / copper, it is preferable that the chromium layer has a thickness of 300 to 700 mm and the copper layer has a thickness of 1000 to 3000 mm.
[0035]
Next, as shown in FIG. 3F, a plating resist 30 is formed on the base 29 in a portion other than a portion where a predetermined circuit pattern is formed. The plating resist 30 may be formed as a predetermined resist pattern by a known method using, for example, a dry film resist. Next, as shown in FIG. 3G, the conductor layer 21 is formed by plating on the outer insulating layer 22 where the plating resist 30 is not formed. The plating method may be either electroless plating or electrolytic plating, but is preferably formed by electrolytic plating. In the case of forming the conductor layer 21 by electrolytic plating, for example, from the first step shown in FIG. 2A, a support plate 32 made of a metal that can be a cathode for electrolytic plating is used, and this support plate is used. 32 is used as a cathode, metal is deposited in the outer via hole 24, the conductive passage 31 is formed first, and then electrolytic plating is continued to form a resist 30 on the outer insulator layer 22. It is preferable to form the conductor layer 21 with a predetermined circuit pattern by depositing a metal on a portion that is not formed. By such electrolytic plating, the conductive passage 31 in the outer via hole 24 and the conductor layer 21 can be formed in one step. Of the metals described above, for example, gold, copper, nickel, solder, and the like are preferably used as the metal used for electrolytic plating. In particular, copper is preferably used from the viewpoint of ease of formation of a circuit pattern and electrical characteristics. The metal that forms the conductive path 31 may be different from the metal that forms the conductive layer 21 that follows.
[0036]
Then, as shown in FIG. 3 (h), after removing the plating resist 30 by a known etching method such as chemical etching (wet etching), the plating resist 30 is formed as shown in FIG. 3 (i). The formed base 29 is similarly removed by a known etching method such as chemical etching (wet etching).
[0037]
In the step of forming the conductor layer 21 in which a predetermined circuit pattern is formed on the outer insulating layer 22, the conductive path 31 and the conductor in the outer via hole 24 are plated by the plating method as described above. The layer 21 can be formed in one step, but it is not always necessary to form the conductive path 31 together with the formation of the conductor layer 21. For example, the conductive path 31 is first plated using the support plate 32 as a cathode. Then, the conductor layer 21 may be formed on the conductive path 31 by a semi-additive method in which the base 29 is formed.
[0038]
Next, an inner insulator layer 23 is formed on the conductor layer 21. FIG. 4 shows a process of forming the inner side insulator layer 23 from photosensitive polyimide. (Note that FIG. 4 shows a base 29 when the conductor layer 21 is formed by a semi-additive method, but this base 29 is omitted when formed by a subtractive method or an additive method. 4) First, as shown in FIG. 4 (j), a photosensitive polyamic acid resin, which is a precursor of photosensitive polyimide, is formed in layers on the conductor layer 21 to form an inner side precursor layer 23p. To do. The photosensitive polyamic acid resin that forms the inner side precursor layer 23p may be the same component as the photosensitive polyamic acid resin that forms the outer side precursor layer 22p, but the inner side insulator layer 23 is made of an adhesive. It is preferable to have adhesiveness so that the semiconductor chip 18 can be directly bonded (heat fusion) without using any of the above. Therefore, for example, as acid dianhydride, 3, 3 ′, 4, 4 ′ − Dianhydride of oxydiphthalic dianhydride (ODPA), 2,2-bis (3,4-dicarboxyphenyl) hexafluoropropane dianhydride (6FDA), ester compound of ethylene glycol and trimellitic acid (TMEG) 3,3 ′, 4,4′-benzophenonetetracarboxylic dianhydride (BTDA) is preferred, and in particular, 3,3 ′, 4,4′-oxydi It is preferable to use tartric dianhydride (ODPA), and as the diamine, 1,3-bis (3-aminophenoxy) benzene (APB), bisaminopropyltetramethyldisiloxane (APDS), 4,4 ′ It is preferable to use diaminodiphenyl ether (DDE), and it is particularly preferable to use 1,3-bis (3-aminophenoxy) benzene (APB) or bisaminopropyltetramethyldisiloxane (APDS). Moreover, the photosensitive polyamic acid resin for forming such an inner side precursor layer 23 has a melt viscosity (250 ° C.) after imidation of 1000 to 1000000 Pa · S, and further 5000 to 500000 Pa · S. And the glass transition temperature (Tg) is preferably 50 to 250 ° C, more preferably 100 to 200 ° C.
[0039]
And in order to form such a photosensitive polyamic acid resin in a layer form on the conductor layer 21 to form the inner side precursor layer 23p, as in the case of forming the outer side precursor layer 22p, For example, after the photosensitive polyamic acid resin is applied to the conductor layer 21 with a constant thickness by a known method, for example, the organic solvent is dried at about 100 to 150 ° C., or A dry film of a photosensitive polyamic acid resin obtained by drying an organic solvent with a certain thickness may be formed in advance, and this dry film may be bonded to the conductor layer 21. Although the thickness of the inner side precursor layer 23p is not specifically limited, For example, about 5-30 micrometers is suitable.
[0040]
Next, an inner via hole 25 is formed in the inner precursor layer 23p formed in this way. Similarly to the formation of the outer via hole 24, the inner via hole 25 may be exposed through a photomask, heated to a predetermined temperature, and then developed. The inner via hole 25 may be formed with either a positive pattern or a negative pattern, but preferably with a negative pattern. FIG. 4K and FIG. 4L show an example in which the inner via hole 25 is formed with a negative pattern. That is, first, as shown in FIG. 4 (k), the photomask 33 is disposed at a position opposite to the position corresponding to the electrode of the semiconductor chip 18 in the inner-side precursor layer 23p. The inner side precursor layer 23p is irradiated with an irradiation beam. Next, as described above, after heating at a predetermined temperature of a negative type and performing a predetermined development process, as shown in FIG. 4 (l), the unexposed portion of the inner side precursor layer 23p, that is, The portion masked by the photomask 33 is dissolved in the developer, whereby the inner side via hole 25 is formed.
[0041]
Then, as shown in FIG. 4 (m), the inner side precursor layer 23p in which the inner side via hole 25 is formed is finally cured (imidized) by, for example, being heated to 250 ° C. or higher. Thus, the inner insulator layer 23 made of photosensitive polyimide is formed.
[0042]
Thus, if the inner side via hole 25 is formed in the inner side insulator layer 23, it is not necessary to form the inner side via hole 25 later by laser processing, and moreover, the inner side via hole 25 is formed as in laser processing. Since a large number of inner via holes 25 can be formed at a fine pitch at a time without forming each one, the working time can be greatly reduced, and the cost can be reduced by improving workability and efficient production. Can be achieved.
[0043]
Then, as shown in FIG. 4 (n), a bump-like inner side electrode 27 is formed in the inner side via hole 25 by a known method such as plating with gold, nickel, copper, solder, etc. As shown, the interposer 20 can be obtained by removing the support plate 32 and forming the outer electrode 26. FIG. 5 shows a step of removing the support plate 32 and a step of forming the outer side electrode 26. (Note that FIG. 5 shows a base 29 when the conductor layer 21 is formed by a semi-additive method, but this base 29 is omitted when formed by a subtractive method or an additive method. In addition, the step of FIG. 5 (o ′) is also omitted.) First, as shown in FIG. 5 (o), the support plate 32 is removed from the outer insulating layer 22. The support plate 32 may be removed by a known etching method such as chemical etching (wet etching). Further, when the conductor layer 21 is formed by a semi-additive method, the base 29 is exposed to the outer insulating layer 22 by removing the support plate 32 as shown in FIG. The underlayer 29 may also be removed by a known etching method such as chemical etching (wet etching) as shown in FIG. Next, as shown in FIG. 5 (p), a bump-shaped outer electrode 26 in contact with the conductive passage 31 of the outer insulator layer 22 is formed. The outer side electrode 26 may be formed by a known method such as connecting a solder ball or plating gold, copper, nickel, solder, or the like. What is necessary is just to select suitably.
[0044]
As shown in FIG. 1, the interposer 20 obtained in this manner is interposed between the electrode of the semiconductor chip 18 and the electrode 17 of the external circuit board 16 to electrically connect them. Used to do. (In FIG. 1, the base 29 when the conductor layer 21 is formed by the semi-additive method is omitted).
In the interposer 20 thus obtained, the outer side insulator layer 22 and the inner side insulator layer 23 sandwiching the conductor layer 21 are all formed of photosensitive polyimide. The side via hole 25 can be formed of a photoresist. Therefore, it is possible to accurately form a large number of outer via holes 24 and inner via holes 25 at a fine pitch at a time without forming the outer via holes 24 and the inner via holes 25 one by one as in laser processing. it can. Therefore, such an interposer 20 can be efficiently produced and provided at low cost even though the outer via hole 24 and the inner via hole 25 are accurately arranged at a fine pitch. Therefore, as described above, it is usefully used as an interposer for chip size packages.
[0045]
In the above description, the outer insulating layer 22 is first formed on the support plate 32, and then the inner insulating layer 23 is formed after the conductor layer 21 is formed. That is, first, the inner insulating layer 23 may be formed on the support plate 32, and then the outer insulating layer 22 may be formed after the conductor layer 21 is formed. In the case where the inner insulating layer 23 is formed first, if the conductive layer 21 is formed by the additive method or the semi-additive method, the conductive passage 31 can be formed at the same time. Therefore, the conductive passage 31 is formed into the flat inner side electrode 27. It can also be used as Which is formed first may be appropriately selected depending on the purpose and application. For example, when the inner side insulator layer 23 is made adhesive as described above, the inner side precursor layer 23p is cured. Since the temperature is preferably lower than the curing temperature of the outer-side precursor layer 22p, it is preferable to form the outer-side precursor layer 22p to be cured at a higher temperature first.
[0046]
  In the above description, the interposer 20 is formed using the support plate 32..Since the outer side precursor layer 22p and the inner side precursor layer 23p are hardened, especially during the first curing (that is, when the outer side precursor layer 22p is cured in the above description), heat shrinkage is likely to occur. As a result, there may be a case where an accurate arrangement of the inner via hole 24 during exposure cannot be ensured.FromUse the support plate 32The
[0048]
【Example】
Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples. However, the present invention is not limited to the examples and comparative examples.
[0049]
Example 1
First, using a SUS plate having a thickness of 25 μm as the support plate 32, a photosensitive polyamic acid resin having the following composition was applied on the support plate 32 as shown in FIG. The outer side precursor layer 22p was formed by making it dry for minutes.
(Outer side polyamic acid resin composition)
Acid dianhydride component: 3,3 ′, 4,4′-oxydiphthalic dianhydride (0.5 mol), 2,2-bis (3,4-dicarboxyphenyl) hexafluoropropane dianhydride ( 0.5 mole)
Diamine component: 4,4'-diaminodiphenyl ether (0.5 mol), P-phenylenediamine (0.5 mol)
Photosensitizer: 1-ethyl-3,5-dimethoxycarbonyl-4- (2-nitrophenyl) -1,4-dihydropyridine (0.26 mol)
Organic solvent: N-methyl-2-pyrrolidone
Next, as shown in FIG. 2 (b), an exposure irradiation line (g line) is irradiated to the outer precursor layer 22p through the photomask 28, heated at 170 ° C. for 3 minutes, and then ethanol is added. Development processing was performed using the alkaline developer contained therein, thereby forming an outer via hole 24 having a hole diameter of 400 μm at a position corresponding to the electrode 17 of the external circuit board 16 as shown in FIG. . Thereafter, this is cured (imidized) by heating at 400 ° C. for 30 minutes, thereby forming an outer-side insulator layer 22 made of photosensitive polyimide having a thickness of 10 μm, as shown in FIG. did.
[0050]
Next, as shown in FIG. 3E, a chromium film having a thickness of about 300 mm is formed on the entire surface of the outer insulating layer 22 and the wall surface and bottom surface of the outer via hole 24 by a sputter deposition method. After a copper film having a thickness of about 1000 mm is formed on the chromium film as the base 29, a predetermined circuit pattern can be obtained with a dry film resist having a thickness of 15 μm as shown in FIG. A resist pattern of the plating resist 30 was formed. Then, as shown in FIG. 3G, the conductive plate 31 is formed by depositing copper in the outer via hole 24 by electrolytic plating using the support plate 32 as a cathode, and on the outer insulator layer 22. Also, copper was deposited to form a conductor layer 21 having a predetermined circuit pattern. The thickness of the conductor layer 21 was 15 μm, similar to the thickness of the plating resist 30. Thereafter, as shown in FIG. 3 (h), the plating resist 30 is removed with an alkaline etching solution. Further, as shown in FIG. 3 (i), the base 29 on which the plating resist 30 was formed, that is, copper The film and the chromium film were removed with an acidic etching solution and an alkaline etching solution, respectively.
[0051]
Next, as shown in FIG. 4 (j), a photosensitive polyamic acid resin having the following composition is applied onto the conductor layer 21 and dried at 100 ° C. for 20 minutes, whereby the inner side precursor layer 23p. Formed.
(Inner side polyamic acid resin composition)
Acid dianhydride component: 3,3 ', 4,4'-oxydiphthalic dianhydride (1.0 mol)
Diamine component: 1,3-bis (3-aminophenoxy) benzene (0.8 mol), bisaminopropyltetramethyldisiloxane (0.2 mol)
Photosensitizer: 1-ethyl-3,5-dimethoxycarbonyl-4- (2-nitrophenyl) -1,4-dihydropyridine (0.26 mol)
Organic solvent: N-methyl-2-pyrrolidone
Next, as shown in FIG. 4 (k), an irradiation beam (g-line) for exposure is irradiated to the inner precursor layer 23p through the photomask 33, heated at 170 ° C. for 3 minutes, and then ethanol is added. Development processing was performed using the alkaline developer contained therein, thereby forming an inner via hole 25 having a hole diameter of 50 μm at a position corresponding to the electrode of the semiconductor chip 18 as shown in FIG. Thereafter, this is cured (imidized) by heating at 300 ° C. for 30 minutes, thereby forming an inner-side insulator layer 23 made of photosensitive polyimide having a thickness of 10 μm, as shown in FIG. did.
[0052]
And after forming the bump-shaped inner side electrode 27 in the inner side via hole 25 by copper and nickel / gold plating as shown in FIG.4 (n), it uses a roll laminator, and a protective film (weak adhesion type) The inner side electrode 27 is covered with an acid and alkali resistant material), and all of the support plate 32 is removed with an etchant containing ferric chloride as shown in FIG. As shown in FIG. 5 (o ′), the base 29 exposed on the outer insulator layer 22, that is, the chromium film, is removed with an alkaline etching solution, and then the outer side as shown in FIG. 5 (p). A bump-shaped outer electrode 26 in contact with the conductive path 31 of the insulator layer 22 is formed with copper and nickel / gold plating, and then solder balls are connected. Formed by a to obtain an interposer for a chip size package.
[0053]
Comparative Example 1
First, as shown in FIG. 7A, a copper foil having a thickness of 25 μm is used as the conductor layer 6, and an inner side insulator layer 7 made of polyimide having a thickness of 15 μm is formed on one surface of the conductor layer 6. Then, as shown in FIG. 7B, an adhesive layer 8 made of polyimide having a thickness of 10 μm was laminated on the inner insulating layer 7. Next, as shown in FIG. 7C, the conductor layer 6 is formed into a predetermined circuit pattern by the subtractive method, and then, as shown in FIG. 7D, the predetermined circuit pattern in the conductor layer 6 and An outer insulator layer 9 made of polyimide having a thickness of 10 μm was laminated on the finished surface. Then, as shown in FIG. 7E, the outer side via hole 10 having a hole diameter of 400 μm is formed in the outer side insulator layer 9 by laser processing, and as shown in FIG. 7F, the inner side insulator layer 9 is formed. 7, an inner via hole 11 having a hole diameter of 50 μm was formed by laser processing. And after forming copper and nickel / gold plating in the outer side via hole 10, the outer side electrode 12 is formed by connecting a solder ball, and copper and nickel / gold plating are formed in the inner side via hole 11. By forming the bump-shaped inner side electrode 13, an interposer for a chip size package as shown in FIG. 6 was obtained. (In FIG. 6, the inner side electrode 13 is made flat by connection with the semiconductor chip 18.)
Comparative Example 2
First, as shown in FIG. 8A, a copper foil having a thickness of 25 μm is used as the conductor layer 35, and an inner side insulator layer 36 made of polyimide having a thickness of 15 μm is formed on one surface of the conductor layer 35. Then, as shown in FIG. 8B, an adhesive layer 37 made of polyimide having a thickness of 10 μm was laminated on the inner-side insulator layer 36. Next, as shown in FIG. 8C, the conductor layer 35 is formed into a predetermined circuit pattern by the subtractive method, and then, as shown in FIG. 8D, the predetermined circuit pattern in the conductor layer 35 and The outer side precursor layer 38p was formed by apply | coating the photosensitive polyamic acid resin which consists of the following compositions to the finished surface, and drying for 20 minutes at 100 degreeC.
(Outer side polyamic acid resin composition)
Acid dianhydride component: 3,3 ′, 4,4′-oxydiphthalic dianhydride (0.5 mol), 2,2-bis (3,4-dicarboxyphenyl) hexafluoropropane dianhydride ( 0.5 mole)
Diamine component: 4,4'-diaminodiphenyl ether (0.5 mol), P-phenylenediamine (0.5 mol)
Photosensitizer: 1-ethyl-3,5-dimethoxycarbonyl-4- (2-nitrophenyl) -1,4-dihydropyridine (0.26 mol)
Organic solvent: N-methyl-2-pyrrolidone
Next, as shown in FIG. 9 (e), an irradiation beam (g-line) for exposure is irradiated to the outer precursor layer 38 p through the photomask 39 and heated at 170 ° C. for 3 minutes. Development processing was performed using the alkaline developer contained therein, thereby forming an outer via hole 40 having a hole diameter of 400 μm as shown in FIG. Thereafter, this is cured (imidized) by heating at 400 ° C. for 30 minutes, thereby forming an outer-side insulator layer 38 made of photosensitive polyimide having a thickness of 10 μm, as shown in FIG. did. Thereafter, as shown in FIG. 9H, an inner via hole 41 having a hole diameter of 50 μm was formed in the inner insulator layer 36 by laser processing. And the outer side electrode 12 and the inner side electrode 13 as shown in FIG. 6 were formed in the outer side via hole 40 and the inner side via hole 41 by the method similar to the comparative example 1, respectively.
[0054]
Evaluation
In Table 1, the time required for the drilling operation per 200 pieces of Example 1, Comparative Example 1 and Comparative Example 2 is shown in comparison.
[0055]
[Table 1]

[0056]
As is clear from Table 1, Comparative Example 1 in which both the outer via hole 10 and the inner via hole 11 are formed by laser processing takes about eight times as much work time as Example 1, and one of them It can be seen that the comparative example 2 in which the inner via hole 41 is formed by laser processing takes about four times as much work time as the first embodiment.
[0057]
【The invention's effect】
  As described above, the present inventionInterposer for chip size packageAccording to the manufacturing method ofBoth outer-side insulator layer and inner-side insulator layerIs made of photosensitive polyimide, so it can be used to form electrodesOuter side via hole and inner side via holeCan be formed with a fine pitch at a time with a photoresist. Therefore, high accuracy in a short timeOuter side via hole and inner side via holeAnd can be produced with good workability. Therefore, the present inventionChip size package interposer obtained by manufacturing method of chip size package interposerIs accurateOuter side via hole and inner side via holeFormed,Because it is manufactured efficiently, it is provided at a low price.,Usefully used.
[Brief description of the drawings]
FIG. 1 of the present inventionChip size package interposer obtained by manufacturing method of chip size package interposerOne implementationStateIt is sectional drawing shown.
FIG. 2 is a process diagram for forming an outer insulator layer for manufacturing the interposer shown in FIG. 1;
(A) is sectional drawing which shows the process of forming an outer side precursor layer in a support plate,
(B) is a cross-sectional view showing a step of exposing the outer precursor layer through a photomask;
(C) is a cross-sectional view showing a step of forming an outer via hole in the outer precursor layer by development processing;
(D) is sectional drawing which shows the process of forming the outer side insulator layer which consists of photosensitive polyimide by hardening an outer side precursor layer.
3 is a process diagram for forming a conductor layer by a semi-additive method for manufacturing the interposer shown in FIG. 1 following FIG. 2;
(E) is sectional drawing which shows the process of forming a base | substrate on an outer side insulator layer,
(F) is a cross-sectional view showing a step of forming a plating resist on the base,
(G) is sectional drawing which shows the process of forming a conductor layer on a base | substrate,
(H) is a cross-sectional view showing a step of removing the plating resist;
(I) is sectional drawing which shows the process of removing the foundation | substrate of the part in which the plating resist was formed.
FIG. 4 is a process diagram for forming an inner side insulator layer and an inner side electrode for manufacturing the interposer shown in FIG. 1 following FIG. 3;
(J) is a cross-sectional view showing a step of forming an inner side precursor layer on the conductor layer;
(K) is a cross-sectional view showing a step of exposing the inner-side precursor layer through a photomask;
(L) is a cross-sectional view showing a step of forming an inner via hole in the inner precursor layer by development processing;
(M) is a cross-sectional view showing a step of forming an inner insulator layer made of photosensitive polyimide by curing the inner precursor layer;
(N) is sectional drawing which shows the process of forming an inner side electrode in an inner side via hole.
FIG. 5 is a process diagram for manufacturing the interposer shown in FIG. 1 following FIG. 4, for removing the support plate, and for forming the outer electrode;
(O) is a cross-sectional view showing a step of removing the support plate;
(O ′) is a step of removing the base exposed on the outer insulating layer.Cross section showing,
(P) is sectional drawing which shows the process of forming an outer side electrode.
FIG. 6 is a cross-sectional view showing a conventional chip size package interposer.
7 is a process diagram for manufacturing the interposer shown in FIG. 6;
(A) is sectional drawing which shows the process of forming an inner side insulator layer in a conductor layer,
(B) is a cross-sectional view showing a step of forming an adhesive layer on the inner insulator layer;
(C) is a sectional view showing a step of forming a conductor layer in a predetermined circuit pattern;
(D) is sectional drawing which shows the process of forming an outer side insulator layer in the surface used as the predetermined circuit pattern in a conductor layer,
(E) is a cross-sectional view showing a step of forming an outer via hole in the outer insulator layer by laser processing;
(F) is sectional drawing which shows the process of forming an inner side via hole in an inner side insulator layer by laser processing.
FIG. 8 is a process diagram for manufacturing the interposer of Comparative Example 2;
(A) is sectional drawing which shows the process of forming an inner side insulator layer in a conductor layer,
(B) is a cross-sectional view showing a step of forming an adhesive layer on the inner insulator layer;
(C) is a sectional view showing a step of forming a conductor layer in a predetermined circuit pattern;
(D) is sectional drawing which shows the process of forming an outer side precursor layer in the surface used as the predetermined circuit pattern in a conductor layer.
9 is a process diagram for manufacturing the interposer of Comparative Example 2 following FIG. 8,
(E) is sectional drawing which shows the process of exposing an outer side precursor layer through a photomask,
(F) is a cross-sectional view showing a step of forming an outer via hole in the outer precursor layer by development processing;
(G) is a cross-sectional view showing a step of forming an outer insulator layer made of photosensitive polyimide by curing the outer precursor layer;
(H) is sectional drawing which shows the process of forming an inner side via hole in an inner side insulator layer by laser processing.

Claims (2)

Forming a precursor of photosensitive polyimide in a layer on a support plate made of stainless steel having a thickness of 10 to 100 μm, and forming an outer precursor layer;
The outer side precursor layer is exposed through a photomask, the exposed portion is heated to a predetermined temperature, and then developed to form an outer side via hole in the outer side precursor layer; and
Curing the outer precursor layer on which the outer via hole is formed by heating to form an outer insulator layer; and
Forming a conductor layer on which the predetermined circuit pattern is formed on the outer insulator layer;
Forming a precursor of a photosensitive polyimide into a layer on the conductor layer, and forming an inner side precursor layer;
Forming the inner via hole in the inner precursor layer by exposing the inner precursor layer through a photomask, heating the exposed portion to a predetermined temperature, and then developing;
Curing the inner side precursor layer in which the inner side via hole is formed by heating to form an inner side insulator layer; and
Removing the support plate after the step of forming the inner insulator layer;
A method for producing a chip size interposer, comprising: Forming a photosensitive polyimide precursor on a support plate made of stainless steel having a thickness of 10 to 100 μm to form an inner precursor layer;
Forming the inner via hole in the inner precursor layer by exposing the inner precursor layer through a photomask, heating the exposed portion to a predetermined temperature, and then developing;
Curing the inner side precursor layer in which the inner side via hole is formed by heating to form an inner side insulator layer; and
Forming a conductor layer on which a predetermined circuit pattern is formed on the inner insulator layer;
Forming a precursor of photosensitive polyimide into a layer on the conductor layer and forming an outer precursor layer;
The outer side precursor layer is exposed through a photomask, the exposed portion is heated to a predetermined temperature, and then developed to form an outer side via hole in the outer side precursor layer; and
Curing the outer precursor layer on which the outer via hole is formed by heating to form an outer insulator layer; and
Removing the support plate after the step of forming the outer insulator layer;
A method for producing a chip size interposer, comprising:

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