JP3958345B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for epitaxially growing a compound layer between semiconductor metals, particularly a semiconductor metal compound layer having high crystal orientation on a surface portion of a semiconductor layer.

  In semiconductor integrated circuit devices that require high-speed operation, with the recent miniaturization of semiconductor elements, the increase in sheet resistance and contact resistance of semiconductor layers in which impurities are diffused has become a problem.

As one method for solving this problem, a process for forming a silicide layer on the surface of a semiconductor layer has been proposed. Various metals have been proposed for forming the silicide layer, but the cobalt disilicide (CoSi ₂ ) layer formed using cobalt is superior in terms of both thermal stability and resistivity. Particular attention has been paid.

  However, when the surface portion of the silicon substrate is silicided using cobalt, the cobalt silicide layer aggregates or a spike defect occurs in the cobalt silicide layer in the reaction process between cobalt atoms and silicon atoms (IEDM 1995- 449 K. Goto). When the cobalt silicide layer is aggregated, there is a problem that disconnection occurs, and when a spike defect occurs, there is a problem that junction leakage occurs.

Therefore, in order to prevent the aggregation of the cobalt silicide layer and the occurrence of spike defects, as described below in a paper (Appl. Phys. Lett. 68, 1996, June), there is a method of forming a cobalt silicide layer by epitaxial growth. Proposed. That is, after an SiO _x (x <2) film having a thickness of 0.5 to 1.5 nm is formed on a semiconductor layer made of silicon crystal, cobalt is formed on the SiO _x film under an ultrahigh vacuum. A technique (Oxide Mediated Epitaxy; OME technique) is proposed in which a cobalt silicide layer is epitaxially grown by depositing a film to a thickness of several nanometers and then performing a heat treatment to react cobalt atoms with silicon atoms. . According to this technique, it is described that the SiO _x film plays a role of promoting the growth of the cobalt silicide layer.
Japanese Patent Laid-Open No. 09-064349 Japanese Patent Laid-Open No. 11-11980 JP-A-10-163130 JP 63-114122 A JP 09-161697 A Japanese Patent Application Laid-Open No. 06-295881

  However, the above-described method of forming a cobalt silicide layer by epitaxial growth requires an ultra-high vacuum apparatus for depositing a cobalt film, and the ultra-high vacuum apparatus is not used in a semiconductor process made of ordinary silicon. There is a problem that it is not suitable for mass production processes.

In the above-described method, a cobalt film is formed on a semiconductor layer through a SiO _x (x <2) film having a very thin film thickness and silicon in excess of the stoichiometric composition. Therefore, various problems occur due to variations in film quality and film thickness of the SiO _x film. That is, when there is a pinhole in the SiO _x film, cobalt and silicon react explosively through the pinhole, and therefore, the problem that the cobalt silicide layer cannot be epitaxially grown, and the SiO _x film When the film thickness varies, there is a problem that the cobalt silicide layer cannot be epitaxially grown well because the reaction between the cobalt atom and the silicon atom proceeds at a stretch in the thin film portion.

  In view of the above, the present invention provides a semiconductor intermetallic compound layer free of aggregation and spike defects, such as a cobalt silicide layer, which is normally used in a semiconductor mass production process, in a vacuum region or using a manufacturing apparatus. An object is to enable epitaxial growth.

In order to achieve the above object, the inventors of the present invention have studied the cause of the occurrence of aggregation and spike defects in the cobalt silicide layer formed by epitaxial growth, and as a result, have obtained knowledge as described below. In other words, the mechanism by which cobalt atoms and silicon atoms react to form cobalt silicide is due to a reaction of Co ₂ Si → CoSi → CoSi ₂ in view of thermodynamics. However, in the reaction path of Co ₂ Si → CoSi → CoSi ₂ , the interfacial energy is unstable and non-uniform, so that cobalt silicide is polycrystallized, which causes aggregation and spike defects.

Therefore, when a seed layer made of CoSi ₂ is formed at the interface between the semiconductor layer containing silicon and the cobalt film and then epitaxially grown, CoSi ₂ is formed without passing through a reaction path of Co ₂ Si → CoSi → CoSi _2. You have reached the conclusion that you can.

Therefore, as a result of various studies on the method of forming a seed layer made of CoSi _{2 at} the interface between the semiconductor layer containing silicon and the cobalt film, the concentration of oxygen atoms existing between the semiconductor layer and the cobalt film is controlled. Then, it has been found that a seed layer made of CoSi ₂ can be formed. Specifically, when a cobalt film is deposited on a semiconductor layer in which oxygen atoms are distributed in a region near the surface, the amount of oxygen atoms interposed between the semiconductor layer and the cobalt film is determined by the semiconductor layer and the cobalt film. since reduced as compared with the case of interposing the SiO _x film between it has been found that can form a seed layer made of CoSi ₂ between the semiconductor layer and the cobalt film.

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a compound layer comprising a semiconductor element and a nonmetallic element that is one of oxygen, nitrogen, and fluorine on a semiconductor layer made of silicon. A step of irradiating the compound layer with particle energy rays to distribute nonmetallic elements contained in the compound layer in the semiconductor layer by recoil, a step of removing the compound layer, and A step of depositing a metal film made of a transition metal, and a silicon intermetallic compound on the surface of the semiconductor layer by reacting silicon constituting the semiconductor layer and transition metal constituting the metal film by subjecting the metal film to a heat treatment And epitaxially growing the layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a compound layer comprising a semiconductor element and a nonmetallic element that is one of oxygen, nitrogen, and fluorine on a semiconductor layer made of silicon. , Irradiating the compound layer with particle energy rays to distribute non-metallic elements contained in the compound layer in the semiconductor layer by recoil, removing the compound layer, and a transition metal on the semiconductor layer A silicon transition intermetallic compound layer is formed on the surface of the semiconductor layer by depositing a metal film comprising: and reacting the silicon constituting the semiconductor layer with the transition metal constituting the metal film by performing a heat treatment on the metal film. Epitaxial growth.

According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method according to the first or second aspect of the present invention, wherein the semiconductor layer has a face-centered cubic crystal structure, and a silicon transition metal. The intermetallic compound layer has a face-centered cubic crystal structure, and the compound layer composed of a semiconductor element and a nonmetallic element is amorphous.

According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the first or second aspect, wherein the particle energy beam is an Ar ion beam.

  The method for manufacturing a semiconductor device according to claim 5 of the present invention is the method for manufacturing a semiconductor device according to claim 1 or 2, wherein the semiconductor layer is a silicon layer, the nonmetallic element is oxygen, and the metal film is It is a cobalt film, and the silicon transition intermetallic compound layer is a cobalt silicide layer.

A method for manufacturing a semiconductor device according to a sixth aspect of the present invention is the method for manufacturing a semiconductor device according to the first or second aspect, wherein the number of atoms per unit area of oxygen in a region in which oxygen is distributed is 4 ×. 10 ¹⁴ ~ 4x10 ¹⁵ cm ^-2 It is.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate electrode on a semiconductor layer made of silicon; forming an impurity layer on both sides of the gate electrode in the semiconductor layer; A compound layer including a semiconductor element and a non-metallic element that is one of oxygen, nitrogen, and fluorine; and a compound energy layer irradiated with particle energy rays to be included in the compound layer A step of distributing the nonmetallic element in the semiconductor layer by recoil, a step of removing the compound layer, a step of depositing a metal film made of a transition metal on the semiconductor layer, and subjecting the metal film to a heat treatment And a step of causing a silicon transition intermetallic compound layer to epitaxially grow on the surface of the semiconductor layer by reacting silicon constituting the metal and a transition metal constituting the metal film.

According to the onset bright, to react the metal constituting the element and the metal film constituting the semiconductor layer is subjected to heat treatment in a state of being distributed non-metallic element in the region near the surface of the semiconductor layer, a metal film Since it is possible to avoid a situation in which the constituent metal and the element constituting the semiconductor layer react at a stretch, it is possible to prevent the epitaxial semiconductor intermetallic compound layer from being polycrystallized.

  Therefore, according to the present invention, an epitaxial semiconductor intermetallic compound layer free from agglomeration and spike defects can be stably formed at a low temperature in a vacuum region normally used in a semiconductor mass production process.

( Reference Embodiment 1 )
A semiconductor device according to the reference embodiment 1 will be described with reference to FIGS. 1 (a) and (b).

FIG. 1A shows a planar structure of the semiconductor device according to the first embodiment , and FIG. 1B shows a cross-sectional structure taken along line Ib-Ib in FIG.

The semiconductor device according to the reference embodiment 1, CMOS, may be any type of transistors pMOS and nMOS, it will be described here n-type MOS transistor.

  As shown in FIGS. 1A and 1B, an n-type channel stopper 11 is formed on a surface portion of a semiconductor substrate 10 made of an n-type silicon crystal and having a resistivity of several Ω · cm. A field insulating film 13 serving as an element isolation region is formed on the channel stopper 11, and a p-type well region 12 is formed in a region surrounded by the channel stopper 11 in the semiconductor substrate 10.

  An n-type low-concentration impurity diffusion layer 16 and an n-type high-concentration impurity diffusion layer 18 constituting an LDD structure are formed in a region serving as a source or drain inside the p-type well region 12. A gate electrode 15 made of a polycrystalline silicon film is provided between the source region and the drain region on the semiconductor substrate 10 via a gate insulating film 14 made of a silicon oxide film. A sidewall 17 made of a silicon oxide film is formed.

As a feature of the first embodiment, an epitaxial growth layer made of cobalt disilicide (CoSi ₂ ) is formed on the surface portion of the n-type high-concentration impurity diffusion layer 18, and a large amount is formed on the surface portion of the gate electrode 15. A polycrystalline cobalt disilicide layer having an epitaxial relationship with individual crystal grains of crystalline silicon is simultaneously formed under the same conditions as the epitaxial growth layer is formed on the n-type high-concentration impurity diffusion layer 18. ing. The thickness of the silicide layer grown on each surface portion of the n-type high concentration impurity diffusion layer 18 and the gate electrode 15 is, for example, about 30 to 50 nm. For this reason, since the resistance values of the n-type high concentration impurity diffusion layer 18 and the gate electrode 15 are sufficiently reduced, the performance of the semiconductor integrated circuit device having the MOSFET according to the first embodiment is improved.

  An interlayer insulating film 22 is deposited on the semiconductor substrate 10, and a metal wiring 24 made of, for example, an aluminum alloy film is formed on the interlayer insulating film 22. The metal wiring 24 is a protective insulating film 25. Covered with The metal wiring 24 is connected to an epitaxial silicide layer 21 formed on the surface portion of the n-type high-concentration impurity diffusion layer 18 through a contact hole 23 formed in the interlayer insulating film 22. For this reason, the contact resistance between the n-type high concentration impurity diffusion layer 18 and the metal wiring 24 is sufficiently reduced.

( Reference Embodiment 2 )
Hereinafter, as a reference embodiment 2 , a semiconductor device manufacturing method according to the reference embodiment 1 will be described with reference to FIGS. 2 (a) to 2 (c), FIGS. 3 (a) to 3 (c), and FIGS. 4 (a) and 4 (b). Will be described with reference to FIG.

  First, after forming a thin silicon oxide film on the surface of the semiconductor substrate 100 made of n-type silicon crystal shown in FIG. 2A, a silicon nitride film is deposited on the silicon oxide film, and then By patterning the silicon nitride film using a known photolithography technique and etching technique, the field insulating film formation region in the silicon nitride film is removed.

  Next, using a silicon nitride film patterned on the semiconductor substrate 100 as a mask, an n-type impurity such as phosphorus or arsenic is ion-implanted at a high concentration to form a channel stopper 101, and then the semiconductor substrate 100 is made of boron or the like. A p-type well region 102 is formed by ion implantation of p-type impurities. Thereafter, a heat treatment is performed on the semiconductor substrate 100 to perform a LOCOS method for oxidizing a region of the surface portion of the semiconductor substrate 100 that is not covered with the silicon nitride film, so that the surface portion of the semiconductor substrate 100 has a thickness of, for example, 400 nm. A field insulating film 103 is formed. Note that the channel stopper 101 and the p-type well region 102 are activated by this heat treatment. Thereafter, the silicon oxide film and the silicon nitride film are removed.

  Next, a gate insulating film 104 made of a silicon oxide film having a film thickness of, for example, 5 to 10 nm is formed on the entire surface of the semiconductor substrate 100 by, for example, thermal oxidation, and then the gate insulating film 104 is formed by, for example, CVD. After depositing a polycrystalline silicon film thereon, a gate electrode 105 is formed by patterning the polycrystalline silicon film using a known photolithography technique and etching technique.

  Next, n-type impurities such as arsenic or phosphorus are ion-implanted into the semiconductor substrate 100 using the gate electrode 105 as a mask to form an n-type low-concentration impurity layer 106 as shown in FIG. To do.

  Next, after depositing a silicon oxide film over the entire surface of the semiconductor substrate 100, anisotropic etching is performed on the silicon oxide film, and as shown in FIG. Sidewalls 107 are formed on the side surfaces. Thereafter, n-type impurities such as arsenic or phosphorus are ion-implanted at a high concentration into the semiconductor substrate 100 using the gate electrode 105 and the sidewall 107 as a mask to form an n-type high-concentration impurity layer 108. The n-type low-concentration impurity layer 106 and the high-concentration impurity layer 108 are activated by heat treatment.

  The sidewall 107 may be a silicon nitride film instead of the silicon oxide film. Moreover, you may perform the heat processing for activation in the 1st time process and the 2nd heat processing process which are mentioned later.

  Next, as shown in FIG. 3A, non-metal element ions such as oxygen ions are implanted into the semiconductor substrate 100 with a low acceleration energy of 100 to 500 eV, for example, and as shown in FIG. An oxygen atom distribution region 109 in which oxygen atoms are distributed in the substrate surface direction is formed in a region near the surface of the n-type high concentration impurity layer 108 and a region near the surface of the gate electrode 105. As a method for forming the oxygen atom distribution region 109, oxygen atoms may be distributed by plasma doping instead of oxygen ion implantation.

The depth at which oxygen atoms constituting the oxygen atom distribution region 109 are distributed is preferably in the range of 0.5 to 5 nm from the surface of the n-type high concentration impurity layer 108 or the gate electrode 105, and the oxygen atom distribution region 109 is formed. As a density | concentration of the oxygen atom to perform, the range of 4 * 10 ^{< 14} > cm ^<-2 > ^-4 * 10 ^{< 15} > cm ^<-2 > is preferable. These reasons will be described later.

Next, as shown in FIG. 3C, by performing sputtering in a sputtering apparatus in which the inside of the chamber is maintained at a vacuum degree of 1 × 10 ⁵ to 1 × 10 ⁷ Pa, the upper surface of the semiconductor substrate 100 is obtained. A metal film such as a cobalt film 110 is deposited over the entire surface.

An oxygen atom distribution region 109 is formed between the cobalt film 110 and the n-type high-concentration impurity layer 108 or the gate electrode 105, and oxygen atoms are introduced from the surface of the n-type high-concentration impurity layer 108 or the gate electrode 105. It is distributed in a depth range of 0.5 to 5 nm. Therefore, the diffusion of cobalt atoms constituting the cobalt film 110 into the semiconductor substrate 100 is suppressed by the oxygen atom distribution region 109. Further, since the silicon crystal lattice existing below the oxygen atom distribution region 109 is seen from the cobalt atoms constituting the cobalt film 110, the region above the oxygen atom distribution region 109 is disturbed by ion implantation or plasma doping. Even though the cobalt atoms react while being influenced by the crystal structure of the lower region of the oxygen atom distribution region 109 in the semiconductor substrate 100, the interface between the n-type high concentration impurity layer 108 and the cobalt film 110 Cobalt disilicide (CoSi ₂ ) nuclei (not shown) having a lattice constant close to that of silicon crystals are formed. The gate electrode 105 is made of polycrystalline silicon, but for each crystal grain, a nucleus of cobalt disilicide (CoSi ₂ ) is formed as in the reaction between cobalt atoms and silicon atoms in the n-type high concentration impurity layer 108. Is formed.

Next, first heat treatment (RTA: Rapid Thermal Anneal) is performed in which the semiconductor substrate 100 is held at a temperature of 500 ° C. for 10 seconds. In this case, since the cobalt atoms constituting the cobalt film 110 diffuse into the silicon region through the cobalt disilicide nucleus and the cobalt atoms react with the silicon atoms, as shown in FIG. A cobalt disilicide (CoSi ₂ ) epitaxial growth layer (hereinafter referred to as a first epitaxial layer) corresponding to the crystal structure of the cobalt disilicide nucleus already formed on the surface portions of the n-type high concentration impurity layer 108 and the gate electrode 105. 111A) is formed.

  When the thickness of the cobalt film 110 is 5 nm, the thickness of the first epitaxial silicide layer 111A is about 17 to 18 nm. When the thickness of the cobalt film 110 is 10 nm, the first epitaxial silicide layer is formed. The film thickness of 111A is about 34 to 36 nm.

  When the crystal structure of the semiconductor substrate 100 is a face-centered cubic type, the crystal structure of the first epitaxial silicide layer 111A is also a face-centered cubic type, and the crystal structure of the semiconductor substrate 100 is a diamond type or a zinc blende type. Sometimes, the crystal structure of the first epitaxial silicide layer 111A is a calcium fluoride type (meteorite).

  As described above, in the region near the surface of the n-type high-concentration impurity layer 108 and the gate electrode 105, the oxygen atom distribution region 109 is formed at a depth of 0.5 to 5 nm from the surface, and the cobalt film 110 is formed. Since the cobalt atoms constituting the n-type high-concentration impurity layer 108 or the silicon atoms constituting the gate electrode 105 are not in direct contact with each other, the cobalt atoms and the silicon atoms do not react at a stretch, so that the first epitaxial silicide layer A situation in which 111A is aggregated or polycrystallized can be prevented.

By the way, when the concentration of oxygen atoms constituting the oxygen atom distribution region 109 is lower than 4 × 10 ¹⁴ cm ⁻² , cobalt atoms and silicon atoms react at a stretch, and the first epitaxial silicide layer 111A aggregates. If the concentration of oxygen atoms is higher than 4 × 10 ¹⁵ cm ⁻² , the distance between the cobalt atoms and the crystal lattice of the semiconductor substrate 100 increases, so that the cobalt atoms and silicon There is a risk that the reaction with the atoms will not be performed well. Therefore, the concentration of oxygen atoms constituting the oxygen atom distribution region 109 is preferably in the range of 4 × 10 ¹⁴ cm ⁻² to 4 × 10 ¹⁵ cm ⁻² .

Note that in the first epitaxial silicide layer 111A, all the layers may be made of cobalt disilicide (CoSi ₂ ), and the lower layer (interface side with the silicon layer) is cobalt disilicide (CoSi ₂ ). In addition, the upper layer (cobalt film 110 side) may be cobalt silicide (CoSi). In the first epitaxial silicide layer 111A of Reference Embodiment 2 , the lower layer is cobalt disilicide and the upper layer is cobalt silicide. When the cobalt disilicide layer is formed at least at the interface with the silicon layer, the cobalt silicide layer does not aggregate, and thus the leakage current can be reduced.

  Next, as shown in FIG. 4A, the cobalt film 110 that has not reacted in the first heat treatment is replaced with an etchant made of, for example, a mixed solution of an ammonia solution and a hydrogen peroxide solution or a hydrochloric acid mixed acid solution. Then, a second heat treatment (RTA) is performed in which the semiconductor substrate 100 is held at a temperature of 800 ° C. for 10 seconds. As a result, the cobalt silicide on the upper layer of the first epitaxial silicide layer 111A also grows to become cobalt disilicide, so that the first epitaxial silicide layer 111A is the second epitaxial layer in which all layers are made of cobalt disilicide. The silicide layer 111B is changed.

When all the layers of the first epitaxial silicide layer 111A are made of cobalt disilicide (CoSi ₂ ), the second heat treatment can be omitted. In this case, the second epitaxial silicide layer 111B in the following description is read as the first epitaxial silicide layer 111A.

  Next, as shown in FIG. 4B, an interlayer insulating film 112 made of a silicon oxide film is deposited on the entire surface of the semiconductor substrate 100 by, for example, a CVD method using TEOS (tetraethoxysilane). A contact hole 113 is formed in the interlayer insulating film 112 using a known photolithography technique and etching technique.

Next, after depositing, for example, an aluminum alloy film so as to be embedded in the contact hole 113 over the entire surface of the semiconductor substrate 100 by, for example, sputtering, the aluminum alloy film is patterned using a well-known photolithography technique and etching technique. Thus, the metal wiring 114 is formed. Next, when a protective insulating film 115 made of, for example, a laminated body of a silicon oxide film and a silicon nitride film is deposited on the metal wiring 114 by using, for example, plasma CVD, the semiconductor device according to the first embodiment is obtained. .

  As the metal wiring 114, a laminated film of an aluminum alloy film and a titanium nitride film or a tungsten film may be used instead of the aluminum alloy film.

According to the second embodiment, since the second epitaxial silicide layer 111B made of cobalt disilicide is formed on the surface portions of the n-type high concentration impurity layer 108 and the gate electrode 105, the n-type high concentration impurity layer is formed. 108 and the gate electrode 105 can be reduced to a sheet resistance of about 5Ω / □, so that the sheet resistance (100Ω / □) when the second epitaxial silicide layer 111B is not formed can be greatly reduced, and the contact resistance can be reduced. Therefore, the performance of the semiconductor integrated circuit device having the MOSFET can be improved.

Further, according to the second embodiment , a non-metal element such as an oxygen atom 109 is distributed in a region near the surface of the n-type high-concentration impurity layer 108 and a region near the surface of the gate electrode 105 and then a metal film such as cobalt. A film 110 is deposited, and then the first and second heat treatments are performed to form a second epitaxial silicide made of cobalt disilicide on the surface portion of the n-type high concentration impurity layer 108 and the surface portion of the gate electrode 105. Since the layer 111B is formed, it is possible to avoid a situation in which cobalt atoms and silicon atoms react at a stroke, so that it is possible to avoid a situation in which the second epitaxial silicide layer 111B is aggregated or polycrystallized, and the second epitaxial silicide layer. A situation in which spike defects are formed in 111B can be avoided. For this reason, disconnection due to aggregation or polycrystallization of the epitaxial silicide layer can be prevented, and junction leakage due to spike defects can be prevented.

Further, according to the second embodiment , the oxygen atoms 109 are distributed in the region near the surface of the n-type high concentration impurity layer 108 and the region near the surface of the gate electrode 105, that is, the n-type high concentration impurity layer. 108, the first heat treatment is performed at a low temperature, for example, 500 ° C. in order to perform the first heat treatment in a state where low concentration oxygen atoms 109 are interposed between the gate electrode 105 and the cobalt film 110. Can do.

In the second embodiment , the second epitaxial silicide layer 111B made of cobalt disilicide is formed on both the surface portion of the n-type high-concentration impurity layer 108 and the surface portion of the gate electrode 105. Thus, the second epitaxial silicide layer 111 </ b> B may be formed only on one of the surface portion of the n-type high concentration impurity layer 108 and the surface portion of the gate electrode 105.

In the second embodiment , oxygen atoms are distributed as nonmetallic elements in the region near the surface of the n-type high concentration impurity layer 108 and the region near the surface of the gate electrode 105, but instead of oxygen atoms, Nitrogen atoms or fluorine atoms may be distributed.

In the second embodiment , the cobalt film 110 is deposited as the metal film to form the second epitaxial silicide layer 111B made of cobalt disilicide. However, instead of the cobalt film 110, other materials such as nickel or iron are used. A metal film made of a transition metal may be deposited to form an epitaxial silicide layer made of transition metal and silicon constituting the metal film.

( One embodiment of the present invention )
Hereinafter, as an embodiment of the present invention, a method for manufacturing a semiconductor device according to Reference Embodiment 1 will be described with reference to FIGS. 5 (a) to 5 (c), FIGS. 6 (a) to 6 (c), FIGS. This will be described with reference to b).

First, similarly to the reference embodiment 2 , as shown in FIG. 5A, a p-type well region 202 is formed by ion implantation of p-type impurities such as boron into a semiconductor substrate 200 made of n-type silicon crystal. Thereafter, a field insulating film 203 having a thickness of, for example, 400 nm is formed on the surface portion of the semiconductor substrate 200 by the LOCOS method. Next, after forming a gate insulating film 204 made of a silicon oxide film having a film thickness of, for example, 5 to 10 nm over the entire surface of the semiconductor substrate 200, the polycrystalline silicon is formed on the gate insulating film 204 by, for example, a CVD method. After depositing the film, the polycrystalline silicon film is patterned to form the gate electrode 205.

  Next, n-type impurities such as arsenic or phosphorus are ion-implanted into the semiconductor substrate 200 using the gate electrode 205 as a mask to form an n-type low-concentration impurity layer 206 as shown in FIG. To do.

  Next, after a silicon oxide film is deposited on the entire surface of the semiconductor substrate 200, anisotropic etching is performed on the silicon oxide film, and as shown in FIG. After the sidewalls 207 are formed on the side surfaces, n-type impurities such as arsenic or phosphorus are ion-implanted at a high concentration into the semiconductor substrate 200 using the gate electrode 205 and the sidewalls 207 as a mask to form an n-type high-concentration impurity layer 208. After the formation, heat treatment is performed on the semiconductor substrate 200 to activate the n-type low concentration impurity layer 206 and the high concentration impurity layer 208.

  Next, as shown in FIG. 6A, a compound layer made of a semiconductor element and a non-metal film and having a thickness of about 10 nm, for example, a silicon oxide film 209 is formed on the entire surface of the semiconductor substrate 200.

As a method for forming the silicon oxide film 209, a solution having oxidizing power (for example, a mixed solution composed of ammonia, hydrogen peroxide solution, and pure water) is supplied to the surface of the semiconductor substrate 200, and a so-called Chemical Oxide (SiO ₂ ) film is formed. A second method of forming a silicon oxide film having a thickness of about 10 nm by exposing the surface of the semiconductor substrate 200 to oxygen plasma, or a semiconductor substrate 200 in an oxidizing atmosphere at 750 to 900. A third method for forming a thermal oxide film having a thickness of about 10 nm by heating to 0 ° C. is exemplified.

  Next, as shown in FIG. 6B, the silicon oxide film 209 is irradiated with a particle energy beam made of a nonmetallic element, for example, an Ar ion beam with low energy. In this way, due to the recoil of the particle energy beam, the oxygen atoms constituting the silicon oxide film 209 are regions near the surface of the n-type high-concentration impurity layer 208 as shown in FIG. In addition, an oxygen atom distribution region 210 is formed in a region near the surface of the gate electrode 205 in the substrate surface direction. In this case, oxygen atoms constituting the silicon oxide film 209 may be sputtered by irradiation with particle energy rays.

The depth at which oxygen atoms constituting the oxygen atom distribution region 210 are distributed is preferably in the range of 0.5 to 5 nm from the surface of the n-type high concentration impurity layer 208 or the gate electrode 205, and the oxygen atom distribution region 210 The concentration of oxygen atoms that constitutes is preferably in the range of 4 × 10 ¹⁴ cm ⁻² to 4 × 10 ¹⁵ cm ⁻² . These reasons are the same as those in the second embodiment .

  When Ar ion irradiation is performed as particle energy beam irradiation, if the acceleration energy of Ar ions is 100 eV, the peak of oxygen atom distribution in the oxygen atom distribution region 210 is at a depth of 1 nm from the surface of the silicon region. Thus, if the acceleration energy of Ar ions is 300 eV, the peak of the distribution of oxygen atoms is 2 nm deep from the surface of the silicon region.

Next, as shown in FIG. 7A, after the silicon oxide film 209 is removed, a sputtering method is performed in a sputtering apparatus in which the inside of the chamber is maintained at a vacuum degree of 1 × 10 ⁵ to 1 × 10 ⁷ Pa. As a result, a metal film such as a cobalt film 211 is deposited on the entire surface of the semiconductor substrate 200. In this way, as in the second embodiment , cobalt atoms constituting the cobalt film 211 are incorporated into the silicon crystal lattice, so that the cobalt disilicide (at the interface between the n-type high-concentration impurity layer 208 and the cobalt film 210 is formed. CoSi ₂ ) nuclei are formed, and cobalt disilicide (CoSi ₂ ) nuclei are also formed for individual crystal grains of the gate electrode 205.

  Next, a first heat treatment (RTA) is performed to hold the semiconductor substrate 200 at a temperature of 500 ° C. for 10 seconds, and a first epitaxial layer is formed on the surface portions of the n-type high concentration impurity layer 208 and the gate electrode 205. A silicide layer 212A is formed.

In one embodiment of the present invention, an oxygen atom distribution region 210 is formed in the region near the surface of the n-type high concentration impurity layer 208 and the gate electrode 205 at a depth of 0.5 to 5 nm from the surface. Therefore, since the cobalt atom and the silicon atom do not react at a stretch, it is possible to prevent the first epitaxial silicide layer 212A from being aggregated or polycrystallized.

  Here, the result of measuring the concentration of oxygen atoms constituting the oxygen atom distribution region 210 will be described.

FIG. 8 shows the result of measuring the concentration of oxygen atoms by low energy SIMS, the horizontal axis represents the oxygen concentration (unit: number of atoms / cm ² ), and the vertical axis represents the degree of epitaxial growth. The degree of epitaxial growth can be expressed by intensity, and it can be said that the greater the intensity value, the greater the degree of epitaxial growth. Here, the vertical axis represents the peak intensity of CoSi ₂ (400).

From the data shown in FIG. 8, it can be seen how the concentration of oxygen distributed near the surface of the semiconductor substrate 200 can form the first epitaxial silicide layer 212A made of cobalt disilicide (CoSi ₂ ). Further, from FIG. 8, the cobalt disilicide is practically epitaxially grown without any heat resistance problem when the value on the vertical axis is 100 or more. That is, when the value on the vertical axis is 100 or more, cobalt disilicide has heat resistance even at a high temperature of about 800 ° C., and can prevent agglomeration even at a high temperature. The value of the vertical axis is 100 or more when the oxygen concentration is in the range of 4 × 10 ¹⁴ cm ⁻² to 4 × 10 ¹⁵ cm ⁻² atoms / cm ² .

Therefore, when the concentration of oxygen atoms in the oxygen atom distribution region 210 is controlled to 4 × 10 ¹⁴ cm ⁻² to 4 × 10 ¹⁵ cm ⁻² atoms / cm ² , the aggregation of cobalt disilicide (CoSi ₂ ) is prevented, It can be seen that the first epitaxial silicide layer 212A can be favorably grown.

In the first epitaxial silicide layer 212A, all the layers may be made of cobalt disilicide (CoSi ₂ ), and the lower layer (interface side with the silicon layer) is cobalt disilicide (CoSi ₂ ). In addition, the upper layer (cobalt film 110 side) may be cobalt silicide (CoSi). In this way, since the cobalt silicide layer does not aggregate, leakage current can be reduced.

  Next, as shown in FIG. 7B, the cobalt film 211 that has not reacted in the first heat treatment is used, for example, by using an etchant made of a mixed solution of ammonia solution and hydrogen peroxide solution or a hydrochloric acid mixed acid solution. Then, a second heat treatment (RTA) is performed in which the semiconductor substrate 200 is held at a temperature of 800 ° C. for 10 seconds, so that the first epitaxial silicide layer 212A is formed of a cobalt disilicide having all layers made of cobalt disilicide. 2 to the epitaxial silicide layer 212B.

  When all the layers of the first epitaxial silicide layer 212A are made of cobalt disilicide, the second heat treatment can be omitted. In this case, the second epitaxial silicide layer 212B in the following description is read as the first epitaxial silicide layer 212A.

Next, although not shown, when an interlayer insulating film, contact holes, metal wirings, and a protective insulating film are formed in the same manner as in the second embodiment , the semiconductor device according to the first embodiment is obtained.

According to one embodiment of the present invention, since the second epitaxial silicide layer 212B made of cobalt disilicide is formed on the surface portions of the n-type high concentration impurity layer 208 and the gate electrode 205, the n-type high concentration impurity layer 208B is formed. Since the sheet resistance of the impurity layer 208 and the gate electrode 205 can be reduced to about 5Ω / □ and the contact resistance can be reduced, the performance of the semiconductor integrated circuit device having the MOSFET can be improved.

In addition, according to an embodiment of the present invention , the silicon oxide film 209 is deposited on the semiconductor substrate 200 and then irradiated with particle energy rays, so that the oxygen atoms 210 constituting the silicon oxide film 209 are n-type. It can be reliably distributed in a region near the surface of the high concentration impurity layer 208 and a region near the surface of the gate electrode 205.

  Further, after a nonmetallic element such as oxygen atom 210 is distributed in a region near the surface of the n-type high concentration impurity layer 208 and a region near the surface of the gate electrode 205, a metal film such as a cobalt film 211 is deposited, and then In order to form the second epitaxial silicide layer 212B made of cobalt disilicide on the surface portion of the n-type high concentration impurity layer 208 and the surface portion of the gate electrode 205 by performing the first and second heat treatments, Since a situation where atoms and silicon atoms react at a time can be avoided, a situation where the second epitaxial silicide layer 212B is agglomerated or polycrystallized can be avoided, and a spike defect is formed in the second epitaxial silicide layer 212B. The situation can be avoided. For this reason, disconnection due to aggregation or polycrystallization of the epitaxial silicide layer can be prevented, and junction leakage due to spike defects can be prevented.

Furthermore, according to an embodiment of the present invention, the first heat treatment is performed in a state where oxygen atoms 210 are distributed in a region near the surface of the n-type high concentration impurity layer 208 and a region near the surface of the gate electrode 205. Therefore, the first heat treatment can be performed at a low temperature, for example, 500 ° C.

In the embodiment of the present invention, the second epitaxial silicide layer 212B made of cobalt disilicide is formed on both the surface portion of the n-type high concentration impurity layer 208 and the surface portion of the gate electrode 205. Instead, the second epitaxial silicide layer 212B may be formed only on one of the surface portion of the n-type high concentration impurity layer 208 and the surface portion of the gate electrode 205.

In one embodiment of the present invention , the silicon oxide film 209 is formed on the semiconductor substrate 200. Instead, a silicon nitride film or a silicon fluoride film is deposited, and nitrogen atoms or fluorine atoms are deposited. The n-type high concentration impurity layer 208 may be distributed in a region near the surface and a region near the surface of the gate electrode 205.

In one embodiment of the present invention, the cobalt film 211 is deposited as the metal film to form the second epitaxial silicide layer 212B made of cobalt disilicide. Instead of the cobalt film 211, nickel or iron or the like is used. A metal film made of another transition metal may be deposited to form an epitaxial silicide layer made of transition metal and silicon constituting the metal film.

(Modification of one embodiment of the present invention )
In one embodiment of the present invention , the silicon oxide film 209 is irradiated with particle energy rays made of a non-metallic element, for example, Ar ions, so that oxygen atoms 210 are converted into regions near the surface of the n-type high-concentration impurity layer 208 and The silicon oxide film 209 is removed after being distributed in the region near the surface of the gate electrode 205. However, in a modification of the embodiment of the present invention, the mass and energy amount of particles used for the particle energy line, such as Ar ions, are changed. When the oxygen atoms 210 are controlled to be distributed in the region near the surface of the n-type high concentration impurity layer 208 and the region near the surface of the gate electrode 205, the silicon oxide film 209 is removed by irradiation with particle energy rays. In this way, the step of removing the silicon oxide film 209 can be omitted.

  The present invention is useful for a method of forming an epitaxial semiconductor intermetallic compound layer free from agglomeration and spike defects in a vacuum region generally used in a semiconductor mass production process at a low temperature.

(A) is a figure which shows the planar structure of the semiconductor device which concerns on Reference Embodiment 1, (b) is sectional drawing of the Ib-Ib line | wire in (a). (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on Reference Embodiment 2. FIG. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on Reference Embodiment 2. FIG. (A) And (b) is sectional drawing which shows each process of the manufacturing method of the semiconductor device concerning the reference embodiment 2 . (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention . (A) ~ (c) are sectional views showing the steps in a manufacturing method of a semiconductor device according to an embodiment of the present invention. (A) And (b) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention . FIG. 6 is a characteristic diagram showing the relationship between the oxygen concentration and the degree of epitaxial growth, as a result of measuring the concentration of oxygen atoms by low energy SIMS.

Claims (7)

Forming a compound layer made of a semiconductor element and a non-metallic element that is one of oxygen, nitrogen, and fluorine on the semiconductor layer made of silicon;
Irradiating the compound layer with particle energy rays and distributing the non-metallic elements contained in the compound layer in the semiconductor layer by recoil; and
Removing the compound layer;
Depositing a metal film comprising a transition metal on the semiconductor layer,
And a step of epitaxially growing a silicon intermetallic compound layer on the surface of the semiconductor layer by reacting silicon constituting the semiconductor layer with a transition metal constituting the metal film by performing a heat treatment on the metal film. A method for manufacturing a semiconductor device. Forming a compound layer made of a semiconductor element and a non-metallic element that is one of oxygen, nitrogen, and fluorine on the semiconductor layer made of silicon;
Irradiating the compound layer with particle energy rays to distribute the nonmetallic element contained in the compound layer in the semiconductor layer by recoil, and removing the compound layer;
Depositing a metal film comprising a transition metal on the semiconductor layer,
And a step of epitaxially growing a silicon intermetallic compound layer on the surface of the semiconductor layer by reacting silicon constituting the semiconductor layer with a transition metal constituting the metal film by performing a heat treatment on the metal film. A method for manufacturing a semiconductor device. The semiconductor layer has a face-centered cubic crystal structure;
The silicon transition intermetallic compound layer has a face-centered cubic crystal structure,
The method for manufacturing a semiconductor device according to claim 1 , wherein the compound layer made of the semiconductor element and the nonmetallic element is amorphous. The method for manufacturing a semiconductor device according to claim 1, wherein the particle energy beam is an Ar ion beam . The semiconductor layer is a silicon layer;
The non-metallic element is oxygen;
The metal film is a cobalt film;
The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the silicon transition metal intermetallic compound layer is a cobalt silicide layer. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the number of atoms per unit area of oxygen in the region in which oxygen is distributed is 4 * 10 < ¹⁴ > to 4 * 10 ^{< 15} > cm ^<-2 >. Forming a gate electrode on the semiconductor layer made of silicon ;
Forming an impurity layer on both sides of the gate electrode in the semiconductor layer;
Forming a compound layer comprising a semiconductor element and a non-metallic element that is one of oxygen, nitrogen, and fluorine on the semiconductor layer;
Irradiating the compound layer with particle energy rays and distributing the non-metallic elements contained in the compound layer in the semiconductor layer by recoil; and
Removing the compound layer;
Depositing a metal film made of a transition metal on the semiconductor layer;
And a step of epitaxially growing a silicon intermetallic compound layer on the surface of the semiconductor layer by reacting silicon constituting the semiconductor layer with a transition metal constituting the metal film by performing a heat treatment on the metal film. A method for manufacturing a semiconductor device.

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