JPH09260658A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a junction having not a high-concentration defect and a dislocation, which are generated by high-energy ion incidence using ion- implantation or the like, by a method, wherein the thermally controlled shallow junction of a depth of 0.005μm or thereabouts can be formed. SOLUTION: When this device has a junction using a transition metal as a dopant in the surface part of a semiconductor substrate, a gate region 43 is formed on the surface part of the n-type Si substrate 41 and thereafter, p<+> layers 44 (1) of a thickness of 0.05μm or thereabouts are formed in regions, used as source and drain regions, by a low-accelerating ion-implantation method. Then, a Ti film 47 is deposited on the surface of the substrate 41 by a selective CVD method. Then, a reaction in solid phase is made for 30 minutes or thereabouts at a temperature, which does not reach the temperature for forming a compound consisting of Si and Ti, and in a temperature region (about 460 deg.C), which generates the interdiffusion of the Si and the T, and p<+> layers 44 are formed to positions deeper than those of the layers 44 (1).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a shallow junction in a fine element structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art As semiconductor devices have been highly integrated in recent years, electric circuits have been miniaturized, and field effect transistors (FETs), which are basic elements, have been further miniaturized. As one of them, the width of the gate electrode of the FET is narrowed, which causes a short channel effect. In order to suppress the occurrence of this short channel effect, it is required to make the source / drain region diffusion layer shallow.

As means for reducing the depth of the diffusion layer,
For example, a diffusion layer forming technique by low-acceleration ion implantation has been widely studied. The ion implantation method is B, BF ₂ , As, P
It is a method of forming a diffusion layer by ionizing a dopant such as, for example, implanting it into a Si substrate at a certain acceleration voltage, and activating it in a subsequent heat treatment.

In the low-acceleration ion implantation method, not only the acceleration voltage of the conventional ion implantation is lowered by the recent technological improvement but also the dispersion of incident ion energy is reduced and converged to form a shallower diffusion layer with good control. can do. Specifically, it has become possible to form a diffusion layer of 0.05 to 0.1 μm, and the low-acceleration ion implantation method is a very effective method as one means for forming a next-generation shallow diffusion layer. is there. Further, various methods for forming a stable diffusion layer with a junction depth xj of about 0.05 μm, such as a diffusion layer forming method of depositing a substrate material containing a dopant by CVD film formation, have been studied.

A conventional semiconductor device having a shallow diffusion layer using an ion implantation method, which is one of the shallow diffusion layer forming methods, and a method of manufacturing the same will be described below with reference to FIG.
First, a gate region 63 composed of a gate oxide film 63 (1), a gate electrode 63 (2) and a sidewall oxide film 63 (5) is formed on an element isolation region surrounded by a field oxide film 62 on a p-type Si substrate 61. To do. Then, in the exposed region of the Si substrate 61, B ⁺ which is ap ⁺ type impurity is formed by the low acceleration ion implantation method.
F ₂ with a dose amount of 5 × 10 ¹⁴ cm ^-2 and an acceleration voltage of 30 ke
Inject with V. Then, RTA is performed at 950 ° C. for 30 seconds to activate the impurities. In these steps, the shallow diffusion layer 6 having a surface concentration of 2 × 10 ²⁰ cm ⁻³ and a thickness of about 0.08 μm is formed.
4 is formed (FIG. 6A).

Next, the surface of the titanium (Ti) target is sputtered with argon (Ar) plasma to deposit a Ti film 67 with a thickness of 20 nm. Then, the surface of the Ti target is sputtered with plasma generated by a mixed gas of nitrogen and argon (N ₂ / Ar), and titanium nitride (Ti
While forming N), the TiN film 68 is deposited on the surface of the Ti film 67 (FIG. 6B).

Next, this multilayer film is annealed in a nitrogen atmosphere to form a titanium silicide (TiSi ₂ ) film 69.
Then, the unreacted Ti film 67 and TiN film 68 are removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide (FIG. 6C). In this way, the TiSi ₂ film 69 is formed in a self-aligned manner on the shallow diffusion layer 64 of 0.08 μm. Finally, an insulating film 65 is deposited, a contact hole is opened, and then an electrode plug 66 is formed (FIG. 6).
(D)). Through the above steps, the MOSFET is manufactured.

Incidentally, what is required to form a shallow diffusion layer junction is (1) controllability in the diffusion layer depth direction, (2) obtaining a more uniform and steep dopant impurity concentration profile, and (3) high concentration. The purpose is to reduce defects due to the distribution of the dopant. There are merits and demerits in various bonding forming methods for these requirements.

For example, in the ion implantation method, although the controllability of the mass production process is a fairly completed technology,
Since the dopant ions are injected into the Si substrate at a constant accelerating voltage, a tailing concentration profile due to channeling is formed. Further, this method is a process of cutting covalent bonds of Si of the Si substrate by the energy of incident ions to induce high-concentration defects in the substrate.
At the same time, the crystal defects are recovered by the heat treatment for activation, but they remain as point defects in the diffusion layer and the Si substrate.
As the dopant concentration becomes higher, the non-recoverable Si crystal defects generate dislocations.

In particular, in order to form the junction abruptly, the activation heat treatment tends to be shortened at a high temperature for a short time. However, this causes the re-diffusion distance of the dopant to be very short, and the distance between the crystal dislocation and the junction surface is further increased. Get closer. Recent detailed studies have revealed that these defects, when forming a salicide electrode on a diffusion layer junction, contribute to an increase in junction leakage through interaction with a diffusing metal.

On the other hand, the method of introducing the dopant impurities B, As, P, etc. forming the diffusion layer junction by thermal diffusion from an external solid diffusion source or gas diffusion source has few defects introduced into the substrate. It is possible to reduce an increase in generated current in the junction depletion layer. However, the steepness of the dopant impurity concentration profile has a problem, and it is also difficult to increase the peak concentration.

On the other hand, in the formation of the diffusion layer junction by the deposited Si formed by the CVD method, in order to form the diffusion layer junction in a desired pattern, S containing a dopant in a blanket shape is formed.
Either i is deposited and then patterned, or Si containing the dopant is deposited on the selectively exposed Si substrate, but a diffusion layer junction having a steep profile with a desired concentration is formed. It is formed. However,
When epitaxial Si is not used, the number of crystal defects is larger than that of a single crystal Si substrate, so that when a salicide electrode is formed directly on the electrode, an increase in roughness of the interface between the electrode and Si is likely to occur.

[0013]

As described above, Si has conventionally been used.
There are various methods for forming a high-concentration shallow diffusion layer on the surface of the substrate, but the ion implantation method forms a concentration profile that draws a tail due to channeling. There is a problem that it causes an increase in junction leak that is induced in the substrate.

Further, the method of introducing dopant impurities by thermal diffusion from an external solid diffusion source or gas diffusion source has a difficulty in the steepness of the dopant impurity concentration profile, and it has been difficult to increase the peak concentration. Further, in the formation of the diffusion layer junction by the deposited Si formed by the CVD method, there are many crystal defects, so that when the salicide electrode is formed directly on the electrode, there is a problem that the roughness of the interface between the electrode and Si is likely to increase.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a shallow high-concentration junction region having a steep impurity profile without causing damage due to ion implantation or the like. It is an object to provide a semiconductor device that can be formed and a manufacturing method thereof.

[0016]

[Means for Solving the Problems]

(Constitution) A skeleton of the present invention is a semiconductor having a high-concentration diffusion layer junction and an electrode formed by a concept different from the conventional method as a means for forming a shallow junction of about 0.05 μm to 0.1 μm. It is to realize the device.

That is, the present invention (claim 1) is a semiconductor device in which a pn junction is formed on a surface portion of a semiconductor substrate, and has a junction using a transition metal as a dopant on the surface portion of the semiconductor substrate. .

The present invention (claim 2) is a method of manufacturing a semiconductor device having a junction using a transition metal as a dopant on a surface portion of the semiconductor substrate, the step of depositing the transition metal on the surface of the semiconductor substrate. And a heat treatment step of performing a solid phase reaction at a temperature at which the semiconductor substrate and the transition metal do not reach a temperature for forming a compound and in a temperature range where mutual diffusion of the semiconductor substrate and the transition metal occurs. .

The present invention (claim 3) is a method of manufacturing a semiconductor device having a junction using a transition metal as a dopant on the surface portion of the semiconductor substrate, wherein the second portion is formed on the surface portion of the semiconductor substrate of the first conductivity type. Forming a conductive type first impurity diffusion layer, depositing a transition metal on the surface of the semiconductor substrate, at a temperature not reaching a temperature at which the semiconductor substrate and the transition metal form a compound, and Conducting solid-phase reaction in the temperature range where mutual diffusion of semiconductor substrate and transition metal occurs,
Forming a second impurity diffusion layer of the second conductivity type to a position deeper than the first impurity diffusion layer.

Here, preferred embodiments of the present invention include the following. (1) The junction should be the interdiffusion region between the semiconductor substrate and the transition metal. (2) The interdiffusion region must be a transition metal interdiffusion region into the semiconductor substrate crystal layer. (3) In the combination of a transition metal and a p-type semiconductor substrate, the transition metal forms a donor level in the semiconductor substrate. (4) In the combination of a transition metal and an n-type semiconductor substrate, the transition metal forms an acceptor level in the semiconductor substrate. (5) In the combination of the transition metal and the n-type semiconductor substrate, the transition metal has a diffusion rate in the elements constituting the semiconductor substrate,
It should be as fast as or faster than the diffusion rate of the elements that make up the semiconductor substrate in the transition metal. (6) In the combination of the transition metal and the p-type semiconductor substrate, the transition metal has a diffusion rate in the elements constituting the semiconductor substrate,
The rate of diffusion of the elements composing the semiconductor substrate in the transition metal should be the same or slower. (7) The element that constitutes the semiconductor is Si. (8) The transition metals in (6) are V, Co, Ni, Pd,
Must be Pt and Zr. (9) The transition metals in (7) are Ti, Hf, V, Ta,
Must be Mo, W, Fe, Pd, Zr. (10) The first impurity diffusion layer should be formed by ion implantation. (11) The first and second impurity diffusion layers should be the source / drain regions of the MOS transistor. (Function) According to the present invention, a transition metal such as Ti is used as a dopant, and a semiconductor substrate and a transition metal interdiffusion region,
In particular, by forming a junction in the interdiffusion region of the transition metal in the crystal layer of the semiconductor substrate, it is possible to realize a high-concentration and steep impurity profile even with a shallow junction near 0.05 μm. In this case, a junction with few dislocations can be formed without causing damage due to ion implantation and the like, and the roughness of the interface between the electrode and Si is not increased.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. (First Embodiment) FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG. 1A, an n-type Si substrate (semiconductor substrate) having a plane orientation (001) as a main surface
The surface of 11 is treated with a mixed solution of sulfuric acid and hydrogen peroxide to remove surface contamination of carbon (C) and metals other than Cu, and then Cu-based surface contamination is treated with a mixed solution of hydrochloric acid and hydrogen peroxide. To process. Next, the thin SiO ₂ film formed on the surface of the n-type Si substrate 11 is washed and stripped with dilute hydrofluoric acid, and then washed with running pure water having a dissolved oxygen concentration of 10 ppb or less.
At this time, the Si surface should be as clean and flat as possible. Subsequently, a Ti ₂ film (transition metal) 12 is deposited on the surface of the n-type Si substrate 11 by about 30 nm.

Next, this sample is subjected to a temperature not reaching the temperature at which silicide is formed at the Ti / Si interface, for example, about 4
Heat treatment was carried out for 30 minutes near 00 ° C., and as shown in FIG. 1B, a Ti diffusion region 13 was formed to form a p ⁺ / n junction. And as a result of evaluating the IV characteristic of this sample,
It was confirmed that the bonding characteristics were good.

The pn junction formed by this embodiment is
The following mechanism shows good bonding characteristics. That is, the profile of the transition metal forming the junction is T
A diffusion region 13 of high concentration Ti of 1 × 10 ²⁰ cm ⁻³ is formed in a region of about 100 nm or less from the i / Si interface to the Si substrate side. Furthermore, the junction is formed by utilizing the fact that the point defect density of Si in this area is particularly high in the layered area where Ti is diffused.

This is schematically shown in FIG. The formation temperature of the first phase of the Ti silicide compound due to the silicidation is 550 ° C., but in the temperature region where the mutual diffusion before the silicidation occurs at the Ti / Si interface occurs only for the time when the desired diffusion distance is obtained. When heat treatment is performed, Ti diffuses to a depth determined by the diffusion coefficient. In this region formed by the mutual diffusion reaction, Ti is distributed at a high concentration, and in Ti and Si, the diffusion rate of Si is relatively high,
Since Si is a diffusion species, Si is released to the Ti film side to form a vacancy defect region of Si. The high concentration Ti and the vacancy defect region thus formed act as ap ⁺ region. (Second Embodiment) FIG. 3 is a sectional view showing a manufacturing process of a MOSFET according to a second embodiment of the present invention.

First, as shown in FIG. 3A, an 800 nm field oxide film 32 is formed by an embedding method on an n-type Si substrate 31 having a plane orientation (001) as a main surface. 10n in the element formation region surrounded by the oxide film 32
m gate oxide film 33 (1), 150 nm doped polycrystalline layer 33 (2), 150 nm tungsten silicide (WS)
After the i ₂ ) film 33 (3) and the SiN film 33 (4) are sequentially deposited, they are processed into a gate shape by etching to form a laminated film.

In this state, BF ₂ with a dose amount of 5 × 10 ¹³ cm ^-2 is ion-implanted at an acceleration voltage of 15 keV, LDD regions (p ⁺ regions) 34 (1) are preliminarily formed on both sides of the gate, and SiN is further formed. After depositing the film 33 (5) to a thickness of 150 nm, it is processed by anisotropic etching to leave the SiN film 33 (5) only on the side wall of the gate. Thereby, the gate region 33 is formed.

Then, the exposed surface of the Si substrate 31 is treated with a mixed solution of sulfuric acid and hydrogen peroxide to remove surface contamination of carbon (C) and metals other than Cu.
Cu-based surface contamination is treated with a mixed solution of hydrochloric acid and hydrogen peroxide. Subsequently, the thin SiO ₂ film formed on the surface of the n-type Si substrate 31 was washed and stripped with diluted hydrofluoric acid, and the dissolved oxygen concentration was reduced to 1
Wash with running water with ultrapure water of 0 ppb or less. Si at this time
The surface should be as clean and flat as possible.

Next, as shown in FIG. 3B, the Ti film 37 is selectively deposited by the CVD method only on the exposed Si surface at a temperature below the temperature at which silicide is formed at the Ti / Si interface. Then, this is heat-treated at about 460 ° C. for 30 minutes to form the P ⁺ layer 34.

Then, as shown in FIG. 3 (c), Ti /
An interlayer insulating film 35 such as SiO ₂ is deposited on the entire surface of the substrate at a temperature of 400 ° C. or lower, which is lower than the temperature at which the Si interface is heat-treated, and then a contact is opened to form a plug 36.

I-of the MOSFET manufactured by the above method
As a result of evaluating the V characteristic, a good p ⁺ / n junction was obtained. As a result of confirming the shape and profile of this junction by cross-sectional TEM observation and EDX analysis, it was confirmed that Ti was formed into a uniform layered region in a region of about 50 nm from immediately below the Ti / Si interface. Furthermore,
As a result of examining this with EDX, about 1 × 10 ²⁰ cm ⁻³ of Ti
The concentration was confirmed.

The above-mentioned concept of the junction forming method is similar to that of the first embodiment, but the temperature is below the temperature at which Ti silicide is formed at the Ti / Si interface, and the interdiffusion of Ti and Si occurs most significantly. Reaction in the temperature range
A region where Ti is diffused in a high concentration just below the Si interface and Si is T
The p ⁺ / n junction is formed by mixing point defect regions in which Si is released by diffusing to the i film side.

In the case of the conventional method of forming a junction, the junction is first formed, and salicide is formed thereon in order to reduce the diffusion layer sheet resistance.
At the same time as consuming a high concentration of dopant at the interface in the area,
In particular, dopants such as boron are sucked into the salicide film, and the salicide / Si interface concentration decreases. As a result, the contact resistance is increased.

On the other hand, in the method and structure of this embodiment,
Since the dopant concentration at the metal / Si interface is the highest, it is not necessary to consider the above problem. Further, since the junction is basically formed by thermal diffusion, dislocation like ion implantation does not occur. Therefore, the contact resistance can be reduced and a dislocation-free junction can be formed. (Third Embodiment) FIG. 4 is a sectional view showing a manufacturing process of a MOSFET according to a third embodiment of the present invention.

First, as shown in FIG. 4A, an 800 nm field oxide film 42 is formed by an embedding method on an n-type Si substrate 41 having a plane orientation (001) as a main surface. In the element formation region surrounded by the oxide film 42, 10 n
m gate oxide film 43 (1), 150 nm doped polycrystalline layer 43 (2), 150 nm tungsten silicide (WS)
After the i ₂ ) film 43 (3) and the SiN film 43 (4) are sequentially deposited, they are processed into a gate shape by etching to form a laminated film.

In this state, BF ₂ with a dose amount of 5 × 10 ¹³ cm ^-2 is ion-implanted at an acceleration voltage of 15 keV, LDD regions are formed in advance on both sides of the gate, and the SiN film 43 (5) is formed.
Is deposited to a thickness of 150 nm and then processed by anisotropic etching to leave the SiN film 43 (5) on the side wall of the gate. Thereby, the gate region 43 is formed.

Next, the surface of the Si substrate 41 is 3 nm thick.
Thin thermal oxide film is formed, and a 0.05 μm junction is formed in that region by low-acceleration ion implantation.
Activated by RTA for seconds to form p ⁺ layer 44 (1). After that, the 3 nm thermal oxide film used as the ion implantation buffer is treated with a mixed solution of sulfuric acid and hydrogen peroxide, and stripped with HF.

Then, the exposed surface of the Si substrate 41 is treated again with a mixed solution of sulfuric acid and hydrogen peroxide to remove surface contamination of carbon (C) and metals other than Cu.
Cu-based surface contamination is treated with a mixed solution of hydrochloric acid and hydrogen peroxide. Subsequently, the thin SiO ₂ film formed on the surface of the n-type Si substrate 41 is removed by washing with diluted hydrofluoric acid, and then washed with running pure water having a dissolved oxygen concentration of 10 ppb or less. S at this time
It is desirable that the surface i be as clean and flat as possible.

Next, as shown in FIG. 4B, the Ti film 47 is deposited only on the exposed Si surface by the selective CVD method at a temperature not higher than the temperature at which silicide is formed at the Ti / Si interface. Then, the p ⁺ layer 44 was formed by heat-treating this at about 460 ° C. for 30 minutes.

Then, as shown in FIG. 4 (c), Ti /
An insulating film 45 is deposited on the entire surface of the substrate at a temperature of 400 ° C. or lower, which is lower than the temperature at which the Si interface is heat-treated, and then a contact is opened to form a plug 46.

As a result of evaluating the IV characteristics of the device manufactured by the above method, a good p ⁺ / n junction with a reduced junction leak current was obtained as compared with the junction manufactured by ordinary ion implantation. It was This is after forming the p ⁺ / n junction in conventional ion implantation, p ⁺ bonding surface ion implantation defects formed by thermal diffusion, extends toward the substrate than the existing areas of dislocation, a new p ⁺ junction surface It is considered that there is also an effect of forming defects and acting as an acceptor in the substrate and compensating for defects in the p ⁺ junction.

FIG. 5 shows the heat treatment temperature dependency of the junction leak reduction at the applied voltage of 1 V before the silicide formation at the Ti / Si interface. The effect of reducing the junction leak can be achieved relatively well in the temperature range of 300 to 600 ° C.,
Ti / Si interdiffusion occurs before silicide formation 4
At around 60 ° C., a particularly remarkable reduction in junction leak can be achieved. (Modification) The present invention is not limited to the above-described embodiments. The Ti used in the embodiment forms an acceptor in the Si substrate, and has a high Si diffusion rate (so-called Si is a diffusion species) in the interdiffusion at the transition metal / Si interface, or the transition metal and Si have a mutual diffusion rate. This is an example in which a junction is formed by using transition metals of the same degree, and is a substance that can achieve the most desirable effects of the present invention. However, it is not always necessary to have the characteristics of the ion polarity and diffusion rate in the substrate at the same time.

Examples of substances in which Si is a diffusive species relative to the transition metal or whose diffusive speeds are similar are, for example, Ti, V, Mo, Pd, Hf, Ta, W, Fe and Z.
r, etc. Furthermore, the metal whose transition metal is a diffusion species relative to Si is, for example, V, Co, Ni, Pd, P.
t and Zr. The positive / negative polarity state of the Si substrate changes depending on the reaction process, the forming method, and the state of the substrate.

If the diffusion coefficient of the transition metal in the Si substrate is low, it can be controlled to be shallow thermally. In addition, since heat treatment is performed using the above material at a temperature that does not reach the temperature at which transition metal silicide is formed at the transition metal / Si interface,
It is desirable to use a process below that temperature in subsequent steps. Furthermore, it is desirable that the Si surface before depositing the transition metal be as clean and flat as possible. For example, it is possible to achieve the purpose more effectively by performing the process from the Si surface treatment to the deposition of the transition metal in a controlled atmosphere that is not exposed to the atmosphere. Surface orientation is (11
1) It is still effective if it is a substrate.

Further, in the embodiment, the transition metal on the junction used for forming the junction is used as it is as an electrode. However, after forming the shallow junction, the transition metal is peeled off by a chemical solution, and the formed p ⁺ / n junction is formed. It goes without saying that it is also possible to form an electrode made of another metal on it.

In the embodiment, the example of p ⁺ / n has been described, but it goes without saying that n ⁺ / p can be used depending on the combination of metals. In addition, various modifications can be made without departing from the scope of the present invention.

[0047]

As described above in detail, according to the present invention, not only a refractory transition metal forming a metal silicide is used as a dopant, but also a shallow high-concentration junction produced by mutual diffusion during solid-phase reaction. The region can be used as a new junction element. As a result, a thermally controlled shallow junction can be formed, and a junction without high-concentration defects or dislocations caused by high-energy injection such as ion implantation can be formed. Further, depending on the assembly of the process, bonding and simultaneous formation of electrodes are possible.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a diagram schematically showing a bonding profile in a Si substrate according to the first embodiment.

FIG. 3 is a cross-sectional view showing the manufacturing process of the MOSFET according to the second embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing process of the MOSFET according to the third embodiment.

FIG. 5 is a diagram showing the heat treatment temperature dependence of the junction leakage reduction effect in the third embodiment.

FIG. 6 is a cross-sectional view showing a manufacturing process of a MOSFET according to a conventional technique.

[Explanation of symbols]

11, 31, 41 ... Silicon substrate 12, 37, 47 ... Ti film (high melting point transition metal) 13, 34, 44 ... P ⁺ layer (diffusion bonding region) 32, 42 ... Field oxide film 33, 43 ... Gate region 35 , 45 ... Interlayer insulating film 36, 46 ... Plug

Claims (3)

[Claims] 1. A semiconductor device having a junction using a transition metal as a dopant on a surface portion of a semiconductor substrate. 2. A method of manufacturing a semiconductor device having a junction using a transition metal as a dopant on a surface portion of a semiconductor substrate, the step of depositing a transition metal on the surface of the semiconductor substrate,
A semiconductor device comprising: a heat treatment step of performing a solid-phase reaction at a temperature at which the semiconductor substrate and the transition metal do not reach a temperature for forming a compound, and in a temperature region where mutual diffusion of the semiconductor substrate and the transition metal occurs. Manufacturing method. 3. A step of forming a first impurity diffusion layer of a second conductivity type on a surface portion of a semiconductor substrate of a first conductivity type, a step of depositing a transition metal on the surface of the semiconductor substrate, and the semiconductor. A solid-phase reaction is performed at a temperature at which the substrate and the transition metal do not reach a temperature for forming a compound, and in a temperature range where mutual diffusion of the semiconductor substrate and the transition metal occurs, and is equal to or more than the first impurity diffusion layer. Second conductivity type to the deep position
And a step of forming an impurity diffusion layer, the method for manufacturing a semiconductor device.