JP3932445B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device including a step of activating an impurity introduced into a semiconductor layer with an energy beam, and in particular, manufacturing a top gate type thin film transistor (TFT) on a low heat resistant substrate. The present invention relates to a method for manufacturing a semiconductor device suitable for use.
[0002]
[Prior art]
In recent years, a polycrystalline silicon (Si) TFT formed on a glass substrate has been used as a switching function element in a pixel and a driver of a liquid crystal display device, and other than that, development as a semiconductor memory is being promoted. . In a semiconductor device such as TFT, a glass substrate, a silicon substrate, or the like is conventionally used as the substrate because the substrate is required to be lightweight, impact resistant, and flexible so as not to be damaged even if a certain amount of stress is applied. I came. Among these, the glass substrate has low heat resistance (heat resistant temperature of 400 ° C.), and by locally heating using an energy beam such as a laser or an infrared lamp, the substrate temperature can be kept relatively low and heat treatment of the semiconductor layer and the like can be performed. It was done.
[0003]
Recently, plastic substrates that are lighter and more resistant to impact than these substrates have been used. However, the heat resistance temperature of a plastic substrate such as polyethylene terephthalate (PET) is about 200 ° C., which is lower than that of a glass substrate.
[0004]
[Problems to be solved by the invention]
For this reason, when a plastic substrate is used, all manufacturing steps of the semiconductor device need to be performed at a temperature of 200 ° C. or lower. In other words, in addition to heat treatment performed for the purpose of crystallization and impurity activation, a thin film of silicon dioxide (SiO ₂ ) film used for a gate insulating film, an interlayer insulating film, etc., generally performed at a temperature higher than 200 ° C. The temperature condition in the formation is 200 ° C. or less.
[0005]
However, in general, it is impossible to activate the impurities implanted into the semiconductor layer at a temperature of 200 ° C. or lower. In addition, when the SiO ₂ film is formed at a temperature of 200 ° C. or less, the resulting SiO ₂ film includes a large amount of defects, and there are many defects at the interface with the semiconductor layer. The method of removing defects by heat treatment after forming this SiO ₂ film is required to be at least 400 ° C. and could not be applied to a plastic substrate.
[0006]
Even if the surface of the element is locally heated by using an energy beam for the above-described heat treatment, the energy beam instantaneously heats at a high temperature. In some cases, a plastic substrate having a very low heat resistance may be damaged by the heat of the irradiated beam.
[0007]
The present invention has been made in view of such problems, and an object thereof is to provide a method of manufacturing a semiconductor device that can manufacture a semiconductor device having good characteristics on a low heat resistant substrate.
[0008]
[Means for Solving the Problems]
A method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor layer on a substrate, a step of selectively forming a metal layer on the semiconductor layer via an insulating layer, and a semiconductor using the metal layer as a mask. A step of selectively introducing impurities into the layer, a step of forming an energy absorption layer by depositing aluminum nitride (AlN) so as to cover the insulating layer and the metal layer, and a pulse laser beam from the side of the energy absorption layer And activating the impurities introduced into the semiconductor layer.
[0009]
In the method for manufacturing a semiconductor device according to the present invention, the irradiated energy beam is once absorbed by the energy absorption layer, and indirectly through the energy absorption layer without damaging a low heat resistant substrate such as plastic. The underlying metal layer, insulating layer and semiconductor layer are heated. Thereby, activation of impurities in the semiconductor layer and removal of defects in the insulating layer are performed.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0011]
[First Embodiment]
FIG. 1 shows a cross-sectional configuration of a top gate type TFT according to the first embodiment of the present invention. In this TFT, for example, a polycrystalline silicon (Si) layer 13 including a channel region 13 a, a source region 13 b, and a drain region 13 c is provided on a substrate 10 via a buffer layer 11. The source region 13b and the drain region 13c are formed to be separated from each other and adjacent to the channel region 13a. A gate electrode 15 is formed on the channel region 13a via an insulating layer 14, and a source electrode 17 is electrically connected to the source region 13b, and a drain electrode 18 is electrically connected to the drain region 13c.
[0012]
A method for manufacturing such a TFT will be described below with reference to FIGS.
[0013]
First, as shown in FIG. 2, for example, a buffer layer 11 for protecting the substrate 10 from heat by a heat insulating effect is formed on the substrate 10 having a heat resistant temperature of about 200 ° C. or lower. Form with.
[0014]
As the substrate 10, for example, an organic material is used. Specifically, polyethylene sulfone (PES), polyethylene terephthalate (PET), polyesters such as polyethylene naphthalate or polycarbonate, polyolefins such as polypropylene, polyphenylin sulfides such as polyphenylin sulfide, polyamides, aromatics Polymer materials such as group polyamides, polyether ketones or polyimides are preferable, and any one or more of these may be included. The thickness of the substrate 10 is, for example, 200 μm, but a thinner one is more preferable in order to give flexibility to the TFT and reduce the size. In addition, the softening point of such an organic material is 250 ° C. or less, and the heat resistance temperatures of PES and PET are about 200 ° C. and 100 ° C., respectively. As the buffer layer 11, for example, silicon dioxide (SiO ₂ ) is used. In addition, silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), or a laminated film thereof can be used. The buffer layer 11 has a thickness of, for example, 300 nm.
[0015]
Next, an amorphous silicon layer 12 is formed on the buffer layer 11 at a temperature lower than the heat resistant temperature of the substrate 10. The amorphous silicon layer 12 has a film thickness of 30 nm, for example. For forming the buffer layer 11 and the amorphous silicon layer 12, for example, a reactive sputtering method, a plasma enhanced chemical vapor deposition (PECVD) method, a low pressure CVD (LPCVD) method, a vapor deposition method, or the like. Can be used. Here, the amorphous silicon layer 12 is formed using silicon (Si), but one of silicon germanium (SiGe), germanium (Ge), and silicon carbide (SiC) including Si is used. The above semiconductors can be used.
[0016]
Next, the amorphous silicon layer 12 is heated by irradiation with, for example, a pulsed laser beam. As a result, the amorphous silicon layer 12 is crystallized to become a polycrystalline silicon layer 13 as shown in FIG. As the pulse laser beam, it is preferable to use a laser having a wavelength that is easily absorbed by the amorphous silicon layer 12, that is, an ultraviolet wavelength. Specifically, the third harmonic (355 nm) of an XeCl excimer laser (wavelength 308 nm), a KrF excimer laser (wavelength 248 nm), an ArF excimer laser (wavelength 193 nm), an XeF excimer laser (wavelength 351 nm), or an Nd: YAG laser. , Nd: YAG laser fourth harmonic (266 nm), etc., and the conditions such as the wavelength, energy density, pulse width and number of irradiation pulses of this laser depend on the layer thickness of the amorphous silicon layer 12 and the like. It is selected as appropriate. However, in order to sufficiently heat the amorphous silicon layer 12 and obtain a polycrystalline silicon layer 13 with good crystallinity, it is preferable that the pulse width of the beam be in the range of 100 ps to 300 ns.
[0017]
The irradiated pulse laser beam is almost completely absorbed by the amorphous silicon layer 12. Therefore, the substrate 10 is hardly heated. Here, the polycrystalline silicon layer 13 corresponds to a specific example of “semiconductor layer” of the present invention. Note that the “semiconductor layer” does not necessarily have to be polycrystalline as a whole, and may be formed to have a crystalline region that is partially crystalline, for example.
[0018]
Further, the polycrystalline silicon layer 13 is patterned into a predetermined shape, for example, an island shape by lithography and etching, for example.
[0019]
Next, as shown in FIG. 4, so as to cover the patterned polycrystalline silicon layer 13, the insulating layer 14 is formed on the insulating layer 14 at a temperature lower than the heat resistant temperature of the substrate 10 by using, for example, SiO ₂ or SiN _x. Form. The insulating layer 14 can be formed by, for example, a reactive sputtering method, a PECVD method, a vapor deposition method, a JVD (Jet Vapor Deposition) method, or the like. In addition, the surface of the polycrystalline silicon layer 13 is subjected to plasma oxidation or plasma nitridation. Can also be obtained. The thickness of the insulating layer 14 is 50 nm, for example.
[0020]
Next, the gate electrode 15 is formed on the insulating layer 14 by sputtering or vapor deposition using, for example, aluminum (Al). As the gate electrode 15, in addition to Al, copper (Cu), molybdenum (Mo), tantalum (Ta), platinum (Pt), or ITO (indium and tin oxide) can be used. The thickness of the gate electrode 15 is 240 nm, for example. Here, the gate electrode 15 corresponds to a specific example of the “metal layer” of the present invention.
[0021]
Subsequently, impurities are introduced into the polycrystalline silicon layer 13 at a temperature not higher than the heat resistance temperature of the substrate 10 by using, for example, an ion implantation method with the gate electrode 15 as a mask. As an impurity, for example, phosphorus (P) is used as an n-type impurity in the case of an n-channel TFT, and boron (B) is used as a p-type impurity in the case of a p-channel TFT. Thereby, the source region 13b and the drain region 13c which are impurity implantation regions and the channel region 13a which is a non-implantation region therebetween are formed in a self-aligned manner with respect to the gate electrode 15 (see FIG. 5).
[0022]
Further, as shown in FIG. 5, the energy absorption layer 16 is formed at a temperature lower than the heat resistant temperature of the substrate 10 so as to cover the outermost surface of the substrate 10 from above the gate electrode 15 and the insulating layer 14. As the energy absorbing layer 16, a material having a band gap equal to or lower than the energy of the energy beam is used in order to absorb the irradiation energy of the energy beam well as described later. Specifically, carbon (C), silicon (Si), germanium (Ge), silicon carbide (SiC), silicon nitride (SiN), aluminum nitride (AlN), silicon germanium (SiGe), and molybdenum which is a transition metal (Mo), tantalum (Ta), tungsten (W), nickel (Ni), chromium (Cr) and the like can be used, and any one or more of these can be used. When the energy absorption layer 16 is removed after the energy beam irradiation, the energy absorption layer 16 further has an etching selectivity with respect to the gate electrode 15. For example, if the gate electrode 15 is Al, it is preferable to use amorphous silicon for the energy absorption layer 16. The thickness of the energy absorption layer 16 is, for example, 30 nm.
[0023]
Next, the energy absorbing layer 16 is heated by irradiating an ultraviolet pulse laser beam from, for example, an excimer laser from the energy absorbing layer 16 side. As this pulse laser beam, the same laser beam as that applied to the amorphous silicon layer 12 can be used. The irradiated laser beam is almost completely absorbed by the energy absorption layer 16, and heat treatment is indirectly performed by heat emitted from the energy absorption layer 16. The energy once absorbed in the energy absorption layer 16 is uniformly emitted from the entire layer surface of the energy absorption layer 16 and propagates to the gate electrode 15, the insulating layer 14 and the polycrystalline silicon layer 13. The gate electrode 15 has good thermal conductivity, and heats the surroundings, particularly the insulating layer 14 immediately below the gate electrode 15. Thus, the layers below the insulating layer 14 are heated relatively uniformly and slowly, and the substrate 10 is hardly heated.
[0024]
By this heat treatment, impurities in the polycrystalline silicon layer 13 are activated and the gate electrode 15 is heated, whereby the insulating layer 14 and the interface between the insulating layer 14 and the polycrystalline silicon layer 13 are heated, and the insulating layer Defects existing inside 14 and at the interface between this and polycrystalline silicon layer 13 are removed. Here, it is desirable that the impurities of the polycrystalline silicon layer 13 are activated to an activation rate of 20% or more. Incidentally, when the insulating layer 14 is directly irradiated with a laser beam as in the prior art, the layer below the insulating layer 14 cannot be sufficiently heated if the irradiation amount is decreased to prevent the temperature of the substrate 10 from rising. Since the beam energy is locally released, a temperature distribution in the layer surface direction occurs in the layers below the insulating layer 14, and in this case, for example, there is a possibility that a part of the polycrystalline silicon layer 13 or the insulating layer 14 is not sufficiently heat-treated. It was.
[0025]
Next, as shown in FIG. 1, the energy absorption layer 16 is removed. Further, the source electrode 17 and the drain electrode 18 are formed on the source region 13b and the drain region 13c. The source electrode 17 and the drain electrode 18 may be formed by a known method such as a method of using Al, for example, forming a film by sputtering, vapor deposition or the like and then patterning by lithography and etching. Note that the surface of the TFT thus formed may be covered with an oxide such as SiO ₂ or SiN _x to form a protective film.
[0026]
As described above, according to the present embodiment, since the pulse laser beam is irradiated after the energy absorption layer 16 is provided on the substrate 10, the energy that is instantaneously emitted locally like the laser beam. Is absorbed by the energy absorption layer 16 and indirectly emitted from the entire layer surface of the energy absorption layer 16, so that the substrate 10 is not substantially heated, but the gate electrode 15 below the energy absorption layer 16. The insulating layer 14 and the polycrystalline silicon layer 13 are heated uniformly and slowly. Therefore, while preventing damage to the substrate 10 that occurs when the laser beam is directly irradiated, the activation of impurities in the polycrystalline silicon layer 13 and the removal of defects occurring in and around the insulating layer 14 are sufficiently and simultaneously performed. be able to.
[0027]
Further, according to the present embodiment, since the impurity is ion-implanted into the polycrystalline silicon layer 13 using the gate electrode 15 as a mask, the channel region 13a and the source region are formed in one step without forming a mask separately. 13b and the drain region 13c can be formed in a self-aligned manner.
[0028]
[Second Embodiment]
FIG. 6 shows a cross-sectional configuration of a top-gate TFT according to the second embodiment of the present invention. This TFT has the same configuration as that of the first embodiment except that the gate electrode 15a is formed between the insulating layers 14a and 14b. Here, the insulating layers 14a and 14b and the gate electrodes 15a and 15b correspond to the insulating layer 14 and the gate electrode 15 of the first embodiment. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
[0029]
A method for manufacturing such a TFT will be described below with reference to FIGS.
[0030]
First, similarly to the first embodiment, a buffer layer 11 and an amorphous silicon layer 12 are formed in this order on a substrate 10 at a temperature not higher than the heat resistance temperature of the substrate 10, and the amorphous silicon layer 12 is pulsed. Heat by laser beam. As a result, the amorphous silicon layer 12 is crystallized to become a polycrystalline silicon layer 13. As the pulse laser beam, for example, the same one as in the first embodiment such as an excimer laser can be used. The irradiated pulse laser beam is almost completely absorbed by the amorphous silicon layer 12, and the substrate 10 is hardly heated.
[0031]
Next, as shown in FIG. 7, an insulating layer 14a is formed on the polycrystalline silicon layer 13 at a temperature lower than the heat resistant temperature of the substrate 10, and a gate electrode 15a is formed thereon. Next, selective etching is performed by ECR-RIE (Electron Cyclotron Resonance Reactive Ion Etching) in a mixed gas of CF ₄ and H _{2 using} the gate electrode 15a as a mask. Thereby, the insulating layer 14a on the polycrystalline silicon layer 13 which becomes the source region 13b and the drain region 13c is removed in a self-aligning manner.
[0032]
Further, impurities are introduced into the polycrystalline silicon layer 13 by plasma doping using the gate electrode 15a as a mask. The plasma doping is performed, for example, by exposing the substrate 10 to a glow discharge plasma of a mixed gas of PH ₃ and He at a temperature of 110 ° C. and adsorbing phosphorus (P) on the surface of the polycrystalline silicon layer 13. As the impurity, in addition to phosphorus (P), which is an n-type impurity, for example, boron (B), which is a p-type impurity, can be used. In this case, the substrate 10 is exposed to B ₂ H ₆ plasma and boron (B ). Since the adsorbed impurities are diffused only near the surface (˜1 nm) of the polycrystalline silicon layer 13 as they are, they are sufficiently diffused and doped into the polycrystalline silicon layer 13 in the following laser irradiation.
[0033]
Next, as shown in FIG. 8, the insulating layer 14 b and the energy absorption layer 16 are sequentially formed on the polycrystalline silicon layer 13 and the gate electrode 15 at a temperature lower than the heat resistance temperature of the substrate 10.
[0034]
Next, as shown in FIG. 9, the energy absorbing layer 16 is heated by irradiating, for example, an ultraviolet pulse laser beam from an excimer laser from the energy absorbing layer 16 side. The energy absorption layer 16 absorbs the laser beam almost completely to dissipate heat, and this heat diffuses and activates impurities (here phosphorus (P)) in the polycrystalline silicon layer 13 and is heated. The insulating layers 14a and 14b and the interface between the insulating layers 14a and 14b and the polycrystalline silicon layer 13 are heat-treated through the gate electrode 15a. Thus, the heat treatment is indirectly performed through the energy absorption layer 16, and the substrate 10 is hardly heated. It is desirable that the impurities in the polycrystalline silicon layer 13 are activated to an activation rate of 20% or more. Thereby, the source region 13b and the drain region 13c which are impurity implantation regions and the channel region 13a which is a non-implantation region therebetween are formed in a self-aligned manner with respect to the gate electrode 15a. At the same time, defects existing in the insulating layers 14a and 14b and at the interface between the insulating layers 14a and 14b and the polycrystalline silicon layer 13 are removed.
[0035]
Next, as shown in FIG. 6, the energy absorption layer 16 is removed. Further, the gate electrode 15b, the source electrode 17 and the drain electrode 18 are formed on the channel region 13a (more precisely, the gate electrode 15a), the source region 13b and the drain region 13c, respectively.
[0036]
As described above, also in the present embodiment, since the pulse laser beam is irradiated after the energy absorption layer 16 is provided on the substrate 10, it is emitted locally as in the first embodiment. The energy of the laser beam is once absorbed in the energy absorption layer 16 and indirectly emitted from the entire layer surface of the energy absorption layer 16, whereby the lower layer of the energy absorption layer 16 is uniformly and slowly heated, but the substrate 10. Is not substantially heated. Therefore, while preventing damage to the substrate 10 that occurs when the laser beam is directly irradiated, the activation of impurities in the polycrystalline silicon layer 13 and the removal of defects occurring in and around the insulating layer 14 are sufficiently and simultaneously performed. be able to.
[0037]
Also in the present embodiment, as in the first embodiment, the polycrystalline silicon layer 13 is plasma-doped with the gate electrode 15 as a mask, so that the channel region 13a can be formed without forming a mask separately. The source region 13b and the drain region 13c can be formed in a self-aligned manner.
[0038]
The present invention has been described with reference to the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, a manufacturing method was specifically described for a TFT as a semiconductor device, but the present invention forms a metal layer over an insulating layer on a semiconductor layer formed on a substrate, A semiconductor having another structure that can be manufactured by injecting an impurity into a semiconductor layer using a metal layer as a mask, and further forming an energy absorption layer on the entire surface and irradiating an energy beam from above to activate the impurity. The apparatus can also be widely applied.
[0039]
【The invention's effect】
As described above, according to the method of manufacturing a semiconductor device of the present invention, an energy absorption layer is formed by depositing aluminum nitride (AlN) so as to cover the insulating layer and the metal layer provided on the semiconductor layer. Since the pulse laser beam is irradiated from the side of the energy absorption layer, the irradiated energy heats the lower metal layer, insulating layer and semiconductor layer through the energy absorption layer, but the substrate is not substantially heated. . Therefore, it is possible to prevent the substrate from being damaged by direct irradiation of the energy beam toward the substrate. In addition, according to such a method, the insulating layer and the semiconductor layer are sufficiently heated, and at the same time as the activation of the impurities in the semiconductor layer, the insulating layer and the defects existing around it are effectively removed, A semiconductor device with favorable characteristics can be obtained. Therefore, a low heat-resistant substrate made of, for example, an organic material can be used as the substrate, and a semiconductor device that is lightweight, resistant to impact, and has excellent characteristics can be manufactured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration of a TFT according to a first embodiment of the invention.
2 is a cross-sectional view for explaining a manufacturing step of the TFT shown in FIG. 1. FIG.
3 is a cross-sectional view for explaining a manufacturing step subsequent to the step of FIG. 2. FIG.
4 is a cross-sectional view for explaining a manufacturing step subsequent to the step of FIG. 3. FIG.
5 is a cross-sectional view for explaining a manufacturing step subsequent to the step of FIG. 4. FIG.
FIG. 6 is a cross-sectional view illustrating a configuration of a TFT according to a second embodiment of the invention.
7 is a cross-sectional view for explaining a manufacturing step of the TFT shown in FIG. 6. FIG.
8 is a cross-sectional view for explaining a manufacturing step subsequent to the step of FIG. 7. FIG.
9 is a cross-sectional view for explaining a manufacturing step subsequent to the step of FIG. 8. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Substrate, 12 ... Amorphous silicon layer, 13 ... Polycrystalline silicon layer, 13a ... Channel region, 13b ... Source region, 13c ... Drain region, 14 ... Insulating film, 15 ... Gate electrode, 16 ... Energy absorption layer, 17 ... Source electrode, 18 ... Drain electrode

Claims (6)

Forming a semiconductor layer on the substrate;
Selectively forming a metal layer on the semiconductor layer via an insulating layer;
Selectively introducing impurities into the semiconductor layer using the metal layer as a mask;
Forming an energy absorption layer by depositing aluminum nitride (AlN) so as to cover the insulating layer and the metal layer;
Irradiating a pulse laser beam from the energy absorption layer side and activating impurities introduced into the semiconductor layer. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate has a softening point of 250 ° C. or lower. The method for manufacturing a semiconductor device according to claim 2, wherein the substrate is formed of an organic polymer material. 2. The semiconductor device according to claim 1, wherein the semiconductor layer is formed of one or more semiconductors selected from silicon (Si), silicon germanium (SiGe), germanium (Ge), and silicon carbide (SiC). Production method. The method for manufacturing a semiconductor device according to claim 1, wherein an activation rate of the impurity is set to 20% or more in the impurity region of the semiconductor layer. The method of manufacturing a semiconductor device according to claim 1, characterized in that said pulsed laser beam within a pulse width of less 300ns or more 100ps of.

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