JP2002057164A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to manufacture a semiconductor device having favorable characteristics on a substrate having a low heat resistance. SOLUTION: A semiconductor device is constituted in a structure that a polycrystalline silicon layer 13 is formed on a substrate 10. An insulating layer 14 and a gate electrode 15 are formed on the layer 13 and impurities are introduced in the layer 13 using this gate electrode 15 as a mask to form a channel region 13a, a source region 13b and a drain region 13c in the layer 13 in a self-alignment manner. Then an energy absorption layer 16 is formed in such a way as to cover the entire surface of the substrate 10 to irradiate a pulsed laser beam from the side of the layer 16. The layer 16 absorbs the energy of the laser beam almost completely and diverges heat, whereby a heat treatment of the lower layer under the layer 16 is indirectly performed. That is, an activation of the impurities and the removal of a defect in the layer 14 are simultaneously performed without damaging the substrate 10 due to the heat.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including a step of activating an impurity introduced into a semiconductor layer by an energy beam. Film Tran
The present invention relates to a method for manufacturing a semiconductor device suitable for manufacturing a TFT (Sistor; TFT).

[0002]

2. Description of the Related Art In recent years, a polycrystalline silicon (Si) TFT formed on a glass substrate has been used as a switching function element in a pixel and a driver of a liquid crystal display device, and has been developed as a semiconductor memory. Is being promoted. In a semiconductor device such as a TFT, a substrate such as a glass substrate or a silicon substrate is conventionally used because the substrate is required to have light weight, impact resistance, and flexibility that does not break even when a small amount of stress is applied. Have been. Among them, the glass substrate has low heat resistance (heat resistance temperature 400
° C), and a local heating using an energy beam such as a laser or an infrared lamp, the heat treatment of the semiconductor layer or the like is performed while the substrate temperature is kept relatively low.

Recently, plastic substrates which are lighter and more resistant to impact than these substrates have been used. However, polyethylene terephthalate (polyethy
The heat-resistant temperature of a plastic substrate such as lene terephthalate (PET) is about 200 ° C., which is even lower than that of a glass substrate.

[0004]

Therefore, when a plastic substrate is used, all the manufacturing steps of the semiconductor device must be performed at a temperature of 200 ° C. or less. That is, in addition to the heat treatment performed for the purpose of crystallization, activation of impurities, etc., in general, a silicon dioxide (SiO ₂ ) film used for a gate insulating film, an interlayer insulating film, or the like generally has a thickness of 200 nm.
The temperature condition in forming a thin film performed at a temperature higher than
It will be below 00 ° C.

However, generally, it is impossible to activate impurities implanted in a semiconductor layer at a temperature of 200 ° C. or lower. Further, when the SiO ₂ film is formed at a temperature of 200 ° C. or less, the obtained SiO ₂ film contains a large number of defects,
Many defects also exist at the interface with the semiconductor layer. Note that the method of removing defects by heat treatment after forming the SiO ₂ film requires that the temperature be at least 400 ° C. or more and cannot be applied to a plastic substrate.

Even if the surface of the device is locally heated by using an energy beam for the above-mentioned heat treatment, the energy beam is heated to a high temperature instantaneously. As a result, the heat of the irradiated beam may damage a plastic substrate having extremely low heat resistance.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device having good characteristics on a substrate having low heat resistance. It is in.

[0008]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a semiconductor layer on a substrate and a step of selectively forming a metal layer on the semiconductor layer via an insulating layer. And a step of selectively introducing impurities into the semiconductor layer using the metal layer as a mask, a step of forming an energy absorbing layer so as to cover the insulating layer and the metal layer, and irradiating an energy beam from the side of the energy absorbing layer. And activating the impurities introduced into the semiconductor layer.

In the method of manufacturing a semiconductor device according to the present invention,
The irradiated energy beam is once absorbed by the energy absorbing layer, and indirectly passes through the energy absorbing layer without damaging a low heat-resistant substrate such as plastic, thereby forming a lower metal layer, an insulating layer, and the like. Heat the semiconductor layer. Thus, activation of impurities in the semiconductor layer and removal of defects in the insulating layer are performed.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 shows a sectional structure of a top gate type TFT according to a first embodiment of the present invention. The TFT includes, for example, a substrate 10
A polycrystalline silicon (Si) layer 13 having a channel region 13a, a source region 13b, and a drain region 13c is provided via a buffer layer 11 thereon. The source region 13b and the drain region 13c are formed apart from each other and adjacent to the channel region 13a. A gate electrode 15 is formed on the channel region 13a via an insulating layer 14, a source electrode 17 is electrically connected to the source region 13b, and a drain electrode 18 is electrically connected to the drain region 13c.

A method of manufacturing such a TFT will be described below with reference to FIGS.

First, as shown in FIG. 2, a buffer layer 11 for protecting the substrate 10 from heat by a heat insulating effect is formed on the substrate 10 having a heat resistance temperature of about 200 ° C. or less.
It is formed at a temperature equal to or lower than the heat resistant temperature of the substrate 10.

As the substrate 10, for example, an organic material is used. Specifically, polyethylene sulfone (PE
S), polyesters such as polyethylene terephthalate (PET), polyethylene naphthalate or polycarbonate, polyolefins such as polypropylene, polyphenylene sulfides such as polyphenylene sulfide, polyamides, aromatic polyamides, polyether ketones or Polymer materials such as polyimides are preferable, and may be configured to include any one or more of these. The thickness of the substrate 10 is, for example, 200 μm.
The thickness m is more preferable in order to impart flexibility to the TFT and reduce its size. The softening point of such an organic material is 250 ° C. or less, and among them, PES
And PET have a heat resistance of 200 ° C. and 100 ° C., respectively.
It is about ° C. As the buffer layer 11, for example, silicon dioxide (SiO ₂ ) is used. In addition, silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), or a laminated film of these can be used. The thickness of the buffer layer 11 is, for example, 30
It is set to 0 nm.

Next, an amorphous silicon layer 12 is formed on the buffer layer 11 at a temperature lower than the allowable temperature limit of the substrate 10.
The thickness of the amorphous silicon layer 12 is, for example, 30 nm.
The buffer layer 11 and the amorphous silicon layer 12 are formed by, for example, a reactive sputtering method or plasma enhanced CVD (Plasma Enhanced Chemical Vapor Dep.).
osition; PECVD method, low pressure CVD (Low Pressure)
A CVD; LPCVD) method, an evaporation method, or the like can be used. Here, the amorphous silicon layer 12 is formed using silicon (Si). However, silicon germanium (SiGe) containing Si, germanium (G
e) One or more semiconductors of silicon carbide (SiC) can be used.

Next, the amorphous silicon layer 12 is heated by irradiating a pulse laser beam, for example. As a result, the amorphous silicon layer 12 is crystallized and becomes a polycrystalline silicon layer 13 as shown in FIG. As the pulse laser beam, it is preferable to use a laser having a wavelength easily absorbed by the amorphous silicon layer 12, that is, a wavelength in an ultraviolet region.
Specifically, a XeCl excimer laser (wavelength 308n)
m), KrF excimer laser (wavelength 248 nm), Ar
An F excimer laser (wavelength 193 nm), a XeF excimer laser (wavelength 351 nm), a third harmonic (355 nm) of an Nd: YAG laser, a fourth harmonic (266 nm) of a Nd: YAG laser, or the like can be used. Conditions such as the laser wavelength, energy density, pulse width, and number of irradiation pulses are appropriately selected according to the thickness of the amorphous silicon layer 12 and the like. However, the amorphous silicon layer 1
2 is sufficiently heated to form a polycrystalline silicon layer 13 having good crystallinity.
In order to obtain a pulse width of 100 ps or more,
It is preferably within the range of 00 ns or less.

The irradiated pulse laser beam is almost completely absorbed by the amorphous silicon layer 12. Therefore, the substrate 10 is hardly heated. Here, the polycrystalline silicon layer 13 corresponds to a specific example of the “semiconductor layer” of the present invention. The “semiconductor layer” does not necessarily need to be entirely polycrystalline, and may be formed to have, for example, a partially crystalline region.

Further, the polycrystalline silicon layer 13 is patterned into a predetermined shape, for example, an island shape by, for example, lithography and etching.

Next, as shown in FIG. 4, an insulating layer 1 is formed on the patterned polycrystalline silicon layer 13 by using, for example, SiO ₂ or SiN _x so as to cover the polycrystalline silicon layer 13.
4 is formed at a temperature equal to or lower than the heat resistant temperature of the substrate 10. This insulating layer 14 is formed by, for example, a reactive sputtering method, PEC.
It can be formed by a VD method, a vapor deposition method, a JVD (Jet Vapor Deposition) method, or the like, and can also be obtained by plasma oxidizing or plasma nitriding the surface of the polycrystalline silicon layer 13. The thickness of the insulating layer 14 is, for example, 50 nm.

Next, a gate electrode 15 is formed on the insulating layer 14 using, for example, aluminum (Al) by a sputtering method or an evaporation method. As the gate electrode 15, besides Al, copper (Cu), molybdenum (Mo), tantalum (Ta), platinum (Pt), or ITO (an oxide of indium and tin) can be used. The thickness of the gate electrode 15 is, for example, 240 nm. Here, the gate electrode 15 corresponds to a specific example of the “metal layer” of the present invention.

Subsequently, impurities are introduced into the polycrystalline silicon layer 13 at a temperature lower than the allowable temperature limit of the substrate 10 by using the gate electrode 15 as a mask, for example, by ion implantation. As an impurity, for example, phosphorus (P) is used as an n-type impurity in the case of an n-channel TFT, and boron (B) is used as a p-type impurity in the case of a p-channel TFT. Thus, the source region 13b and the drain region 13c, which are impurity-implanted regions, and the channel region 13a, which is a non-implanted region therebetween, are formed by the gate electrode 1.
5 in a self-aligned manner (see FIG. 5).

Further, as shown in FIG.
The energy absorbing layer 16 is formed at a temperature equal to or lower than the allowable temperature limit of the substrate 10 so as to cover the outermost surface of the substrate 10 from above the layer 5 and the insulating layer 14. As described later, the energy absorbing layer 16 is made of a material whose band gap is equal to or less than the energy of the energy beam in order to absorb the irradiation energy of the energy beam well. Specifically, carbon (C), silicon (Si), germanium (Ge),
Silicon carbide (SiC), silicon nitride (SiN), aluminum nitride (AlN), silicon germanium (SiG
e) and transition metals molybdenum (Mo), tantalum (Ta), tungsten (W), nickel (N
i), chromium (Cr) and the like, and any one or a plurality of them can be used. In addition,
When removing the energy absorbing layer 16 after the energy beam irradiation, the energy absorbing layer 16 further has an etching selectivity to the gate electrode 15. For example, if the gate electrode 15 is Al, it is preferable to use amorphous silicon for the energy absorbing layer 16. The thickness of the energy absorbing layer 16 is, for example, 30 n
m.

Next, the energy absorbing layer 16 is heated by irradiating an ultraviolet pulse laser beam from, for example, an excimer laser from the side of the energy absorbing layer 16. As this pulse laser beam, the same laser beam that irradiates the amorphous silicon layer 12 can be used. The irradiated laser beam is almost completely absorbed by the energy absorbing layer 16, and the heat radiated from the energy absorbing layer 16 is indirectly heat-treated. Once the energy absorption layer 1
The energy absorbed by 6 is uniformly diverged from the entire layer surface of energy absorption layer 16 and propagates to gate electrode 15, insulating layer 14 and further to polysilicon layer 13. The gate electrode 15 has good thermal conductivity, and heats the periphery thereof, particularly, the insulating layer 14 immediately below the gate electrode 15. Thus, the layers below the insulating layer 14 are heated relatively uniformly and slowly, and the substrate 10 is hardly heated.

By this heat treatment, the polycrystalline silicon layer 1
3 is activated and the gate electrode 15 is heated, whereby the insulating layer 14 and the interface between the insulating layer 14 and the polycrystalline silicon layer 13 are heated, and the inside of the insulating layer 14 and the polycrystalline silicon layer 13 are heated. Defects existing at the interface with the silicon layer 13 are removed. Here, the polycrystalline silicon layer 13
Is preferably activated to an activation rate of 20% or more. By the way, in the case where the laser beam is directly irradiated on the insulating layer 14 as in the related art, if the irradiation amount is reduced to prevent the temperature of the substrate 10 from increasing, the layers below the insulating layer 14 cannot be sufficiently heated. Since the beam energy is locally emitted, a temperature distribution in the layer surface direction occurs in the layers below the insulating layer 14, and in this case, for example, the polycrystalline silicon layer 13 and a part of the insulating layer 14 may not be sufficiently heat-treated. Was.

Next, as shown in FIG. 1, the energy absorbing layer 16 is removed. Further, a source electrode 17 and a drain electrode 18 are formed above the source region 13b and the drain region 13c. The source electrode 17 and the drain electrode 18 can be formed by a known method such as, for example, using Al and forming a film by a sputtering method, a vapor deposition method, and then patterning the film by lithography and etching. The surface of the TFT formed in this manner is, for example, SiO _2.
And a protective film may be formed by coating with an oxide such as SiN _x or the like.

As described above, according to the present embodiment, since the pulse laser beam is irradiated after the energy absorbing layer 16 is provided on the substrate 10, the light is locally emitted instantaneously like a laser beam. Once the energy is
By being absorbed by the energy absorbing layer 16 and indirectly diverging from the entire surface of the energy absorbing layer 16,
Although the substrate 10 is not substantially heated, the gate electrode 15, the insulating layer 14, and the polycrystalline silicon layer 13 below the energy absorbing layer 16 are uniformly and slowly heated. Therefore,
The activation of impurities in the polycrystalline silicon layer 13 and the removal of defects generated in and around the insulating layer 14 can be sufficiently and simultaneously performed while preventing damage to the substrate 10 caused by direct irradiation with a laser beam. it can.

Further, according to the present embodiment, the impurity is ion-implanted into polycrystalline silicon layer 13 using gate electrode 15 as a mask, so that channel region 13a can be formed in one step without forming a separate mask. , Source region 13b and drain region 13c can be formed in a self-aligned manner.

[Second Embodiment] FIG. 6 shows a cross-sectional structure of a top gate type TFT according to a second embodiment of the present invention. This TFT includes insulating layers 14a, 14
It has the same configuration as the first embodiment except that a gate electrode 15a is formed between the gate electrodes b. here,
Insulating layers 14a, 14b and gate electrodes 15a, 15b
Are the insulating layer 14 and the gate electrode 1 of the first embodiment.
5 is supported. Therefore, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

A method of manufacturing such a TFT will be described below with reference to FIGS.

First, similarly to the first embodiment, a buffer layer 11 and an amorphous silicon layer 12 are sequentially formed on a substrate 10 at a temperature lower than the allowable temperature limit of the substrate 10. 12 is heated by a pulsed laser beam. As a result, the amorphous silicon layer 12 is crystallized to form a polycrystalline silicon layer 13. As the pulse laser beam, for example, an excimer laser or the like that is the same as that in the first embodiment can be used. The irradiated pulse laser beam is almost completely absorbed by the amorphous silicon layer 12, and the substrate 10 is hardly heated.

Next, as shown in FIG. 7, an insulating layer 14a is formed on the polycrystalline silicon layer 13 at a temperature lower than the allowable temperature limit of the substrate 10, and a gate electrode 15a is formed thereon. Then, ECR-RIE (Electron Cyclotro) in a mixed gas of CF ₄ and H ₂ is performed using the gate electrode 15a as a mask.
n Selective etching by Resonance Reactive Ion Etching). As a result, the insulating layer 14a on the polycrystalline silicon layer 13 serving as the source region 13b and the drain region 13c is removed in a self-aligned manner.

Further, impurities are introduced into polycrystalline silicon layer 13 by plasma doping using gate electrode 15a as a mask. The plasma doping is performed, for example, by setting the temperature of the substrate 10 to 110 ° C., exposing the substrate 10 to glow discharge plasma of a mixed gas of PH ₃ and He, and adsorbing phosphorus (P) on the surface of the polycrystalline silicon layer 13. As impurities,
In addition to phosphorus (P), which is an n-type impurity, for example, boron (B), which is a p-type impurity, can also be used. In this case, the substrate 10 is exposed to B ₂ H ₆ plasma to adsorb boron (B). . Since the adsorbed impurities diffuse only in the vicinity of the surface (up to 1 nm) of the polycrystalline silicon layer 13 as it is, they are sufficiently diffused and doped into the polycrystalline silicon layer 13 by the following laser irradiation.

Next, as shown in FIG. 8, an insulating layer 14b and an energy absorbing layer 16 are sequentially formed on the polycrystalline silicon layer 13 and the gate electrode 15 at a temperature lower than the heat resistant temperature of the substrate 10.

Next, as shown in FIG. 9, an ultraviolet pulse laser beam is irradiated from the side of the energy absorbing layer 16 by, for example, an excimer laser to heat the energy absorbing layer 16. The energy absorbing layer 16 almost completely absorbs the laser beam and radiates heat, and the heat diffuses and activates impurities (here, phosphorus (P)) of the polycrystalline silicon layer 13 and is heated. Insulating layers 14a and 14b and insulating layers 14a and 14b via gate electrode 15a
The interface between the silicon and polycrystalline silicon layer 13 is heat-treated. As described above, the heat treatment is performed indirectly through the energy absorbing layer 16, and the substrate 10 is hardly heated. It is desirable that the impurities in the polycrystalline silicon layer 13 be activated to an activation rate of 20% or more. As a result, the source region 13b and the drain region 13 which are impurity implanted regions are formed.
c and a channel region 13 which is a non-injection region between them.
a are formed in self-alignment with the gate electrode 15a. At the same time, defects existing inside the insulating layers 14a and 14b and at the interface between the insulating layers 14a and 14b and the polycrystalline silicon layer 13 are removed.

Next, as shown in FIG. 6, the energy absorbing layer 16 is removed. Further, the gate electrode 15b, the gate electrode 15a, and the drain region 13c are formed on the channel region 13a (more precisely, the gate electrode 15a).
A source electrode 17 and a drain electrode 18 are formed.

As described above, in the present embodiment, the pulse laser beam is irradiated after the energy absorbing layer 16 is provided on the substrate 10, so that the pulse laser beam is locally irradiated as in the first embodiment. The energy of the emitted laser beam is temporarily absorbed by the energy absorbing layer 16 and is indirectly diverted from the entire surface of the energy absorbing layer 16, so that the lower layer of the energy absorbing layer 16 is uniformly and slowly heated. However, the substrate 10 is not substantially heated. Therefore, the substrate 1 generated when the laser beam is directly irradiated is
Thus, activation of impurities in the polycrystalline silicon layer 13 and removal of defects generated inside and around the insulating layer 14 can be sufficiently and simultaneously performed while preventing damage to the polycrystalline silicon layer 13.

Also, in this embodiment, as in the first embodiment, the polysilicon layer 13 is plasma-doped with impurities using the gate electrode 15 as a mask, so that a separate mask is not formed. Channel area 1
3a, the source region 13b and the drain region 13c can be formed in a self-aligned manner.

As described above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified. For example, in the above-described embodiment, a specific method of manufacturing a TFT as a semiconductor device has been described. However, the present invention forms a metal layer via an insulating layer on a semiconductor layer formed on a substrate, After implanting impurities into the semiconductor layer using the metal layer as a mask, an energy absorption layer is further formed on the entire surface, and an energy beam is irradiated from above to activate the impurities, thereby producing a semiconductor having another structure. The present invention can be widely applied to devices.

[0039]

As described above, according to the method of manufacturing a semiconductor device of the present invention, an energy absorbing layer is formed so as to cover an insulating layer and a metal layer provided on a semiconductor layer. Irradiates an energy beam from the substrate, the applied energy heats the underlying metal layer, insulating layer, and semiconductor layer via the energy absorbing layer, but does not substantially heat the substrate. Therefore, it is possible to prevent the substrate from being directly irradiated with the energy beam and damaged. According to such a method, the insulating layer and the semiconductor layer are sufficiently heated,
At the same time as the activation of impurities in the semiconductor layer, defects existing in the insulating layer and its surroundings are effectively removed, so that a semiconductor device with favorable characteristics can be obtained. Therefore, a low heat-resistant substrate made of, for example, an organic material can be used as the substrate, and a semiconductor device that is lightweight, resistant to impact, and has excellent characteristics can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a TFT according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the TFT shown in FIG.

FIG. 3 is a cross-sectional view for explaining a manufacturing process following the process in FIG. 2;

FIG. 4 is a cross-sectional view for explaining a manufacturing step following the step in FIG. 3;

FIG. 5 is a cross-sectional view for explaining a manufacturing step that follows the step of FIG. 4;

FIG. 6 is a cross-sectional view illustrating a configuration of a TFT according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a manufacturing process of the TFT shown in FIG.

FIG. 8 is a cross-sectional view for explaining a manufacturing process following the process in FIG. 7;

FIG. 9 is a cross-sectional view for explaining a manufacturing step following the step in FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate, 12 ... Amorphous silicon layer, 13 ... Polycrystalline silicon layer, 13a ... Channel region, 13b ... Source region, 13c ... Drain region, 14 ... Insulating film, 15 ... Gate electrode, 16 ... Energy absorption layer, 17 ... source electrode,
18 ... Drain electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akio Machida 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Miyako Chuetsu 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (72) Inventor Setsuo Usui 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo F-term within Sony Corporation (reference) 5F110 AA17 BB02 BB05 CC02 DD01 DD07 DD13 DD14 DD15 DD17 EE02 EE03 EE04 EE07 EE38 EE43 EE44 FF02 FF03 FF25 FF26 FF27 FF28 FF30 GG01 GG02 GG03 GG13 GG25 GG42 GG43 GG45 GG47 HJ01 HJ13 HJ18 HJ23 HL03 HL22 HL23 NN02 NN23 NN24 PP03 PP04 QQ11

Claims (10)

[Claims] A step of forming a semiconductor layer on the substrate; a step of selectively forming a metal layer on the semiconductor layer via an insulating layer; and selectively forming the metal layer on the semiconductor layer using the metal layer as a mask. Introducing an impurity; forming an energy absorbing layer so as to cover the insulating layer and the metal layer; irradiating an energy beam from the side of the energy absorbing layer to activate the impurity introduced into the semiconductor layer A method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein the substrate has a softening point of 250 ° C. or lower. 3. The method according to claim 2, wherein the substrate is formed of an organic polymer material. 4. The method according to claim 1, wherein the energy absorbing layer is formed of a material having a band gap equal to or less than the energy of the energy beam. 5. The method according to claim 1, wherein the energy absorbing layer comprises carbon (C),
Silicon (Si), germanium (Ge), silicon carbide (SiC), silicon germanium (SiG
e), silicon nitride (SiN), aluminum nitride (A
5. The method according to claim 4, wherein the semiconductor device is formed by at least one of (1N). 6. The method according to claim 1, wherein the energy absorbing layer is formed of at least one of molybdenum (Mo), tantalum (Ta), tungsten (W), nickel (Ni), and chromium (Cr). Item 5. The method for manufacturing a semiconductor device according to Item 4. 7. The semiconductor layer is made of silicon (Si), silicon germanium (SiGe), germanium (G).
2. The method according to claim 1, wherein the semiconductor device is formed of at least one of silicon carbide (e) and silicon carbide (SiC). 8. The method according to claim 1, wherein an activation rate of the impurity in the impurity region of the semiconductor layer is 20% or more. 9. The method according to claim 1, wherein the energy beam is a pulsed laser beam. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the pulse width of the pulsed laser beam is in a range from 100 ps to 300 ns.