JP3930949B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3930949B2
JP3930949B2 JP21799397A JP21799397A JP3930949B2 JP 3930949 B2 JP3930949 B2 JP 3930949B2 JP 21799397 A JP21799397 A JP 21799397A JP 21799397 A JP21799397 A JP 21799397A JP 3930949 B2 JP3930949 B2 JP 3930949B2
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Japan
Prior art keywords
semiconductor chip
lead frame
semiconductor device
tape
lead
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JP21799397A
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Japanese (ja)
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JPH1154530A (en
Inventor
宏平 巽
健二 下川
英児 橋野
洋司 川上
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Nippon Steel Chemical and Materials Co Ltd
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Nippon Steel Materials Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

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  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which has the excellent coupling strength with a chip electrode, a lead and the like and can realize the thin configuration and the like effectively, and the manutacturing method thereof. SOLUTION: To a semiconductor device 10, leads 13 of a lead frame and electrodes 12 of a semiconductor chip 11 are connected. The lead 13 and the chip electrode 12 are connected through a metal bump 14. A part 16 of the lead frame and the semiconductor chip 11 are coupled through insulating resin or a tape 17. The metal bump 14 is the spherical bump. The insulating resin or the cape 17 is formed thinner than the initial bump diameter or the metal bump 14. By performing the coupling and fixing by utilizing a part of the island 16 and the like of the lead frame, the high coupling strength is secured, and the stress load applied on the electrode part can be decreased to the essential diameter.

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップの電極とリードフレームのリード等が電気的に接続される半導体装置およびその製造方法に関するものである。
【０００２】
【従来の技術】
従来、この種の半導体装置において、半導体チップの電極とリードフレームのリード等を接合媒体としてのバンプを介して接続するものが知られている。近年では半導体装置の高密度化に伴って、電極の狭ピッチ化あるいはバンプの微小化が進んでいる。バンプを形成すべき微小金属ボールが予め、半導体チップの電極等に接合されるようにしたバンプの形成方法が実用化されつつある。
【０００３】
たとえば特開平７−２７３１４３号に記載の半導体装置では、図４のように半導体チップ１の電極２とインナリード３がボールバンプ４を介して接合され、樹脂５によってモールドされる。この半導体装置において、予め半導体チップ１の周辺に配置された電極２にボールバンプ４を接合する、あるいはインナリード３にボールバンプ４を接合しておき、半導体チップ１とインナリード３を重ねて一括接合する。
【０００４】
【発明が解決しようとする課題】
従来の半導体では、上述のようにリードフレームと半導体チップ１をボールバンプ４を介して接合する。しかしながら、これらの接続後の取扱において、たとえば特に樹脂封止あるいは樹脂ポッティング時に応力が加わって、接合部分が剥離する危険があった。
【０００５】
従来の半導体装置においてまた、ＬＯＣ（Lead On Chip）構造としてたとえば図５に示すように、半導体チップ１およびリードフレーム３′をテープ６を介して（機械的に）接続するものがある。この半導体装置は主に、メモリに使用されるが、電気的接続はボンディングワイヤ７によって行われ、つまりバンプを用いて電気的接続するものとは基本構造が異なっている。
【０００６】
本発明はかかる実情に鑑み、チップ電極およびリード等の結合強度に優れ、有効に薄型化等を実現し得る半導体装置およびその製造方法を提供することを目的とする。
【０００７】
【課題を解決するための手段】
本発明の半導体装置の製造方法は、リードフレームのリードと半導体チップの電極が接続されている半導体装置の製造方法において、前記リードフレームの前記リードまたは前記半導体チップの電極に金属ボールを所定量だけ潰して接合し、金属バンプが絶縁性樹脂もしくはテープに覆われずに、前記リードフレームのアイランドと前記半導体チップを前記絶縁性樹脂もしくはテープを介して接合し、さらに前記半導体チップの周囲を樹脂封止することを特徴とする。
【００１０】
また、本発明の半導体装置製造方法は、リードフレームのリードと半導体チップの電極が接続されている半導体装置の製造方法において、前記リードフレームの前記リードまたは前記半導体チップの電極に金属ボールを所定量だけ潰して接合し、金属バンプが絶縁性樹脂もしくはテープに覆われずに、前記リードフレームのアイランドと前記半導体チップを前記絶縁性樹脂もしくはテープを介して接合し、さらに前記接合部を樹脂封止することを特徴とするものである。
【００１１】
また、本発明の半導体装置の製造方法において、前記絶縁性樹脂もしくは前記テープは、前記金属ボールの初期ボール径よりも薄く形成されることを特徴とする。
【００１２】
本発明によれば、リードフレームのリードと半導体チップの電極を接続する際、リードフレームのアイランドと半導体チップが絶縁性樹脂もしくはテープを介して結合固定される。このようにリードフレームおよび半導体チップにおける相互に接続すべき電極部のみでなく、リードフレームのアイランドを利用して結合固定することで、高い結合強度を確保して電極部にかかる応力負荷を実質的に軽減することができる。
【００１３】
この場合、リードフレームと半導体チップを結合固定する絶縁性樹脂もしくはテープが、金属バンプの初期バンプ径よりも薄く形成されており、これにより結合強度を有効に向上することができる。
【００１４】
【発明の実施の形態】
以下、図１〜図３に基づき、本発明による半導体装置およびその製造方法の好適な実施の形態を説明する。
【００１５】
図１および図２は、この実施形態における半導体装置10の構成例を示している。図において、11は半導体チップ、12は半導体チップ11の電極、13はリードフレームのリード、14は金属バンプである。電極12は好適にはアルミニウムで成り、半導体チップ11の周辺に沿って配置される。半導体チップ11の周囲は、モールド樹脂15によって封止される。
【００１６】
バンプ１４は、この例では金（Ａｕ）製の微小金属ボールによって形成され、そのボール直径３０〜５００μｍ程度のサイズが好適である。またリードフレームの一部、この例ではアイランド１６と半導体チップ１１とは、テープ１７を介して結合されている。テープ１７は特に、金属バンプ１４の初期バンプ径よりも薄く形成されている。
【００１７】
半導体装置１０の製造において、リードフレームのリード１３または半導体チップ１１の電極１２にバンプ形成用の金属ボールを予め接合しておく。この金属ボールの接合に際して、リード１３または電極１２に対応する位置に微小金属ボールを配列保持するボール配列ヘッドを使用する。
【００１８】
このボール配列ヘッドは、半導体チップ１１の電極１２（またはリードフレームのリード１３）に対応する多数のボール配列孔を有する配列基板を備え、吸引チャンバを介して真空引されるようになっている。吸引チャンバには真空吸引源としての真空ポンプが接続され、ボール配列ヘッドは、ボール配列孔にて金属ボールを配列保持する。
【００１９】
ボール配列ヘッドは、微小金属ボールを収容する容器上方から、所定タイミングで該容器内に下降する。さらに、吸引チャンバを介して真空引することで、配列基板のボール配列孔にて微小金属ボールを配列保持する。なお、配列基板のボール配列孔に金属ボールを吸着させる際、容器を加振することで容器内で金属ボールを浮遊状態にし、吸着し易くする等の手段がとられる。
【００２０】
配列基板の各ボール配列孔には、１つの金属ボールが吸着される。ここで、金属ボールを吸着する際、配列基板から余剰ボールを除去して各ボール配列孔に１つの微小金属ボールを吸着させるための余剰ボール除去手段をさらに含んでいるとよい。この余剰ボール除去手段はたとえば、配列基板に微振動を与えることにより余分な金属ボールを配列基板から離脱させることができる。このように金属ボールを吸着保持したボール配列ヘッドを、半導体チップ１１の電極１２（またはリードフレームのリード１３）に対して位置合わせしながら半導体チップ１１へと下降させることで、金属ボールを電極１２またはリード１３に効率的に転写接合することができる。
【００２１】
つぎに、リードフレームのアイランド１６に接着されたテープ１７と半導体チップ１１とを熱圧着により結合固定する。このとき同時に、電極１２またはリード１３に接合されている金属ボールが、対応するリード１３または電極１２に対して熱圧着され、これにより各電極１２およびリード１３は相互に接続する。テープ１７は前述したように、金属バンプ１４の初期バンプ径よりも薄く形成されており、この熱圧着で金属ボールが所定量だけ潰れることによりテープ１７を介して適正な接着効果が得られるようになっている。
【００２２】
ここで、図３は、この実施形態に用いるテープ１７の構成例を示している。テープ１７の形成材料としては、たとえば耐熱性のポリイミドが好適である。テープ１７の上下には接着用テープもしくは接着剤から成る接着層１７ａが付設形成されている。テープ１７は一方の接着層１７ａにてリードフレームのアイランド１６に接着され、他方の接着層１７ａが半導体チップ１１に接着される。金属バンプ１４の初期バンプ径をたとえば３５μｍとするとき、接着層１７ａを含めたテープ１７の圧着後の厚さは２２μｍ程度が好適である。
【００２４】
また、例えばポリイミドによって形成されるテープ17を使用する例を説明したが、その代わりに適宜の絶縁性樹脂を介在させるかたちで構成することもできる。
【００２５】
上述の例のようにリードフレームのリード13と半導体チップ11の電極12を接続する際、リードフレームのアイランド16 を利用して結合固定することで、高い結合強度を確保して電極部分にかかる応力負荷を実質的に軽減することができる。したがって、樹脂封止時等に応力が加わっても接合部分が剥離する危険がなく、適正かつ良好な電気接続を保証することができる。また、所謂TCT(温度サイクル試験)においても接合部分に対する応力負荷が軽減することで、半導体装置の保護を図ると共に円滑に試験を行うことができる。
【００２６】
【発明の効果】
以上説明したように本発明によれば、この種の半導体装置においてチップ電極およびリード等の結合強度に優れ、有効に装置の薄型化等を実現することができる。したがって、性能がよく信頼性に優れた薄型パッケージを提供することができるばかりか、高周波用接続に極めて有用である。さらに、実質的に製造コストや製品コストを安くすることができ、コスト的に極めて有利である等の利点を有している。
【図面の簡単な説明】
【図１】 本発明の実施形態における半導体装置の構成例を示す断面図である。
【図２】 本発明の実施形態における半導体装置の構成例を示す平面図である。
【図３】 本発明の実施形態に係る接着テープの構成例を示す断面図である。
【図４】 従来の半導体装置の構成例を示す断面図である。
【図５】 従来の他の半導体装置の構成例を示す断面図である。
【符号の説明】
１０ 半導体装置
１１ 半導体チップ
１２ 半導体チップ電極
１３ リードフレームのリード
１４ 金属バンプ
１５ モールド樹脂
１６ アイランド
１７ テープ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which an electrode of a semiconductor chip and a lead of a lead frame are electrically connected, and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in this type of semiconductor device, a device in which an electrode of a semiconductor chip and a lead of a lead frame are connected via a bump as a bonding medium is known. In recent years, with the increase in the density of semiconductor devices, the pitch of electrodes or the size of bumps has been reduced. A bump forming method in which a minute metal ball on which a bump is to be formed is previously bonded to an electrode of a semiconductor chip or the like is being put into practical use.
[0003]
For example, in the semiconductor device described in JP-A-7-273143, the electrodes 2 and the inner leads 3 of the semiconductor chip 1 as shown in FIG. 4 is joined via the ball bumps 4 are molded by a resin 5. In this semiconductor device, the ball bumps 4 are bonded to the electrodes 2 arranged around the semiconductor chip 1 in advance, or the ball bumps 4 are bonded to the inner leads 3, and the semiconductor chip 1 and the inner leads 3 are overlapped together. Join.
[0004]
[Problems to be solved by the invention]
In the conventional semiconductor, the lead frame and the semiconductor chip 1 are bonded via the ball bumps 4 as described above. However, in handling after these connections, for example, there is a danger that stress is applied particularly at the time of resin sealing or resin potting, and the joint portion peels off.
[0005]
In the conventional semiconductor device also, LOC as shown in (Lead On Chip), for example, as a structure 5, (mechanically) the semiconductor chip 1 and the lead frame 3 'through the tape 6 is used to connect. This semiconductor device is mainly used for a memory, but the electrical connection is made by bonding wires 7, that is, the basic structure is different from that in which electrical connection is made using bumps.
[0006]
In view of such circumstances, an object of the present invention is to provide a semiconductor device that is excellent in the bonding strength of a chip electrode, a lead, and the like, and that can be effectively reduced in thickness and the like, and a method for manufacturing the same.
[0007]
[Means for Solving the Problems]
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device in which a lead frame lead and a semiconductor chip electrode are connected to each other with a predetermined amount of metal balls on the lead frame or the semiconductor chip electrode. The metal bumps are not covered with an insulating resin or tape, and the island of the lead frame and the semiconductor chip are bonded via the insulating resin or tape, and the periphery of the semiconductor chip is sealed with a resin. It is characterized by stopping.
[0010]
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a lead of a lead frame and an electrode of a semiconductor chip are connected, and a predetermined amount of metal balls are applied to the lead of the lead frame or the electrode of the semiconductor chip. The metal bumps are not covered with an insulating resin or tape, and the island of the lead frame and the semiconductor chip are bonded via the insulating resin or tape , and the bonded portion is resin-sealed. It is characterized by doing.
[0011]
In the method for manufacturing a semiconductor device of the present invention, the insulating resin or the tape is formed thinner than an initial ball diameter of the metal ball.
[0012]
According to the present invention, when connecting the leads and the semiconductor chip electrode of rie de frame, the leadframe island and the semiconductor chip are connected and fixed via an insulating resin or tape. Thus, not only the electrode portions to be connected to each other in the lead frame and the semiconductor chip, to combine immobilized utilizing Islandia de lead frame, substantially stress load on the electrode section to ensure a high bond strength it can be mitigated.
[0013]
In this case, the insulating resin or tape for bonding and fixing the lead frame and the semiconductor chip is formed to be thinner than the initial bump diameter of the metal bump, thereby effectively improving the bonding strength.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, based on FIGS. 1 to 3, illustrating a preferred embodiment of a semiconductor device and a manufacturing method thereof according to the present invention.
[0015]
1 and 2 show a configuration example of the semiconductor device 10 in this embodiment. In the figure, 11 is a semiconductor chip, 12 is an electrode of the semiconductor chip 11, 13 is a lead of the lead frame, and 14 is a metal bump. The electrode 12 is preferably made of aluminum and disposed along the periphery of the semiconductor chip 11. Periphery of the semiconductor chip 11 is sealed by a motor Rudo resin 15.
[0016]
In this example, the bump 14 is formed of a gold (Au) fine metal ball, and the ball diameter is preferably about 30 to 500 μm. Further, a part of the lead frame, in this example, the island 16 and the semiconductor chip 11 are coupled via a tape 17. In particular, the tape 17 is formed thinner than the initial bump diameter of the metal bump 14.
[0017]
In manufacturing the semiconductor device 10, bump forming metal balls are bonded in advance to the leads 13 of the lead frame or the electrodes 12 of the semiconductor chip 11. At the time of joining the metal balls, a ball array head for arranging and holding minute metal balls at positions corresponding to the leads 13 or the electrodes 12 is used.
[0018]
The ball array head includes an array substrate having a large number of ball array holes corresponding to the electrodes 12 (or leads 13 of the lead frame) of the semiconductor chip 11 and is evacuated through a suction chamber. A vacuum pump as a vacuum suction source is connected to the suction chamber, and the ball arrangement head holds and holds the metal balls in the ball arrangement holes.
[0019]
The ball array head descends into the container at a predetermined timing from above the container that accommodates the fine metal balls. Furthermore, vacuum metal is drawn through the suction chamber, whereby the fine metal balls are arrayed and held in the ball array holes of the array substrate. When the metal balls are attracted to the ball array holes of the array substrate, a measure is taken such that the metal balls are floated in the container to be easily attracted by vibrating the container.
[0020]
One metal ball is adsorbed to each ball array hole of the array substrate. Here, when adsorbing the metal balls, it is preferable to further include surplus ball removing means for removing the surplus balls from the array substrate and adsorbing one minute metal ball in each ball array hole. For example, the surplus ball removing means can cause the extra metal balls to be detached from the array substrate by applying a slight vibration to the array substrate. The ball array head holding and holding the metal balls in this way is lowered to the semiconductor chip 11 while being aligned with the electrode 12 (or the lead 13 of the lead frame) of the semiconductor chip 11, whereby the metal ball is moved to the electrode 12. Alternatively, it can be efficiently transferred and bonded to the lead 13.
[0021]
Next, the tape 17 bonded to the island 16 of the lead frame and the semiconductor chip 11 are bonded and fixed by thermocompression bonding. At the same time, the metal ball bonded to the electrode 12 or the lead 13 is thermocompression bonded to the corresponding lead 13 or the electrode 12, whereby the electrodes 12 and the leads 13 are connected to each other. As described above, the tape 17 is formed to be thinner than the initial bump diameter of the metal bump 14, and the metal ball is crushed by a predetermined amount by this thermocompression bonding so that an appropriate bonding effect can be obtained via the tape 17. It has become.
[0022]
Here, FIG. 3 shows a configuration example of the tape 17 used in this embodiment. As a material for forming the tape 17, for example, heat-resistant polyimide is suitable. Adhesive layers 17a made of an adhesive tape or an adhesive are provided on and under the tape 17 respectively. The tape 17 is bonded to the island 16 of the lead frame with one adhesive layer 17 a and the other adhesive layer 17 a is bonded to the semiconductor chip 11. When the initial bump diameter of the metal bump 14 is set to 35 μm, for example, the thickness after pressure bonding of the tape 17 including the adhesive layer 17a is preferably about 22 μm.
[0024]
Also, an example has been described to use the tape 17 which is formed by, for example, polyimide, can be configured in the form of interposing an appropriate insulating resin instead.
[0025]
When connecting the lead 13 of the lead frame and the electrode 12 of the semiconductor chip 11 as in the above-described example, the lead frame island 16 is used for bonding and fixing, so that high bonding strength is ensured and the electrode portion is applied. it is possible to substantially reduce the stress load. Therefore, even if stress is applied at the time of resin sealing or the like, there is no risk that the bonded portion will peel off, and proper and good electrical connection can be ensured. In addition, by also stress load is reduced to the bonding portion in the so-called TCT (thermal cycle test), it can be performed smoothly tested with promoting the protection of a semiconductor device.
[0026]
【The invention's effect】
As described above, according to the present invention, in this type of semiconductor device, the bonding strength of the chip electrode and the lead is excellent, and the device can be effectively thinned. Therefore, not only can a thin package with high performance and excellent reliability be provided, but it is extremely useful for high-frequency connections. Furthermore, the manufacturing cost and product cost can be substantially reduced, and there are advantages such as extremely advantageous cost.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration example of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a plan view illustrating a configuration example of a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a configuration example of an adhesive tape according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a configuration example of a conventional semiconductor device.
FIG. 5 is a cross-sectional view showing a configuration example of another conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor chip 12 Semiconductor chip electrode 13 Lead frame lead 14 Metal bump 15 Mold resin 16 Island 17 Tape

Claims (2)

リードフレームのリードと半導体チップの電極が接続されている半導体装置の製造方法において、
前記リードフレームの前記リードまたは前記半導体チップの電極に金属ボールを所定量だけ潰して接合し、金属バンプが絶縁性樹脂もしくはテープに覆われずに、前記リードフレームのアイランドと前記半導体チップを前記絶縁性樹脂もしくはテープを介して接合し、さらに前記半導体チップの周囲を樹脂封止することを特徴とする半導体装置の製造方法。In the manufacturing method of the semiconductor device in which the lead of the lead frame and the electrode of the semiconductor chip are connected,
A predetermined amount of metal balls are crushed and joined to the leads of the lead frame or the electrodes of the semiconductor chip, and the metal bumps are not covered with insulating resin or tape, and the island of the lead frame and the semiconductor chip are insulated. A method for manufacturing a semiconductor device, characterized in that the semiconductor chip is bonded through a conductive resin or tape, and the periphery of the semiconductor chip is sealed with resin. 前記絶縁性樹脂もしくは前記テープは、前記金属ボールの初期ボール径よりも薄く形成されることを特徴とする請求項１に記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 1 , wherein the insulating resin or the tape is formed thinner than an initial ball diameter of the metal ball.
JP21799397A 1997-07-29 1997-07-29 Manufacturing method of semiconductor device Expired - Fee Related JP3930949B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21799397A JP3930949B2 (en) 1997-07-29 1997-07-29 Manufacturing method of semiconductor device

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Application Number Priority Date Filing Date Title
JP21799397A JP3930949B2 (en) 1997-07-29 1997-07-29 Manufacturing method of semiconductor device

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Publication Number Publication Date
JPH1154530A JPH1154530A (en) 1999-02-26
JP3930949B2 true JP3930949B2 (en) 2007-06-13

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