JPH1154530A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH1154530A JPH1154530A JP21799397A JP21799397A JPH1154530A JP H1154530 A JPH1154530 A JP H1154530A JP 21799397 A JP21799397 A JP 21799397A JP 21799397 A JP21799397 A JP 21799397A JP H1154530 A JPH1154530 A JP H1154530A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- tape
- semiconductor chip
- electrode
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップの電
極とリードフレームのリード等が電気的に接続される半
導体装置およびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which electrodes of a semiconductor chip are electrically connected to leads of a lead frame, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、この種の半導体装置において、半
導体チップの電極とリードフレームのリード等を接合媒
体としてのバンプを介して接続するものが知られてい
る。近年では半導体装置の高密度化に伴って、電極の狭
ピッチ化あるいはバンプの微小化が進んでいる。バンプ
を形成すべき微小金属ボールが予め、半導体チップの電
極等に接合されるようにしたバンプの形成方法が実用化
されつつある。2. Description of the Related Art Heretofore, in this type of semiconductor device, there has been known a semiconductor device in which electrodes of a semiconductor chip and leads of a lead frame are connected via bumps as a bonding medium. In recent years, as the density of semiconductor devices has increased, the pitch of electrodes has been reduced or the size of bumps has been reduced. A method of forming a bump in which a minute metal ball on which a bump is to be formed is previously bonded to an electrode or the like of a semiconductor chip is being put to practical use.
【０００３】たとえば特開平７−２７３１４３号に記載
の半導体装置では、図５のように半導体チップ１の電極
２とインナリード３がボールバンプ４を介して接合さ
れ、樹脂５によってモールドされる。この半導体装置に
おいて、予め半導体チップ１の周辺に配置された電極２
にボールバンプ４を接合するか、あるいはインナリード
３にボールバンプ４を接合しておき、半導体チップ１と
インナリード３を重ねて一括接合する。For example, in the semiconductor device described in Japanese Patent Application Laid-Open No. 7-273143, the electrodes 2 of the semiconductor chip 1 and the inner leads 3 are joined via ball bumps 4 as shown in FIG. In this semiconductor device, an electrode 2 previously arranged around a semiconductor chip 1
The ball bump 4 is bonded to the inner lead 3, or the ball bump 4 is bonded to the inner lead 3, and the semiconductor chip 1 and the inner lead 3 are overlapped and bonded together.
【０００４】[0004]
【発明が解決しようとする課題】従来の半導体では、上
述のようにリードフレームと半導体チップ１をボールバ
ンプ４を介して接合する。しかしながら、これらの接続
後の取扱において、たとえば特に樹脂封止あるいは樹脂
ポッティング時に応力が加わって、接合部分が剥離する
危険があった。In the conventional semiconductor, the lead frame and the semiconductor chip 1 are joined via the ball bumps 4 as described above. However, in handling after these connections, for example, there is a danger that a stress will be applied particularly at the time of resin sealing or resin potting, and the bonded portion will peel off.
【０００５】従来の半導体装置においてまた、ＬＯＣ
（Lead On Chip）構造としてたとえば図６に示すよう
に、半導体チップ１およびリードフレーム３′をテープ
６を介して（機械的に）接続するものがある。この半導
体装置は主に、メモリに使用されるが、電気的接続はボ
ンディングワイヤ７によって行われ、つまりバンプを用
いて電気的接続するものとは基本構造が異なっている。In a conventional semiconductor device, LOC
As a (Lead On Chip) structure, for example, as shown in FIG. 6, there is a structure in which a semiconductor chip 1 and a lead frame 3 'are connected (mechanically) via a tape 6. This semiconductor device is mainly used for a memory, but an electrical connection is made by a bonding wire 7, that is, a basic structure is different from that of an electrical connection using a bump.
【０００６】本発明はかかる実情に鑑み、チップ電極お
よびリード等の結合強度に優れ、有効に薄型化等を実現
し得る半導体装置およびその製造方法を提供することを
目的とする。SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a semiconductor device which is excellent in bonding strength between a chip electrode and a lead and which can effectively realize a reduction in thickness and a method for manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置は、
リードフレームのリードと半導体チップの電極が接続さ
れている半導体装置において、リードとチップ電極が金
属バンプを介して接続され、リードフレームの一部と半
導体チップが、絶縁性樹脂もしくはテープを介して結合
されているものである。According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device in which the lead of a lead frame and the electrode of a semiconductor chip are connected, the lead and the chip electrode are connected via a metal bump, and a part of the lead frame and the semiconductor chip are connected via an insulating resin or tape. Is what is being done.
【０００８】また、本発明の半導体装置において、金属
バンプがボール状バンプであることを特徴とする。ま
た、本発明の半導体装置において、前記絶縁性樹脂もし
くはテープは、前記金属バンプの初期バンプ径よりも薄
く形成されていることを特徴とする。Further, in the semiconductor device according to the present invention, the metal bump is a ball-shaped bump. In the semiconductor device according to the present invention, the insulating resin or the tape is formed to be thinner than an initial bump diameter of the metal bump.
【０００９】また、本発明の半導体装置は、テープ基板
またはプリント基板の電極部と半導体チップの電極が接
続されている半導体装置において、テープ基板またはプ
リント基板の電極部とチップ電極が金属バンプを介して
接続され、テープ基板またはプリント基板の一部と半導
体チップが、前記金属バンプの初期バンプ径よりも薄い
絶縁性樹脂もしくはテープを介して結合されているもの
である。Further, according to the semiconductor device of the present invention, in a semiconductor device in which an electrode portion of a tape substrate or a printed board is connected to an electrode of a semiconductor chip, the electrode portion of the tape substrate or the printed board and the chip electrode are connected via metal bumps. And the semiconductor chip is connected to a part of the tape substrate or the printed board via an insulating resin or a tape thinner than the initial bump diameter of the metal bump.
【００１０】また、本発明の半導体装置製造方法は、リ
ードフレームのリードと半導体チップの電極が接続され
ている半導体装置の製造方法において、リードフレーム
のリードまたは半導体チップの電極に金属ボールを接合
し、リードフレームの一部と半導体チップを絶縁性樹脂
もしくはテープを介して結合することを特徴とするもの
である。Further, according to a method of manufacturing a semiconductor device of the present invention, a metal ball is bonded to a lead of a lead frame or an electrode of a semiconductor chip. In addition, a part of the lead frame and the semiconductor chip are connected via an insulating resin or a tape.
【００１１】また、本発明の半導体装置製造方法におい
て、前記絶縁性樹脂もしくはテープは、前記金属ボール
径よりも薄く形成されることを特徴とする。In the method of manufacturing a semiconductor device according to the present invention, the insulating resin or tape is formed to be thinner than the metal ball diameter.
【００１２】本発明によれば、たとえば特にリードフレ
ームのリードと半導体チップの電極を接続する際、リー
ドフレームの一部と半導体チップが絶縁性樹脂もしくは
テープを介して結合固定される。このようにリードフレ
ームおよび半導体チップにおける相互に接続すべき電極
部のみでなく、リードフレームのアイランド等の一部を
利用して結合固定することで、高い結合強度を確保して
電極部にかかる応力負荷を実質径に軽減することができ
る。According to the present invention, for example, particularly when connecting the lead of the lead frame and the electrode of the semiconductor chip, a part of the lead frame and the semiconductor chip are fixedly connected via an insulating resin or a tape. As described above, not only the electrodes to be connected to each other in the lead frame and the semiconductor chip but also a part of the lead frame, such as an island, is used for fixing and fixing, so that a high bonding strength is secured and the stress applied to the electrode is secured. The load can be reduced to a substantial diameter.
【００１３】この場合、リードフレームと半導体チップ
を結合固定する絶縁性樹脂もしくはテープが、金属バン
プの初期バンプ径よりも薄く形成されており、これによ
り結合強度を有効に向上することができる。In this case, the insulating resin or tape for connecting and fixing the lead frame and the semiconductor chip is formed thinner than the initial bump diameter of the metal bumps, whereby the bonding strength can be effectively improved.
【００１４】[0014]
【発明の実施の形態】以下、図１〜図４に基づき、本発
明による半導体装置およびその製造方法の好適な実施の
形態を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to FIGS.
【００１５】図１および図２は、この実施形態における
半導体装置１０の構成例を示している。図において、１
１は半導体チップ、１２は半導体チップ１１の電極、１
３はリードフレームのリード、１４は金属バンプであ
る。電極１２は好適にはアルミニウムで成り、半導体チ
ップ１１の周辺に沿って配置される。半導体チップ１１
の周囲は、たとえば図示例のようにモールド樹脂１５に
よって封止される。FIGS. 1 and 2 show a configuration example of a semiconductor device 10 in this embodiment. In the figure, 1
1 is a semiconductor chip, 12 is an electrode of the semiconductor chip 11, 1
3 is a lead of the lead frame, and 14 is a metal bump. The electrodes 12 are preferably made of aluminum and are arranged along the periphery of the semiconductor chip 11. Semiconductor chip 11
Is sealed with a mold resin 15 as shown in the example of FIG.
【００１６】バンプ１４は、この例では金（Ａｕ）製の
微小金属ボールによって形成され、そのボール直径３０
〜５００μｍ程度のサイズが好適である。またリードフ
レームの一部、この例ではアイランド１６と半導体チッ
プ１１とは、テープ１７を介して結合されている。テー
プ１７は特に、金属バンプ１４の初期バンプ径よりも薄
く形成されている。In this example, the bump 14 is formed of a fine metal ball made of gold (Au), and has a ball diameter 30.
A size of about 500 μm is preferred. Further, a part of the lead frame, in this example, the island 16 and the semiconductor chip 11 are connected via a tape 17. In particular, the tape 17 is formed thinner than the initial bump diameter of the metal bump 14.
【００１７】半導体装置１０の製造において、リードフ
レームのリード１３または半導体チップ１１の電極１２
にバンプ形成用の金属ボールを予め接合しておく。この
金属ボールの接合に際して、リード１３または電極１２
に対応する位置に微小金属ボールを配列保持するボール
配列ヘッドを使用する。In the manufacture of the semiconductor device 10, the leads 13 of the lead frame or the electrodes 12 of the semiconductor chip 11 are used.
A metal ball for bump formation is bonded in advance. When joining the metal balls, the lead 13 or the electrode 12
A ball array head for arraying and holding minute metal balls at a position corresponding to the above is used.
【００１８】このボール配列ヘッドは、半導体チップ１
１の電極１２（またはリードフレームのリード１３）に
対応する多数のボール配列孔を有する配列基板を備え、
吸引チャンバを介して真空引されるようになっている。
吸引チャンバには真空吸引源としての真空ポンプが接続
され、ボール配列ヘッドは、ボール配列孔にて金属ボー
ルを配列保持する。This ball array head is composed of a semiconductor chip 1
An arrangement substrate having a number of ball arrangement holes corresponding to one electrode 12 (or lead 13 of a lead frame);
A vacuum is drawn through the suction chamber.
A vacuum pump as a vacuum suction source is connected to the suction chamber, and the ball arrangement head arranges and holds metal balls in ball arrangement holes.
【００１９】ボール配列ヘッドは、微小金属ボールを収
容する容器上方から、所定タイミングで該容器内に下降
する。さらに、吸引チャンバを介して真空引すること
で、配列基板のボール配列孔にて微小金属ボールを配列
保持する。なお、配列基板のボール配列孔に金属ボール
を吸着させる際、容器を加振することで容器内で金属ボ
ールを浮遊状態にし、吸着し易くする等の手段がとられ
る。The ball arranging head descends into the container from above the container containing the minute metal balls at a predetermined timing. Further, by evacuating through the suction chamber, the minute metal balls are arranged and held in the ball arrangement holes of the arrangement substrate. When the metal balls are adsorbed in the ball arrangement holes of the arrangement substrate, a means is employed such that the container is vibrated so that the metal balls are floated in the container to facilitate the adsorption.
【００２０】配列基板の各ボール配列孔には、１つの金
属ボールが吸着される。ここで、金属ボールを吸着する
際、配列基板から余剰ボールを除去して各ボール配列孔
に１つの微小金属ボールを吸着させるための余剰ボール
除去手段をさらに含んでいるとよい。この余剰ボール除
去手段はたとえば、配列基板に微振動を与えることによ
り余分な金属ボールを配列基板から離脱させることがで
きる。このように金属ボールを吸着保持したボール配列
ヘッドを、半導体チップ１１の電極１２（またはリード
フレームのリード１３）に対して位置合わせしながら半
導体チップ１１へと下降させることで、金属ボールを電
極１２またはリード１３に効率的に転写接合することが
できる。One metal ball is attracted to each ball arrangement hole of the arrangement substrate. Here, when the metal balls are adsorbed, it is preferable to further include a surplus ball removing means for removing the surplus balls from the array substrate and adsorbing one minute metal ball in each ball arrangement hole. The surplus ball removing means can remove extra metal balls from the array substrate by, for example, applying a slight vibration to the array substrate. The ball arrangement head holding the metal ball by suction is lowered to the semiconductor chip 11 while being positioned with respect to the electrode 12 of the semiconductor chip 11 (or the lead 13 of the lead frame). Alternatively, transfer joining to the lead 13 can be efficiently performed.
【００２１】つぎに、リードフレームのアイランド１６
に接着されたテープ１７と半導体チップ１１とを熱圧着
により結合固定する。このとき同時に、電極１２または
リード１３に接合されている金属ボールが、対応するリ
ード１３または電極１２に対して熱圧着され、これによ
り各電極１２およびリード１３は相互に接続する。テー
プ１７は前述したように、金属バンプ１４の初期バンプ
径よりも薄く形成されており、この熱圧着で金属ボール
が所定量だけ潰れることによりテープ１７を介して適正
な接着効果が得られるようになっている。Next, the island 16 of the lead frame
The semiconductor chip 11 and the tape 17 adhered to are bonded and fixed by thermocompression bonding. At this time, simultaneously, the metal balls bonded to the electrodes 12 or the leads 13 are thermocompression-bonded to the corresponding leads 13 or the electrodes 12, whereby the electrodes 12 and the leads 13 are connected to each other. As described above, the tape 17 is formed so as to be thinner than the initial bump diameter of the metal bump 14, and the metal ball is crushed by a predetermined amount by the thermocompression bonding so that an appropriate bonding effect can be obtained via the tape 17. Has become.
【００２２】ここで、図３は、この実施形態に用いるテ
ープ１７の構成例を示している。テープ１７の形成材料
としては、たとえば耐熱性のポリイミドが好適である。
テープ１７の上下には接着用テープもしくは接着剤から
成る接着層１７ａが付設形成されている。テープ１７は
一方の接着層１７ａにてリードフレームのアイランド１
６に接着され、他方の接着層１７ａが半導体チップ１１
に接着される。金属バンプ１４の初期バンプ径をたとえ
ば３５μｍとするとき、接着層１７ａを含めたテープ１
７の圧着後の厚さは２２μｍ程度が好適である。FIG. 3 shows an example of the configuration of the tape 17 used in this embodiment. As a material for forming the tape 17, for example, heat-resistant polyimide is preferable.
Above and below the tape 17, an adhesive layer 17a made of an adhesive tape or an adhesive is additionally formed. The tape 17 is bonded to the lead frame island 1 by one adhesive layer 17a.
6 and the other adhesive layer 17a is
Adhered to. When the initial bump diameter of the metal bumps 14 is, for example, 35 μm, the tape 1 including the adhesive layer 17a
The thickness after press bonding of No. 7 is preferably about 22 μm.
【００２３】また、本発明において微小金属ボールを使
用するＬＯＣ構造例として、図１に示したものに限ら
ず、たとえば図４の例のように電極１２とリード１３を
接続する金属バンプ１４の外側にて、テープ１７を介し
てリード１３および半導体チップ１１を熱圧着により結
合固定するものであってもよい。In the present invention, the LOC structure using the minute metal balls is not limited to the one shown in FIG. 1, but may be, for example, the one outside the metal bump 14 connecting the electrode 12 and the lead 13 as shown in FIG. The lead 13 and the semiconductor chip 11 may be bonded and fixed by thermocompression bonding via the tape 17.
【００２４】さらに、ＴＡＢ（Tape Automated Bondin
g）等のテープ基板またはプリント基板の電極部と半導
体チップの電極が接続される場合にも、そのテープ基板
またはプリント基板の一部と半導体チップをテープを介
して結合することで、上記の実施形態の場合と同様な作
用効果が得られる。また、例えばポリイミドによって形
成されるテープ１７を使用する例を説明したが、その代
わりに適宜の絶縁性樹脂を介在させるかたちで構成する
こともできる。Further, TAB (Tape Automated Bondin)
g) Even when the electrode portion of the tape substrate or the printed circuit board is connected to the electrode of the semiconductor chip, a part of the tape substrate or the printed circuit board and the semiconductor chip are connected to each other via a tape, so that the above-described operation is performed. The same operation and effect as those of the embodiment can be obtained. Further, the example in which the tape 17 formed of, for example, polyimide is used has been described, but instead, the tape 17 may be formed with an appropriate insulating resin interposed therebetween.
【００２５】上述の例のようにリードフレームのリード
１３と半導体チップ１１の電極１２を接続する際、リー
ドフレームのアイランド１６等の一部を利用して結合固
定することで、高い結合強度を確保して電極部分にかか
る応力負荷を実質径に軽減することができる。したがっ
て、樹脂封止時等に応力が加わっても接合部分が剥離す
る危険がなく、適正かつ良好な電気接続を保証すること
ができる。また、所謂ＴＣＴ（温度サイクル試験）にお
いても接合部分に対する応力負荷が軽減することで、半
導体装置を保護を図ると共に円滑に試験を行うことがで
きる。When the leads 13 of the lead frame are connected to the electrodes 12 of the semiconductor chip 11 as in the above-described example, a high bonding strength is secured by using a part of the island 16 or the like of the lead frame to fix the connection. Thus, the stress load applied to the electrode portion can be reduced to a substantial diameter. Therefore, there is no danger that the joined portion will be peeled off even when stress is applied during resin sealing or the like, and proper and good electrical connection can be guaranteed. Also, in a so-called TCT (Temperature Cycle Test), by reducing the stress load on the joint portion, the semiconductor device can be protected and the test can be performed smoothly.
【００２６】[0026]
【発明の効果】以上説明したように本発明によれば、こ
の種の半導体装置においてチップ電極およびリード等の
結合強度に優れ、有効に装置の薄型化等を実現すること
ができる。したがって、性能がよく信頼性に優れた薄型
パッケージを提供することができるばかりか、高周波用
接続に極めて有用である。さらに、実質的に製造コスト
や製品コストを安くすることができ、コスト的に極めて
有利である等の利点を有している。As described above, according to the present invention, in this type of semiconductor device, the bonding strength of the chip electrode, the lead and the like is excellent, and the device can be effectively reduced in thickness. Therefore, not only can a thin package having good performance and excellent reliability be provided, but it is extremely useful for high-frequency connection. Further, there are advantages that the manufacturing cost and the product cost can be substantially reduced, and the cost is extremely advantageous.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の実施形態における半導体装置の構成例
を示す断面図である。FIG. 1 is a cross-sectional view illustrating a configuration example of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の実施形態における半導体装置の構成例
を示す平面図である。FIG. 2 is a plan view illustrating a configuration example of a semiconductor device according to an embodiment of the present invention.
【図３】本発明の実施形態に係る接着テープの構成例を
示す断面図である。FIG. 3 is a cross-sectional view illustrating a configuration example of an adhesive tape according to an embodiment of the present invention.
【図４】本発明の実施形態における半導体装置の他の構
成例を示す断面図である。FIG. 4 is a cross-sectional view illustrating another configuration example of the semiconductor device according to the embodiment of the present invention.
【図５】従来の半導体装置の構成例を示す断面図であ
る。FIG. 5 is a cross-sectional view illustrating a configuration example of a conventional semiconductor device.
【図６】従来の他の半導体装置の構成例を示す断面図で
ある。FIG. 6 is a cross-sectional view illustrating a configuration example of another conventional semiconductor device.
１０ 半導体装置 １１ 半導体チップ １２ 半導体チップ電極 １３ リードフレームのリード １４ 金属バンプ １５ モールド樹脂 １６ アイランド １７ テープ DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor chip 12 Semiconductor chip electrode 13 Lead of a lead frame 14 Metal bump 15 Mold resin 16 Island 17 Tape
───────────────────────────────────────────────────── フロントページの続き (72)発明者 川上 洋司 東京都千代田区大手町２−６−３ 新日本 製鐵株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoji Kawakami Nippon Steel Corporation 2-6-3 Otemachi, Chiyoda-ku, Tokyo
Claims (6)
の電極が接続されている半導体装置において、 リードとチップ電極が金属バンプを介して接続され、リ
ードフレームの一部と半導体チップが、絶縁性樹脂もし
くはテープを介して結合されていることを特徴とする半
導体装置。In a semiconductor device in which a lead of a lead frame and an electrode of a semiconductor chip are connected, the lead and the chip electrode are connected via a metal bump, and a part of the lead frame and the semiconductor chip are formed of an insulating resin or A semiconductor device which is connected via a tape.
を特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the metal bump is a ball bump.
金属バンプの初期バンプ径よりも薄く形成されているこ
とを特徴とする請求項１または２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the insulating resin or the tape is formed thinner than an initial bump diameter of the metal bump.
と半導体チップの電極が接続されている半導体装置にお
いて、 テープ基板またはプリント基板の電極部とチップ電極が
金属バンプを介して接続され、テープ基板またはプリン
ト基板の一部と半導体チップが、前記金属バンプの初期
バンプ径よりも薄い絶縁性樹脂もしくはテープを介して
結合されていることを特徴とする半導体装置。4. A semiconductor device in which an electrode portion of a tape substrate or a printed board is connected to an electrode of a semiconductor chip, wherein the electrode portion of the tape substrate or the printed board is connected to a chip electrode via a metal bump. A semiconductor device, wherein a part of a printed circuit board and a semiconductor chip are connected via an insulating resin or a tape thinner than an initial bump diameter of the metal bump.
の電極が接続されている半導体装置の製造方法におい
て、 リードフレームのリードまたは半導体チップの電極に金
属ボールを接合し、リードフレームの一部と半導体チッ
プを絶縁性樹脂もしくはテープを介して結合することを
特徴とする半導体装置の製造方法。5. A method of manufacturing a semiconductor device in which a lead of a lead frame and an electrode of a semiconductor chip are connected, wherein a metal ball is bonded to the lead of the lead frame or the electrode of the semiconductor chip, and a part of the lead frame and the semiconductor chip are connected. Are bonded via an insulating resin or a tape.
金属ボール径よりも薄く形成されることを特徴とする請
求項５に記載の半導体装置の製造方法。6. The method according to claim 5, wherein said insulating resin or tape is formed thinner than said metal ball diameter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21799397A JP3930949B2 (en) | 1997-07-29 | 1997-07-29 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21799397A JP3930949B2 (en) | 1997-07-29 | 1997-07-29 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1154530A true JPH1154530A (en) | 1999-02-26 |
| JP3930949B2 JP3930949B2 (en) | 2007-06-13 |
Family
ID=16712950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21799397A Expired - Fee Related JP3930949B2 (en) | 1997-07-29 | 1997-07-29 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3930949B2 (en) |
-
1997
- 1997-07-29 JP JP21799397A patent/JP3930949B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3930949B2 (en) | 2007-06-13 |
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