JP3930116B2 - コンピュータシステム - Google Patents

コンピュータシステム Download PDF

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Publication number
JP3930116B2
JP3930116B2 JP23428597A JP23428597A JP3930116B2 JP 3930116 B2 JP3930116 B2 JP 3930116B2 JP 23428597 A JP23428597 A JP 23428597A JP 23428597 A JP23428597 A JP 23428597A JP 3930116 B2 JP3930116 B2 JP 3930116B2
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JP
Japan
Prior art keywords
cpu
mode
sequence
interrupt
smi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23428597A
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English (en)
Japanese (ja)
Other versions
JPH1173330A5 (enExample
JPH1173330A (ja
Inventor
浩 山崎
学 小荒井
尚伸 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Development and Engineering Corp
Original Assignee
Toshiba Corp
Toshiba Digital Media Engineering Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Digital Media Engineering Corp filed Critical Toshiba Corp
Priority to JP23428597A priority Critical patent/JP3930116B2/ja
Priority to US09/073,265 priority patent/US6038632A/en
Publication of JPH1173330A publication Critical patent/JPH1173330A/ja
Publication of JPH1173330A5 publication Critical patent/JPH1173330A5/ja
Application granted granted Critical
Publication of JP3930116B2 publication Critical patent/JP3930116B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP23428597A 1997-05-07 1997-08-29 コンピュータシステム Expired - Lifetime JP3930116B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP23428597A JP3930116B2 (ja) 1997-08-29 1997-08-29 コンピュータシステム
US09/073,265 US6038632A (en) 1997-05-07 1998-05-06 Interrupt control on SMM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23428597A JP3930116B2 (ja) 1997-08-29 1997-08-29 コンピュータシステム

Publications (3)

Publication Number Publication Date
JPH1173330A JPH1173330A (ja) 1999-03-16
JPH1173330A5 JPH1173330A5 (enExample) 2005-06-16
JP3930116B2 true JP3930116B2 (ja) 2007-06-13

Family

ID=16968592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23428597A Expired - Lifetime JP3930116B2 (ja) 1997-05-07 1997-08-29 コンピュータシステム

Country Status (1)

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JP (1) JP3930116B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4580528B2 (ja) 2000-09-25 2010-11-17 株式会社東芝 コンピュータシステムおよびそのレジューム処理方法
JP3784007B2 (ja) * 2002-01-10 2006-06-07 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピュータ、制御方法、及びプログラム
JP4585249B2 (ja) 2004-07-28 2010-11-24 株式会社東芝 情報処理装置
TWI361382B (en) * 2008-07-30 2012-04-01 Pegatron Corp Electronic apparatus and update bios method thereof
US8151027B2 (en) * 2009-04-08 2012-04-03 Intel Corporation System management mode inter-processor interrupt redirection
DE112017006454B4 (de) * 2017-01-25 2020-06-10 Mitsubishi Electric Corporation Computervorrichtung, Aufgabeneinleitungsverfahren und Aufgabeneinleitungsprogramm

Also Published As

Publication number Publication date
JPH1173330A (ja) 1999-03-16

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