JP3923379B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3923379B2
JP3923379B2 JP2002182099A JP2002182099A JP3923379B2 JP 3923379 B2 JP3923379 B2 JP 3923379B2 JP 2002182099 A JP2002182099 A JP 2002182099A JP 2002182099 A JP2002182099 A JP 2002182099A JP 3923379 B2 JP3923379 B2 JP 3923379B2
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JP
Japan
Prior art keywords
wire
semiconductor chip
pad
lead terminal
ball
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Expired - Fee Related
Application number
JP2002182099A
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Japanese (ja)
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JP2004031451A5 (en
JP2004031451A (en
Inventor
和子 鳴瀧
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2002182099A priority Critical patent/JP3923379B2/en
Publication of JP2004031451A publication Critical patent/JP2004031451A/en
Publication of JP2004031451A5 publication Critical patent/JP2004031451A5/ja
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Publication of JP3923379B2 publication Critical patent/JP3923379B2/en
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Description

【０００１】
【発明の属する技術分野】
この発明は、半導体装置、特にパッケージの厚さを薄くするための構成に関するものである。
【０００２】
【従来の技術】
図６及び図７は、従来の半導体装置の構成を示すもので、図６はパッケージの概略構造を示す断面図、図７は半導体チップとリード端子とを接続するワイヤの形状を示す概略側面図である。これらの図において、１はダイパッド、２はダイパッド１にダイボンド材３を介して裏面が固着された半導体チップ、４は半導体チップ２の回路面に設けられた接続用のパッド、６は半導体チップ２と外部回路とを接続するリード端子、７は半導体チップのパッド４とリード端子６とを接続する金線等のワイヤで、金線の先端を溶融して生成した金ボール７Ａをキャピラリー（図示せず）を介してパッド４にボンディングすると共に、キャピラリーをリバース動作させて図６及び図７に７Ｂで示すように屈曲部を形成し、更に必要があればキャピラリーを再度リバース動作させて、図７に７Ｃで示すように第２の屈曲部を形成した後、リード端子６に接続されている。
【０００３】
このように、パッド４からワイヤ７の屈曲部７Ｂまでの高さを持たせるのは、ワイヤ７と半導体チップ２のエッジとの接触を回避するためである。また、８はダイパッド１、半導体チップ２、リード端子６の内端部及びワイヤ７を封止する封止樹脂である。なお、上述した従来の半導体装置は、半導体チップ２の回路面からワイヤ７の屈曲部７Ｂまでの高さが150μｍ程度以上とされていたため、パッケージを薄くしたり、多機能化を図るためにパッケージ内に複数個の半導体チップを搭載することが困難であった。このための改良案として図８〜図１０に示す構成あるいは方法が提案されている。以下、これらの改良案について説明する。
図８〜図１０において、図６、図７と同一または相当部分にはそれぞれ同一符号を付して説明を省略する。
【０００４】
図８に示す改良案は、バンプ５上にワイヤ７を接続する際、キャピラリー９からはみ出したワイヤ７のテール７１を、その長さが50μｍ以下となるように抑えた状態で、かつ先端にボールを生成せずに線径のワイヤのままバンプ５に当接し、キャピラリー９で超音波熱圧着する。その後、キャピラリー９をリバース動作させずにクランパー１０を緩めて所定量のワイヤ７を繰り出した後、キャピラリー９を円弧運動させてリード端子６の上に位置させ、ワイヤ７をリード端子６に超音波熱圧着する。このような構成とすることにより、ワイヤ７のループ高さを50μｍ以下に抑えることが可能となる。
【０００５】
また、図９に示す改良案は、半導体チップ２のパッド４上に設けられていたバンプ５を除去し、パッド４上に直接ワイヤ７を圧着するものである。
圧着の手順は図８の場合と同様である。このようにすると、バンプ５の高さ分だけ更にワイヤのループ高さを抑えることができる。
【０００６】
また、図１０に示す改良案は、図６、図７と同様に、ワイヤ７の先端にボール７Ａを生成し半導体チップ２のパッド４上にボールボンドする構成で、図６、図７の場合よりワイヤ７のループ高さを抑えようとするものである。即ち、この場合には、半導体チップ２のパッド４にワイヤ７をボールボンドした後、キャピラリー９をリバース動作させずに、そのままリード端子６上に移動させ、ワイヤ７をリード端子６に超音波熱圧着させるものである。
【０００７】
【発明が解決しようとする課題】
従来の半導体装置及び従来の改良案は以上のように構成され、図６、図７の構成に比してワイヤのループ高さをある程度低く抑えることが可能となったが、パッケージの更なる薄型化と多機能化を図ることが求められているため、従来の改良案では、なお十分とは云えないという問題点があった。
この発明は、このような問題点に対処するためになされたもので、ワイヤのループ高さを更に低く抑えることができる半導体装置を提供することを目的とする。
【０００８】
【課題を解決するための手段】
この発明に係る半導体装置は、ダイパッドに装着された半導体チップ、この半導体チップと外部回路とを接続するリード端子、上記半導体チップのパッドにボール部が接続され、他端が上記リード端子に接続されると共に、上記パッドよりも、反リード端子側で折り返され、上記折り返された部分と、上記他端との間で、上記ボール部の上に固定されたワイヤ及び上記半導体チップ、パッド、リード端子の一部並びにワイヤを封止する封止樹脂を備えたものである。
【０００９】
この発明に係る半導体装置は、また、上記半導体チップが、複数個の半導体チップの積層体とされるものである。
【００１０】
【発明の実施の形態】
参考の形態１．
以下、この発明の実施の形態の説明に先立って参考の形態を図にもとづいて説明する。図１は、参考の形態１の構成及び製造方法を説明するための概略図で、封止樹脂は省略している。
この図において、図７と同一または相当部分にはそれぞれ同一符号を付して説明を省略する。この形態は、ワイヤ７の半導体チップ側の接続をボールボンドによって行なうもので、図１（ａ）に示すように、半導体チップ２のパッド４にワイヤ７の一端をボールボンドした後、キャピラリー９を破線矢印で示すように、上方に向けてＡまで移動させ、その後、Ａからリード端子６側、即ち図１において右方へ破線矢印で示すように、Ｂまでリバース動作させる。
この結果、ワイヤ７はパッド４にボールボンドした位置とＢとを結ぶ形で傾斜する。その後、キャピラリー９を破線矢印で示すように、Ｂから更に上方に向けてＣまで移動させ、その後、Ｃから反リード端子側、即ち図１において左方へ破線矢印で示すように、Ｄまでリバース動作させる。この結果、ワイヤ７はＢで屈曲してＢとＤとを結ぶ形で傾斜する。その後、キャピラリー９を図１において右下方に移動させて、リード端子６にワイヤ７の他端を超音波熱圧着すると、ワイヤ７は図１（ｂ）に示すように、２個所で屈曲してループ高さが更に低く抑えられるものである。なお、以上の説明では、ワイヤ７の一端を半導体チップのパッド４にボールボンドする例を示したが、ワイヤ７の一端にボールを生成せず、線径のワイヤのままパッド４に当接して圧着してもよい。また、パッド４上にバンプを設け、このバンプにワイヤをボールボンドあるいは線径のワイヤのまま圧着するようにしてもよい。
【００１１】
参考の形態２．
次に、この発明の参考の形態２を図にもとづいて説明する。図２は、参考の形態２の構成及び製造方法を説明するための概略図で、封止樹脂は省略している。
この図において、図１と同一または相当部分にはそれぞれ同一符号を付して説明を省略する。この形態は、参考の形態１と同様に、ワイヤの半導体チップ側の接続をボールボンドによって行なうもので、図２（ａ）に示すように、半導体チップ２のパッド４にワイヤ７の一端をボールボンドした後、キャピラリー９を破線矢印で示すように、上方に向けてＡまで移動させ、その後、Ａからリード端子６側、即ち図２において右方へ破線矢印で示すように、Ｂまでリバース動作させる。この結果、ワイヤ７はパッド４にボールボンドした位置とＢとを結ぶ形で傾斜する。その後、キャピラリー９を破線矢印で示すように、Ｂから更に上方に向けてＣまで移動させ、その後、Ｃから更にリード端子側、即ち図２において右方へ破線矢印で示すように、Ｅまでリバース動作させる。
この結果、ワイヤ７はＢで屈曲してＢとＥとを結ぶ形で傾斜する。その後、キャピラリー９を図２において右下方に移動させて、リード端子６にワイヤ７の他端を超音波熱圧着すると、ワイヤ７は図２（ｂ）に示すように、２個所で屈曲してループ高さが更に低く抑えられる。なお、以上の説明では、ワイヤ７の一端を半導体チップのパッド４にボールボンドする例を示したが、ワイヤ７の一端にボールを生成せず、線径のワイヤのままパッド４に当接して圧着してもよい。
また、パッド４上にバンプを設け、このバンプにワイヤをボールボンドあるいは線径のワイヤのまま圧着するようにしてもよい。
【００１２】
参考の形態３．
次に、この発明の参考の形態３を図にもとづいて説明する。図３は、参考の形態３の構成及び製造方法を説明するための概略図で、封止樹脂は省略している。
この図において、図１と同一または相当部分にはそれぞれ同一符号を付して説明を省略する。図３に示すように、この形態は、半導体チップ２のパッド４上にワイヤ７の一端をボールボンドした後、キャピラリー（図示せず）を反リード端子６側に大きくリバース動作させ、その後、ルーピングを行なって、ワイヤ７の他端をリード端子６に超音波熱圧着するものである。
この結果、ワイヤ７はパッド４の反リード端子側、即ち図３においてパッドの左方で図示のように折り返され、そのままリード端子６に向けて延在するため、ループ高さを更に低くすることができる。なお、以上の説明では、ワイヤ７の一端を半導体チップのパッド４にボールボンドする例を示したが、ワイヤ７の一端にボールを生成せず、線径のワイヤのままパッド４に当接して圧着してもよい。 また、パッド４上にバンプを設け、このバンプにワイヤをボールボンドあるいは線径のワイヤのまま圧着するようにしてもよい。
【００１３】
実施の形態
次に、この発明の実施の形態を図にもとづいて説明する。図４は、実施の形態の構成及び製造方法を説明するための概略図で、封止樹脂は省略している。この図において、図３と同一または相当部分にはそれぞれ同一符号を付して説明を省略する。図４に示すように、この実施の形態は、半導体チップ２のパッド４上にワイヤ７の一端をボールボンドした後、キャピラリー（図示せず）を反リード端子６側、即ち図４においてパッド４の左方に大きくリバース動作させ、その後、ルーピングを行なって、ワイヤ７の他端をリード端子６に超音波熱圧着し、その後、パッド４の上にバンプ５をボンドしてワイヤ７を固定するようにしたものである。この結果、参考の形態３と同様に、ワイヤ７のループ高さを更に低くすることができる。なお、以上の説明では、ワイヤ７の一端を半導体チップのパッド４上にボールボンドする例を示したが、ワイヤ７の一端にボールを生成せず、線径のワイヤのままパッド４に当接して圧着してもよい。また、パッド４上にバンプ５を設け、このバンプにワイヤをボールボンドあるいは線径のワイヤのまま圧着するようにしてもよい。
【００１４】
上述した実施の形態にもとづいてワイヤ７のループ高さを低くすることにより、半導体チップ２を複数個搭載することが可能となり、更に、多機能化を図ることが可能となる。図５は、上述した実施の形態の実施により、半導体チップ２を４個積層して搭載した例を示すものである。
この図において、２２はダイパッド１の一面にダイボンド材３によって裏面が固着された第１の半導体チップ、７２は第１の半導体チップとリード端子６とを接続するワイヤ、２３は第１の半導体チップ２２の回路面にダイボンド材３によって裏面が固着された第２の半導体チップ、７３は第２の半導体チップとリード端子６とを接続するワイヤ、２４はダイパッド１の他面にダイボンド材３によって裏面が固着された第３の半導体チップ、７４は第３の半導体チップとリード端子６とを接続するワイヤ、２５は第３の半導体チップ２４の回路面にダイボンド材３によって裏面が固着された第４の半導体チップ、７５は第４の半導体チップとリード端子６とを接続するワイヤである。
【００１５】
【発明の効果】
この発明に係る半導体装置は、ダイパッドに装着された半導体チップ、この半導体チップと外部回路とを接続するリード端子、上記半導体チップのパッドにボール部が接続され、他端が上記リード端子に接続されると共に、上記パッドよりも、反リード端子側で折り返され、上記折り返された部分と、上記他端との間で、上記ボール部の上に固定されたワイヤ及び上記半導体チップ、パッド、リード端子の一部並びにワイヤを封止する封止樹脂を備えたものであるため、ワイヤのループ高さを低く抑えることができ、パッケージの薄型化が容易となる。
【図面の簡単な説明】
【図１】 この発明の参考の形態１の構成及び製造方法を説明するための概略図である。
【図２】 この発明の参考の形態２の構成及び製造方法を説明するための概略図である。
【図３】 この発明の参考の形態３の構成及び製造方法を説明するための概略図である。
【図４】 この発明の実施の形態の構成及び製造方法を説明するための概略図である。
【図５】 実施の形態にもとづいて複数個の半導体チップを搭載した例を示す構成図である。
【図６】 従来の半導体装置の概略構成を示す断面図である。
【図７】 従来の半導体装置のワイヤの形状を示す概略側面図である。
【図８】 従来の半導体装置の改良案の構成の一例を示す概略図である。
【図９】 従来の半導体装置の改良案の構成の他の一例を示す概略図である。
【図１０】 従来の半導体装置の改良案の構成の更に他の一例を示す概略図である。
【符号の説明】
１ ダイパッド、 ２ 半導体チップ、 ３ ダイボンド材、 ４ パッド、 ５ バンプ、 ６ リード端子、 ７ ワイヤ、 ８ 封止樹脂、 ９キャピラリー。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a configuration for reducing the thickness of a package.
[0002]
[Prior art]
6 and 7 show the configuration of a conventional semiconductor device. FIG. 6 is a cross-sectional view showing a schematic structure of a package. FIG. 7 is a schematic side view showing the shape of a wire connecting a semiconductor chip and a lead terminal. It is. In these drawings, 1 is a die pad, 2 is a semiconductor chip whose back surface is fixed to the die pad 1 via a die bonding material 3, 4 is a connection pad provided on the circuit surface of the semiconductor chip 2, and 6 is a semiconductor chip 2. A lead terminal 7 for connecting the lead wire 6 to the external circuit and a wire 7 such as a gold wire for connecting the pad 4 and the lead terminal 6 of the semiconductor chip. A gold ball 7A generated by melting the tip of the gold wire is capillary (not shown). 7), the capillary is reversely operated to form a bent portion as indicated by 7B in FIG. 6 and FIG. 7, and if necessary, the capillary is reversely operated again. After the second bent portion is formed as shown by 7C, the lead terminal 6 is connected.
[0003]
In this way, the height from the pad 4 to the bent portion 7B of the wire 7 is provided in order to avoid contact between the wire 7 and the edge of the semiconductor chip 2. Reference numeral 8 denotes a sealing resin for sealing the die pad 1, the semiconductor chip 2, the inner ends of the lead terminals 6 and the wires 7. In the conventional semiconductor device described above, since the height from the circuit surface of the semiconductor chip 2 to the bent portion 7B of the wire 7 is about 150 μm or more, the package can be made thin or multi-functional. It was difficult to mount a plurality of semiconductor chips inside. As an improvement plan for this purpose, the configuration or method shown in FIGS. 8 to 10 has been proposed. Hereinafter, these improvement plans will be described.
8 to 10, the same or corresponding parts as those in FIGS. 6 and 7 are denoted by the same reference numerals, and the description thereof is omitted.
[0004]
In the improved plan shown in FIG. 8, when connecting the wire 7 on the bump 5, the tail 71 of the wire 7 protruding from the capillary 9 is suppressed so that its length is 50 μm or less, and the ball is attached to the tip. Without being generated, the wire 5 is brought into contact with the bump 5 as it is and is subjected to ultrasonic thermocompression bonding with the capillary 9. Thereafter, the clamper 10 is loosened and the predetermined amount of the wire 7 is fed out without operating the capillary 9 in the reverse direction, and then the capillary 9 is moved over the arc to be positioned on the lead terminal 6, and the wire 7 is ultrasonically applied to the lead terminal 6. Thermocompression bonding. With this configuration, the loop height of the wire 7 can be suppressed to 50 μm or less.
[0005]
Further, the improvement shown in FIG. 9 is to remove the bumps 5 provided on the pads 4 of the semiconductor chip 2 and directly press the wires 7 onto the pads 4.
The procedure of pressure bonding is the same as that in the case of FIG. In this way, the wire loop height can be further reduced by the height of the bump 5.
[0006]
10 is similar to FIGS. 6 and 7 in that the ball 7A is generated at the tip of the wire 7 and is bonded to the pad 4 of the semiconductor chip 2 in the case of FIG. 6 and FIG. It is intended to suppress the loop height of the wire 7 more. That is, in this case, after the wire 7 is ball bonded to the pad 4 of the semiconductor chip 2, the capillary 9 is moved as it is onto the lead terminal 6 without performing the reverse operation, and the wire 7 is ultrasonically heated to the lead terminal 6. It is to be crimped.
[0007]
[Problems to be solved by the invention]
The conventional semiconductor device and the conventional improvement proposal are configured as described above, and the loop height of the wire can be suppressed to some extent as compared with the configurations of FIGS. 6 and 7, but the package is further thinned. Therefore, there has been a problem that the conventional improvement plan is still not sufficient.
The present invention has been made to address such problems, and an object of the present invention is to provide a semiconductor device capable of further reducing the wire loop height.
[0008]
[Means for Solving the Problems]
In the semiconductor device according to the present invention, a semiconductor chip mounted on a die pad, a lead terminal for connecting the semiconductor chip and an external circuit, a ball portion is connected to the pad of the semiconductor chip, and the other end is connected to the lead terminal. In addition, the wire is folded on the side opposite to the lead terminal than the pad, and is fixed on the ball portion between the folded portion and the other end, and the semiconductor chip, pad, and lead terminal. And a sealing resin for sealing the wire.
[0009]
In the semiconductor device according to the present invention, the semiconductor chip is a stacked body of a plurality of semiconductor chips.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Reference form 1.
Prior to the description of the embodiments of the present invention, reference embodiments will be described with reference to the drawings. FIG. 1 is a schematic diagram for explaining the configuration and manufacturing method of Reference Embodiment 1, and the sealing resin is omitted.
In this figure, the same or corresponding parts as in FIG. Shape status of this is the connection of the semiconductor chip side of the wire 7 performs the ball bond, as shown in FIG. 1 (a), after the one end of the wire 7 and the ball bond to the pads 4 semiconductor chip 2, the capillary 9 is moved upward to A as indicated by a broken line arrow, and thereafter, reverse operation is performed from A to the lead terminal 6 side, that is, to the right side in FIG.
As a result, the wire 7 is inclined so as to connect the position where the ball bond is made to the pad 4 and B. Thereafter, the capillary 9 is moved further upward from B to C as indicated by a broken line arrow, and then reverse from C to the opposite lead terminal side, that is, to the left as indicated by a broken line arrow in FIG. Make it work. As a result, the wire 7 bends at B and tilts in a form connecting B and D. After that, when the capillary 9 is moved to the lower right in FIG. 1 and the other end of the wire 7 is subjected to ultrasonic thermocompression bonding to the lead terminal 6, the wire 7 is bent at two places as shown in FIG. The loop height can be further reduced. In the above description, an example in which one end of the wire 7 is ball-bonded to the pad 4 of the semiconductor chip is shown. However, a ball is not generated at one end of the wire 7 and the wire 4 is in contact with the pad 4 as it is. You may crimp. Alternatively, bumps may be provided on the pads 4 and wires may be pressure-bonded to the bumps as they are with ball bonds or wire diameters.
[0011]
Reference form 2.
Next, will be described with reference to FIG form 2 of reference for the present invention. FIG. 2 is a schematic diagram for explaining the configuration and the manufacturing method of Reference Embodiment 2, and the sealing resin is omitted.
In this figure, the same or corresponding parts as in FIG. Form state this is, as in the first reference, the connection of the wires of the semiconductor chip side and performs the ball bond, as shown in FIG. 2 (a), one end of the wire 7 to the pad 4 the semiconductor chip 2 After the ball bonding, the capillary 9 is moved upward to A as indicated by a broken line arrow, and then from A to the lead terminal 6 side, that is, to the right as indicated by a broken line arrow to the right in FIG. Reverse operation is performed. As a result, the wire 7 is inclined so as to connect the position where the ball bond is made to the pad 4 and B. Thereafter, the capillary 9 is moved further upward from B to C as indicated by a broken line arrow, and then further reversely from C to E as indicated by a broken line arrow to the lead terminal side, that is, to the right in FIG. Make it work.
As a result, the wire 7 bends at B and tilts in a form connecting B and E. After that, when the capillary 9 is moved to the lower right in FIG. 2 and the other end of the wire 7 is subjected to ultrasonic thermocompression bonding to the lead terminal 6, the wire 7 is bent at two places as shown in FIG. The loop height is further reduced. In the above description, an example in which one end of the wire 7 is ball-bonded to the pad 4 of the semiconductor chip is shown. However, a ball is not generated at one end of the wire 7 and the wire 4 is in contact with the pad 4 as it is. You may crimp.
Alternatively, bumps may be provided on the pads 4 and wires may be pressure-bonded to the bumps as they are with ball bonds or wire diameters.
[0012]
Reference form 3.
Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a schematic diagram for explaining the configuration and manufacturing method of Reference Embodiment 3, and the sealing resin is omitted.
In this figure, the same or corresponding parts as in FIG. As shown in FIG. 3, the shape condition of this, after the end of the wire 7 on the pad 4 the semiconductor chip 2 and the ball bond, capillary (not shown) was significantly reverse operation in the counter-lead terminal 6 side, then The other end of the wire 7 is ultrasonically thermocompression bonded to the lead terminal 6 by looping.
As a result, the wire 7 is folded back as shown in the figure on the opposite lead terminal side of the pad 4, that is, on the left side of the pad in FIG. 3, and extends toward the lead terminal 6 as it is, so that the loop height is further reduced. Can do. In the above description, an example in which one end of the wire 7 is ball-bonded to the pad 4 of the semiconductor chip is shown. However, a ball is not generated at one end of the wire 7 and the wire 4 is in contact with the pad 4 as it is. You may crimp. Alternatively, bumps may be provided on the pads 4 and wires may be pressure-bonded to the bumps as they are with ball bonds or wire diameters.
[0013]
Form state of implementation will be described with reference to FIG shape condition of the present invention. Figure 4 is a schematic view for explaining the structure and manufacturing method of the form status of implementation, the sealing resin is omitted. In this figure, the same or corresponding parts as in FIG. As shown in FIG. 4, in this embodiment, after one end of the wire 7 is ball-bonded on the pad 4 of the semiconductor chip 2, the capillary (not shown) is connected to the side opposite to the lead terminal 6, that is, the pad 4 in FIG. The wire 7 is then reversely operated to the left and then looped, and the other end of the wire 7 is ultrasonically thermocompression bonded to the lead terminal 6. Thereafter, the bump 5 is bonded onto the pad 4 to fix the wire 7. It is what I did. As a result, in the same manner as in Reference Embodiment 3, the loop height of the wire 7 can be further reduced. In the above description, an example in which one end of the wire 7 is ball-bonded on the pad 4 of the semiconductor chip is shown. However, a ball is not generated at one end of the wire 7 and the wire 4 is in contact with the pad 4 as it is. May be crimped. Alternatively, bumps 5 may be provided on the pads 4, and wires may be bonded to the bumps with ball bonds or wires having a diameter.
[0014]
By reducing the loop height of the wire 7 based on the form of implementation described above, it is possible to a plurality mounting the semiconductor chip 2, further, it is possible to achieve multiple functions. 5, the implementation of the form status of implementation described above, it illustrates an example of mounting the semiconductor chip 2 4 laminated to.
In this figure, 22 is a first semiconductor chip whose back surface is fixed to one surface of a die pad 1 by a die bonding material 3, 72 is a wire for connecting the first semiconductor chip and the lead terminal 6, and 23 is a first semiconductor chip. 22 is a second semiconductor chip whose back surface is fixed to the circuit surface by the die bond material 3, 73 is a wire connecting the second semiconductor chip and the lead terminal 6, and 24 is a back surface by the die bond material 3 on the other surface of the die pad 1. Is a third semiconductor chip to which is fixed, 74 is a wire for connecting the third semiconductor chip and the lead terminal 6, and 25 is a fourth whose rear surface is fixed to the circuit surface of the third semiconductor chip 24 by the die bonding material 3. The semiconductor chip 75 is a wire for connecting the fourth semiconductor chip and the lead terminal 6.
[0015]
【The invention's effect】
In the semiconductor device according to the present invention, a semiconductor chip mounted on a die pad, a lead terminal for connecting the semiconductor chip and an external circuit, a ball portion is connected to the pad of the semiconductor chip, and the other end is connected to the lead terminal. In addition, the wire is folded on the side opposite to the lead terminal than the pad, and is fixed on the ball portion between the folded portion and the other end, and the semiconductor chip, pad, and lead terminal. Since part of the wire and the sealing resin for sealing the wire are provided, the loop height of the wire can be kept low, and the package can be easily thinned.
[Brief description of the drawings]
1 is a schematic diagram for explaining the structure and manufacturing method of Reference Embodiment 1 of the present invention.
Figure 2 is a schematic diagram for explaining the structure and manufacturing method of Reference Embodiment 2 of the present invention.
Figure 3 is a schematic diagram for explaining the structure and manufacturing method of Reference Embodiment 3 of the present invention.
Figure 4 is a schematic diagram for explaining the structure and manufacturing method of the form status of the present invention.
5 is a block diagram showing an example of mounting a plurality of semiconductor chips based on the form of implementation.
FIG. 6 is a cross-sectional view showing a schematic configuration of a conventional semiconductor device.
FIG. 7 is a schematic side view showing a shape of a wire of a conventional semiconductor device.
FIG. 8 is a schematic diagram showing an example of a configuration of a conventional improvement plan of a semiconductor device.
FIG. 9 is a schematic view showing another example of the configuration of the improvement plan of the conventional semiconductor device.
FIG. 10 is a schematic view showing still another example of the configuration of a conventional proposal for improving a semiconductor device.
[Explanation of symbols]
1 die pad, 2 semiconductor chip, 3 die bond material, 4 pad, 5 bump, 6 lead terminal, 7 wire, 8 sealing resin, 9 capillary.

Claims (2)

ダイパッドに装着された半導体チップ、この半導体チップと外部回路とを接続するリード端子、上記半導体チップのパッドにボール部が接続され、他端が上記リード端子に接続されると共に、上記パッドよりも、反リード端子側で折り返され、上記折り返された部分と、上記他端との間で、上記ボール部の上に固定されたワイヤ及び上記半導体チップ、パッド、リード端子の一部並びにワイヤを封止する封止樹脂を備えた半導体装置。  A semiconductor chip mounted on a die pad, a lead terminal for connecting the semiconductor chip and an external circuit, a ball portion is connected to the pad of the semiconductor chip, the other end is connected to the lead terminal, and more than the pad, Folded on the side opposite to the lead terminal, and the wire fixed on the ball part and the semiconductor chip, the pad, a part of the lead terminal and the wire are sealed between the folded portion and the other end A semiconductor device provided with a sealing resin. 上記半導体チップは、複数個の半導体チップの積層体であることを特徴とする請求項１記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the semiconductor chip is a stacked body of a plurality of semiconductor chips.
JP2002182099A 2002-06-21 2002-06-21 Semiconductor device Expired - Fee Related JP3923379B2 (en)

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