JP2011023768A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
JP2011023768A
JP2011023768A JP2010248251A JP2010248251A JP2011023768A JP 2011023768 A JP2011023768 A JP 2011023768A JP 2010248251 A JP2010248251 A JP 2010248251A JP 2010248251 A JP2010248251 A JP 2010248251A JP 2011023768 A JP2011023768 A JP 2011023768A
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Japan
Prior art keywords
chip
wire
bonding
solder
power transistor
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JP2010248251A
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Japanese (ja)
Inventor
Masaaki Koyama
正晃 小山
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Fuji Electric Co Ltd
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Fuji Electric Systems Co Ltd
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Application filed by Fuji Electric Systems Co Ltd filed Critical Fuji Electric Systems Co Ltd
Priority to JP2010248251A priority Critical patent/JP2011023768A/en
Publication of JP2011023768A publication Critical patent/JP2011023768A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that mounts a plurality of semiconductor components on the same substrate to receive the semiconductor components in a compact package, has the controlled, stabilized loop height and loop geometry of each wire connection, and improves an adhesion between the semiconductor components. <P>SOLUTION: A metal thin wire 9 is connected at a given wire length while being clamped with a clamp mechanism 34 before proceeding to a second bonding step after a first bonding step. An amount of pulling out the metal thin wire 9 is stabilized utilizing an active clamp function, which is an added function of a wedge bonder 30, in order to stabilize the loop geometry of a connecting wire when the wire is pull out after the first bonding step has finished. The method is also capable of stabilizing the loop geometry formed by the metal thin wire 9. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体チップを半田接合によって金属製のリードフレームの所定位置にマウントされた半導体装置の製造方法に関し、とくに出力段パワートランジスタチップの上に制御用のＩＣチップを積層して配置し、所定の配線用ワイヤによってリードフレーム、出力段パワートランジスタチップ、またはＩＣチップの間を電気的に接続する半導体装置の製造方法に関する。   The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor chip is mounted at a predetermined position of a metal lead frame by solder bonding, and in particular, a control IC chip is stacked on an output stage power transistor chip and arranged. The present invention relates to a method for manufacturing a semiconductor device in which a lead frame, an output stage power transistor chip, or an IC chip are electrically connected by a predetermined wiring wire.

従来では、ディスクリート製品は１パッケージに１素子、あるいは同一半導体基板（同電位上）に数チップが搭載され、それらを配線用ワイヤによってパッケージの外部端子（アウタリード）とチップ電極とを結線する製品が主流であった。しかしながら、とくに自動車電装部品の分野においては、各種部品の電子化が進んでいて、近年では高電流／低抵抗のパワートランジスタのような半導体装置が多数採用されている。そのため、負荷短絡、過熱保護等の付加機能を有する半導体装置が必要とされることとなって、半導体装置の低損失化や小型パッケージ化の要求が強くなっている。   Conventionally, a discrete product is a product in which one element is mounted in one package or several chips are mounted on the same semiconductor substrate (on the same potential), and the external terminals (outer leads) of the package and chip electrodes are connected by wiring wires. It was mainstream. However, in the field of automotive electrical components, in particular, various components have been digitized, and in recent years, many semiconductor devices such as high current / low resistance power transistors have been adopted. For this reason, a semiconductor device having additional functions such as load short-circuiting and overheat protection is required, and there is an increasing demand for lower loss and smaller packaging of the semiconductor device.

小型パッケージ化された製品の一例として、後述する特許文献１には、車載エンジンの点火装置としてのイグナイタなどにおいて、スイッチング用のパワートランジスタとそのトランジスタを駆動するための回路素子とを備えた電子装置に関する発明が記載されている。すなわち、イグナイタは、基板としてのリードフレームと、第１のチップと、第２のチップとを備え、リードフレーム上に第１のチップが半田にて接合されるとともに、第１のチップ上には第２のチップがフリップチップ方式にて三次元実装されている。   As an example of a small packaged product, Patent Document 1 described later discloses an electronic device including a switching power transistor and a circuit element for driving the transistor in an igniter as an ignition device for an in-vehicle engine. The invention is described. In other words, the igniter includes a lead frame as a substrate, a first chip, and a second chip. The first chip is joined to the lead frame by solder, and the first chip is mounted on the first chip. The second chip is three-dimensionally mounted by a flip chip method.

このように、パワートランジスタを形成した第１のチップ上に、そのトランジスタを駆動するための回路素子を形成した第２のチップを積み重ねて配置することによって、セラミック基板上にパワートランジスタと回路素子を平面配置した従来のイグナイタと比較して、投影面積（上部から見た面積）を小さくでき、製品の小型化を図ることができる。   In this way, the power transistor and the circuit element are arranged on the ceramic substrate by stacking and arranging the second chip on which the circuit element for driving the transistor is stacked on the first chip on which the power transistor is formed. Compared to a conventional igniter arranged in a plane, the projected area (area viewed from above) can be reduced, and the product can be downsized.

図２は、一般的なチップオンチップ（ＣＯＣ）構成の半導体装置を示す断面構造図である。
基板となる金属製のリードフレーム１上には、パワートランジスタ２を導電性の接合部材、たとえば半田層３により接合され、その後に制御用のＩＣチップ４が絶縁性接着剤５（あるいは導電性接着剤）によって接合されている。さらに、超音波および熱圧着を併用して、アルミニウムまたは金線等の金属細線６によって、パワートランジスタ２とリードフレーム１に対して外部端子となるアウタリード７との間が結線されている。また、金属細線６よりさらに細い金属細線８によって、パワートランジスタ２とＩＣチップ４の電極間が接続され、さらに金属細線９によってＩＣチップ４の電極とアウタリード７との間も接続されている。 FIG. 2 is a cross-sectional structure diagram illustrating a semiconductor device having a general chip-on-chip (COC) configuration.
A power transistor 2 is bonded to a metal lead frame 1 serving as a substrate by a conductive bonding member, for example, a solder layer 3, and then a control IC chip 4 is connected to an insulating adhesive 5 (or conductive bonding). Agent). Furthermore, the power transistor 2 and the outer lead 7 serving as an external terminal with respect to the lead frame 1 are connected to each other by a thin metal wire 6 such as aluminum or gold wire by using ultrasonic waves and thermocompression bonding. In addition, the power transistor 2 and the electrode of the IC chip 4 are connected by a fine metal wire 8 that is thinner than the fine metal wire 6, and the electrode of the IC chip 4 and the outer lead 7 are also connected by a fine metal wire 9.

こうしたパワートランジスタ２に、その制御用のＩＣチップ４が積層されたチップオンチップ構成の半導体装置では、第１の半導体素子（パワートランジスタ２）が反った状態で第２の半導体素子（ＩＣチップ４）を第１の半導体素子上に搭載すると、半導体素子どうしを全面にわたって均一に接着させることが困難となり、あるいはチップ接合面に間隙が生じることがあり、樹脂硬化後に半導体素子間で剥離が生じるおそれがあった。また、チップ接合面に間隙や剥離があると、第２の半導体素子の電極に金属細線６をボンディングする際に、ボンディング荷重や超音波振動のエネルギー等、接合エネルギーが分散されるために、安定して金属細線６を第２の半導体素子の電極に接合できなくなる。   In a semiconductor device having a chip-on-chip configuration in which the control IC chip 4 is stacked on the power transistor 2, the second semiconductor element (IC chip 4) with the first semiconductor element (power transistor 2) warped. ) Is mounted on the first semiconductor element, it may be difficult to uniformly bond the semiconductor elements over the entire surface, or a gap may be formed on the chip bonding surface, which may cause separation between the semiconductor elements after resin curing. was there. In addition, if there is a gap or separation on the chip bonding surface, bonding energy such as bonding load and ultrasonic vibration energy is dispersed when bonding the fine metal wire 6 to the electrode of the second semiconductor element. As a result, the metal thin wire 6 cannot be bonded to the electrode of the second semiconductor element.

特許文献２には、そのような問題に対処するための新規の半導体装置の製造方法の発明が記載されている。この発明は、配線基板と第１の半導体素子とを接着する第１の樹脂を軟化させ、第１の半導体素子の反りを解消させた状態で半導体素子どうしを全面にわたって接着したものである。これによって、ワイヤボンディング時の接合エネルギーの分散を防止して、安定した金属細線の接合を確保できるとともに、半導体素子どうしの間に形成した第２の樹脂の亀裂発生を防止している。   Patent Document 2 describes an invention of a novel method for manufacturing a semiconductor device to cope with such a problem. According to the present invention, the first resin for bonding the wiring board and the first semiconductor element is softened, and the semiconductor elements are bonded to each other in a state where the warp of the first semiconductor element is eliminated. Accordingly, dispersion of bonding energy during wire bonding can be prevented, stable metal thin wire bonding can be secured, and cracking of the second resin formed between the semiconductor elements can be prevented.

特開２００１−１６８２７１号公報（〔００１２〕〜〔００２２〕、図２）JP 2001-168271 A ([0012] to [0022], FIG. 2) 特開２００２−２５２３２６号公報（〔００１２〕〜〔００２３〕）JP 2002-252326 A ([0012] to [0023])

ところが、従来のパワートランジスタの半田接合方法には、以下の問題があった。
図２の半導体装置において、基板上に搭載されるパワートランジスタの素子面積は大型化しており、従来のダイボンディング装置によるマウント方法では、素子以外の領域に接合材がはみ出し、かつ接合材の厚みも不均一でコントロールできないという不具合が発生している。 However, the conventional power transistor soldering method has the following problems.
In the semiconductor device of FIG. 2, the element area of the power transistor mounted on the substrate is increased, and in the mounting method using the conventional die bonding apparatus, the bonding material protrudes into a region other than the element, and the thickness of the bonding material also increases. There is a problem that it is uneven and cannot be controlled.

自動車電装部品としての半導体装置が置かれている環境は、近年になって高温化が進み、適用環境における高耐熱性が要求されるようになっている。また、半田の鉛フリー化で融点の高い半田を使用することにより、実装温度が約２０℃も上昇している。   The environment in which a semiconductor device as an automobile electrical component is placed has been increased in temperature in recent years, and high heat resistance in an application environment is required. In addition, the soldering temperature is increased by about 20 ° C. due to the use of solder having a high melting point by making the solder lead-free.

このような状況下では、前述の半田のはみ出し、および半田厚の不均一さは、封止材との密着を大幅に妨げ、耐湿性および対熱応力性の低下の大きな要因となっている。
ＩＣチップの接着剤による接合方法についても、以下の問題があった。 Under such circumstances, the protrusion of the solder and the non-uniformity of the solder thickness greatly hinder the close contact with the sealing material, and are a major factor in lowering the moisture resistance and heat stress resistance.
The bonding method using an IC chip adhesive also has the following problems.

パワートランジスタ上へのＩＣチップの接合では、一般的に熱硬化性の有機材料が用いられている。しかし、硬化キュア時に発生するアウトガス付着によるワイヤボンディング性の低下や素子電極の腐食が進行（耐腐食性低下）し、接着剤の位置ずれや染み出しによってもワイヤボンディング性の低下や実装面積の縮小化が生じ、さらには接着剤内のボイドや接着剤の厚み不均一による絶縁性の低下などが問題となる。   In joining an IC chip onto a power transistor, a thermosetting organic material is generally used. However, deterioration of wire bonding due to adhesion of outgas generated during curing and progress of corrosion of device electrodes (decrease in corrosion resistance), and deterioration of wire bonding and reduction of mounting area due to misalignment and leakage of adhesive. In addition, voids in the adhesive and deterioration of insulation due to uneven thickness of the adhesive become a problem.

また、接着剤をチップ接合部の全面にわたって添着させて、それを確実に硬化させておかないと、ＩＣチップ上で金属細線をワイヤボンディングして結線するときに、ボンディングツールに超音波が伝わると同時に、素子そのものが同期してしまい、素子電極面とワイヤ間での摩擦が生じず、結果として凝固現象が起こらないで、不安定な接合につながる問題がある。   In addition, if the adhesive is not applied to the entire surface of the chip joint, and it is not hardened, the ultrasonic wave will be transmitted to the bonding tool when wire-bonding the fine metal wires on the IC chip. At the same time, the elements themselves are synchronized, there is no friction between the element electrode surface and the wire, and as a result, there is a problem that solidification does not occur and leads to unstable bonding.

さらに、ワイヤボンディングによる結線方法についても、下記の問題があった。
大電流化（低オン抵抗化）、およびパッケージの小型化による高密度実装可能な製品ができるというＣＯＣ構造のメリットについては前述したが、このような目標を達成するには、出力側端子への結線材は太線化・多数掛け化が必要不可欠である。一方、制御用ＩＣとの間の結線には、搭載チップサイズ等の制約があって、ワイヤボンディングの細線化が必要であり、またＩＣチップとパワートランジスタを直接結線することも必要である。また、自動車電装部品としての半導体装置を小型パッケージ化するためには、結線のループ高さ、およびループ形状をコントロールし、そのワイヤ結線を安定させることも求められている。 Furthermore, the wire bonding method has the following problems.
As described above, the advantages of the COC structure that enables high current mounting (low on-resistance) and high-density mounting by reducing the size of the package are described above. It is indispensable to use thick wires and multiple wires for the connecting material. On the other hand, the connection with the control IC has restrictions such as the size of the mounted chip, so that it is necessary to make the wire bonding thinner, and it is also necessary to directly connect the IC chip and the power transistor. In addition, in order to make a semiconductor device as an automobile electrical component into a small package, it is also required to stabilize the wire connection by controlling the loop height and loop shape of the connection.

本発明はこのような点に鑑みてなされたものであり、複数の半導体素子を同一基板に搭載することによって小型パッケージに収納される半導体装置であって、ワイヤ結線のループ高さ、およびループ形状をコントロールし、かつ安定させた半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of the above points, and is a semiconductor device that is housed in a small package by mounting a plurality of semiconductor elements on the same substrate, the loop height of the wire connection, and the loop shape It is an object of the present invention to provide a method for manufacturing a semiconductor device that controls and stabilizes.

本発明では、上記問題を解決するために、半導体チップを半田接合によって金属製のリードフレームの所定位置にマウントし、前記半導体チップにＩＣチップをさらに積層して配置し、前記リードフレーム、前記半導体チップ、または前記ＩＣチップの間を電気的に接続する半導体装置の製造方法が提供される。この半導体装置の製造方法は、前記リードフレーム、前記半導体チップ、または前記ＩＣチップのボンディング位置に配線用ワイヤを超音波接合する第１のボンディング工程と、前記配線用ワイヤをキャピラリから所定長さだけ引き出した後に、前記キャピラリをワイヤクランプ状態にして前記リードフレーム、前記半導体チップ、または前記ＩＣチップの別のボンディング位置に移動するワイヤ引き出し工程と、前記別のボンディング位置で前記配線用ワイヤの他端を超音波接合する第２のボンディング工程と、を含むことを特徴とする。   In the present invention, in order to solve the above problem, a semiconductor chip is mounted at a predetermined position of a metal lead frame by solder bonding, and an IC chip is further stacked on the semiconductor chip, and the lead frame, the semiconductor A method of manufacturing a semiconductor device that electrically connects chips or the IC chips is provided. The semiconductor device manufacturing method includes a first bonding step of ultrasonically bonding a wiring wire to a bonding position of the lead frame, the semiconductor chip, or the IC chip, and the wiring wire from the capillary by a predetermined length. A wire pulling process in which the capillary is brought into a wire clamped state after being pulled and moved to another bonding position of the lead frame, the semiconductor chip, or the IC chip; and the other end of the wiring wire at the other bonding position And a second bonding step for ultrasonic bonding.

本発明の半導体装置の製造方法によれば、接合材の厚みを均一にコントロールして、小型パッケージ化された半導体装置において、ワイヤ結線のループ高さ、およびループ形状をコントロールし、かつ安定させることができる。   According to the semiconductor device manufacturing method of the present invention, the thickness of the bonding material is uniformly controlled to control and stabilize the wire connection loop height and loop shape in a small packaged semiconductor device. Can do.

実施の形態に係る半導体装置のダイボンディング装置を示す図である。It is a figure which shows the die bonding apparatus of the semiconductor device which concerns on embodiment. 一般的なチップオンチップ（ＣＯＣ）構成の半導体装置を示す断面構造図である。1 is a cross-sectional structure diagram illustrating a semiconductor device having a general chip-on-chip (COC) configuration. 半田形状整形用の叩き工具を示す底面図、およびその側面断面図である。It is the bottom view which shows the tap tool for solder shape shaping, and its side surface sectional drawing. 図３に示す叩き工具によって圧延された半田の形状を示す図である。It is a figure which shows the shape of the solder rolled by the hitting tool shown in FIG. 従来のダイボンディング装置、およびチップ領域以外の部分に接合材がはみ出した様子を示す図である。It is a figure which shows a mode that the joining material protruded into parts other than the conventional die-bonding apparatus and a chip | tip area | region. 本発明の半田接合方法によりリードフレーム上にマウントされたパワートランジスタの顕微鏡写真を示す図である。It is a figure which shows the microscope picture of the power transistor mounted on the lead frame by the soldering method of this invention. 半導体ウェハーの裏面に接着剤フィルムを貼り付けてマウントする工程を示す図である。It is a figure which shows the process of affixing an adhesive film on the back surface of a semiconductor wafer, and mounting. 熱硬化型ポリイミドフィルムの吸発熱曲線の一例を示す図である。It is a figure which shows an example of the heat absorption-and-exotherm curve of a thermosetting polyimide film. パワートランジスタにポリイミドフィルムを接着した接着部の顕微鏡写真を示す図である。It is a figure which shows the microscope picture of the adhesion part which adhere | attached the polyimide film on the power transistor. 本発明のワイヤボンディングによる結線方法を示す説明図である。It is explanatory drawing which shows the connection method by the wire bonding of this invention.

以下、図面を参照してこの発明の実施の形態について、半導体チップの半田接合方法、接着剤によるＩＣチップの接合方法、およびワイヤボンディングによる結線方法のそれぞれを順次に説明する。ここでは、図２に示すチップオンチップ（ＣＯＣ）構成の半導体装置の一例として、出力段のパワートランジスタを構成する半導体チップの上に制御用ＩＣチップが積層配置された半導体装置について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings in order of a solder bonding method for semiconductor chips, a bonding method for IC chips using an adhesive, and a connection method using wire bonding. Here, as an example of a semiconductor device having a chip-on-chip (COC) structure shown in FIG. 2, a semiconductor device in which a control IC chip is stacked on a semiconductor chip constituting a power transistor in an output stage will be described.

（１）パワートランジスタの半田接合方法
最初に、半導体チップ（パワートランジスタ）を金属製のリードフレームの所定位置に、半田接合によってマウントする半田接合方法について説明する。 (1) Power Transistor Solder Joining Method First, a solder joining method for mounting a semiconductor chip (power transistor) on a predetermined position of a metal lead frame by solder joining will be described.

図１は、実施の形態に係る半導体装置のダイボンディング装置を示す図である。このダイボンディング装置は、リードフレーム１をタクト搬送するための搬送機構であるヒータレール１１、このヒータレール１１の上流でリードフレーム１上に半田１２を供給する半田供給手段１３、供給された半田１２ａをリードフレーム１の上方から押圧整形する押圧手段１４、およびリードフレーム１に還元性雰囲気中でパワートランジスタ２をマウントするマウント手段１５によって構成される。   FIG. 1 is a diagram illustrating a die bonding apparatus for a semiconductor device according to an embodiment. This die bonding apparatus includes a heater rail 11 which is a transport mechanism for tact transporting the lead frame 1, solder supply means 13 for supplying solder 12 onto the lead frame 1 upstream of the heater rail 11, and supplied solder 12a. Is formed by pressing means 14 for pressing and shaping from above the lead frame 1 and mounting means 15 for mounting the power transistor 2 on the lead frame 1 in a reducing atmosphere.

ここで半田供給手段１３は、供給部１３ａと半田押出しツール（図示せず）から構成されている。ここでは、接合部材の最小半田厚を３０〔μｍ〕以上に形成するために、溶融状態で定量の半田１２が半田押出しツールからリードフレーム１の所定位置に供給される。このとき、パワートランジスタ２の寸法が４．３×３．６〔ｍｍ〕の大きさであって、金属製のリードフレーム１上に平均半田厚さ７５〔μｍ〕の半田層３を形成して、パワートランジスタ２を接合するような設定であれば、そのために必要な半田１２ａの体積としては、４．３×３．６×０．０７５＝１．１６１〔ｍｍ3〕のように計算することができる。 Here, the solder supply means 13 includes a supply unit 13a and a solder extrusion tool (not shown). Here, in order to form the minimum solder thickness of the joining member to 30 [μm] or more, a certain amount of solder 12 is supplied from a solder extrusion tool to a predetermined position of the lead frame 1 in a molten state. At this time, the size of the power transistor 2 is 4.3 × 3.6 [mm], and the solder layer 3 having an average solder thickness of 75 [μm] is formed on the metal lead frame 1. If the setting is such that the power transistor 2 is joined, the volume of the solder 12a necessary for that is calculated as 4.3 × 3.6 × 0.075 = 1.161 [mm 3 ]. Can do.

ヒータレール１１の中流には押圧手段１４が設けられている。この押圧手段１４は、カム形式またはサーボモータ駆動により上下に駆動される加圧工具１４ａの下面に、叩き工具１４ｂが取り付けられている。ここでは、叩き工具１４ｂがリードフレーム１の表面まで上下移動して、リードフレーム１上に供給されたＳｎ−Ｐｂ系の半田１２ａを押圧整形する。これによって、半田１２ａはパワートランジスタ２の素子形状に相似する形状であって、パワートランジスタ２の接合面積を越えない広さに圧延される。   A pressing means 14 is provided in the middle of the heater rail 11. The pressing means 14 has a hitting tool 14b attached to the lower surface of a pressurizing tool 14a that is driven up and down by a cam type or servo motor drive. Here, the striking tool 14b moves up and down to the surface of the lead frame 1 to press and shape the Sn—Pb solder 12a supplied onto the lead frame 1. As a result, the solder 12 a has a shape similar to the element shape of the power transistor 2 and is rolled to a size not exceeding the junction area of the power transistor 2.

つぎに、叩き工具１４ｂの形状について説明する。
図３（ａ）は、半田形状整形用の叩き工具を示す底面図、同図（ｂ）はその側面断面図である。叩き工具１４ｂは、パワートランジスタ２と同様の矩形断面をなす直方体によって構成され、その断面積はチップサイズより小さく、かつその底面部には所定面積の開口部１４１が形成されている。また、この叩き工具１４ｂの上部には、加圧工具１４ａの底部の挿入穴に嵌合可能な突起部１４２が設けられている。 Next, the shape of the hitting tool 14b will be described.
FIG. 3A is a bottom view showing a tapping tool for shaping the solder shape, and FIG. 3B is a side sectional view thereof. The hitting tool 14b is configured by a rectangular parallelepiped having the same rectangular cross section as that of the power transistor 2, and its cross-sectional area is smaller than the chip size, and an opening 141 having a predetermined area is formed on the bottom surface thereof. In addition, a protrusion 142 that can be fitted into the insertion hole in the bottom of the pressing tool 14a is provided on the top of the hitting tool 14b.

ここで、叩き工具１４ｂの開口部１４１は、その開口面積がパワートランジスタ２の接合面積の５０％から９０％の範囲内に設定されていることが好ましい。具体的には、リードフレーム１の表面、およびパワートランジスタ２のチップ裏面での半田１２ａの濡れ性を考慮して、接合面積の７５％程度に設計されている。すなわち、図３に示すように、この叩き工具１４ｂの底面形状は、０．１〔ｍｍ〕幅の縁部を備えた矩形凹部をなしており、その有効開口面積は３．８×３．１〔ｍｍ〕となっている。また、必要半田量が１．１６１〔ｍｍ3〕であることから、開口部１４１の矩形凹部は０．１〔ｍｍ〕の深さが必要である。 Here, the opening 141 of the hitting tool 14b preferably has an opening area set in a range of 50% to 90% of the bonding area of the power transistor 2. Specifically, in consideration of the wettability of the solder 12a on the surface of the lead frame 1 and the chip back surface of the power transistor 2, it is designed to be about 75% of the bonding area. That is, as shown in FIG. 3, the bottom shape of the tapping tool 14b is a rectangular recess having an edge with a width of 0.1 [mm], and the effective opening area is 3.8 × 3.1. [Mm]. Further, since the necessary solder amount is 1.161 [mm 3 ], the rectangular recess of the opening 141 needs to have a depth of 0.1 [mm].

こうした叩き工具１４ｂを加圧工具１４ａの下部に取り付けて、半田１２ａがリードフレーム１上で繰り返し叩かれることにより、パワートランジスタ２との接合面積の７５％程度の広さにまで圧延される。なお、このような叩き工具１４ｂは、リードフレーム１と繰り返し接触するものであるから、超硬製の金属で構成されていることが好ましい。また、上述したような箱型の額縁形状のものであれば、その耐久性を考慮するとき、縁部の幅はその材質にもよるが０．１〔ｍｍ〕以上が妥当である。   The hitting tool 14b is attached to the lower part of the pressing tool 14a, and the solder 12a is repeatedly hit on the lead frame 1 to be rolled to a size of about 75% of the joining area with the power transistor 2. In addition, since such a hitting tool 14b repeatedly contacts the lead frame 1, it is preferable that the hitting tool 14b is made of a hard metal. Further, in the case of the box-shaped frame shape as described above, when considering the durability, the width of the edge portion is appropriate to be 0.1 [mm] or more although it depends on the material.

図４には、図３に示す叩き工具１４ｂによって圧延された半田１２ａの形状を示している。図４（ａ）には半田１２ａの平面的な広がりを、同図（ｂ）にはその断面高さを示す。   FIG. 4 shows the shape of the solder 12a rolled by the hitting tool 14b shown in FIG. FIG. 4A shows a planar spread of the solder 12a, and FIG. 4B shows the cross-sectional height thereof.

ここに示すように、半田１２ａがＳｎ−Ｐｂ系の半田である場合、パワートランジスタ２のマウント以前での断面形状は、表面張力の関係からなお円弧形状をなしているものの、そのピーク高さは、叩き工具１４ｂに形成された凹部深さの約１．８倍の高さ（＝０．１８ｍｍ）になることが実験的に明らかにされている。この点に関しては、Ｓｎ−Ｓｂ系、あるいはＳｎ−Ａｇ系の半田を用いた場合であっても、ほぼ同様の形状となることが知られている。   As shown here, when the solder 12a is Sn-Pb solder, the cross-sectional shape before mounting the power transistor 2 is still an arc shape due to the surface tension, but the peak height is It has been experimentally clarified that the height (= 0.18 mm) is about 1.8 times the depth of the recess formed in the hitting tool 14b. With regard to this point, it is known that the same shape is obtained even when Sn—Sb or Sn—Ag solder is used.

つぎに、リードフレーム１はマウント手段１５に搬送される。このマウント手段１５は、コレット１６とその昇降ユニット（図示せず）から構成され、窒素ガスと水素ガスを混合した還元性雰囲気中で動作する。マウント工程では、パワートランジスタ２がコレット１６により真空吸着され、その接合面が半田高さの５０〜６０％の位置で保持されるように、リードフレーム１の上で停止位置が設定され、リードフレーム１上の所定位置にパワートランジスタ２がマウントされる。   Next, the lead frame 1 is conveyed to the mounting means 15. The mounting means 15 is composed of a collet 16 and its elevating unit (not shown), and operates in a reducing atmosphere in which nitrogen gas and hydrogen gas are mixed. In the mounting process, the stop position is set on the lead frame 1 so that the power transistor 2 is vacuum-sucked by the collet 16 and the joint surface is held at a position of 50 to 60% of the solder height. A power transistor 2 is mounted at a predetermined position on 1.

このマウント工程では、パワートランジスタ２のマウント高さを適切に設定することによって、以下の不都合が生じないようにすることが必要である。すなわち、マウント高さを低めに設定すると、半田のはみ出しが起こるだけでなく、半田層３の厚みが薄く、かつ不均一になってしまう。また、反対にマウント高さを高めに設定した場合は、マウントされるパワートランジスタ２の半田層３との接触面積が減少し、矩形のチップコーナ部分で未接合が発生し、さらにはパワートランジスタ２が傾くことによって、半田層３の厚みに不均一が発生する。ここでは、半田高さが０．１８〔ｍｍ〕であれば、チップ下面の停止位置をフレーム面の上方０．０９〜０．１１〔ｍｍ〕に設定することで、安定したマウント状態を確保できる。   In this mounting process, it is necessary to prevent the following inconveniences by appropriately setting the mounting height of the power transistor 2. That is, if the mount height is set low, not only the solder will protrude, but the thickness of the solder layer 3 will be thin and non-uniform. On the other hand, when the mount height is set high, the contact area of the power transistor 2 to be mounted with the solder layer 3 is reduced, non-bonding occurs at the rectangular chip corner, and further the power transistor 2 As a result, the thickness of the solder layer 3 becomes non-uniform. Here, if the solder height is 0.18 [mm], a stable mounting state can be secured by setting the stop position of the lower surface of the chip to 0.09 to 0.11 [mm] above the frame surface. .

また、リードフレーム１上の半田層３は、もともとパワートランジスタ２のチップサイズよりも半田広がりが小さく、ＣｕおよびＮｉメッキが施されているリードフレーム１では、半田濡れ性が劣る場合がある。そこで、パワートランジスタ２をスクラブすることによって半田濡れ性を確保する必要がある。   Further, the solder layer 3 on the lead frame 1 originally has a smaller solder spread than the chip size of the power transistor 2, and the lead frame 1 on which Cu and Ni plating are applied may have poor solder wettability. Therefore, it is necessary to ensure solder wettability by scrubbing the power transistor 2.

パワートランジスタ２のスクラブを実施するには、様々な方法が適用できる。ここでは、コレット１６に保持されたパワートランジスタ２の形状にあわせて、スクウェア仕様のスクラブが最適である。なお、パワートランジスタ２のチップ裏面には、通常ＡｕまたはＡｇ蒸着が施されているので、とくに問題はない。   Various methods can be applied to scrub the power transistor 2. Here, in accordance with the shape of the power transistor 2 held in the collet 16, a square scrub is optimal. In addition, since Au or Ag vapor deposition is normally performed on the chip back surface of the power transistor 2, there is no particular problem.

図５は、従来のダイボンディング装置、およびチップ領域以外の部分に接合材がはみ出した様子を示す図である。同図（ａ）は、半導体装置のダイボンディング装置を示す図であって、同図（ｂ），（ｃ）には、それぞれ半田供給後と、チップマウント後のリードフレーム１の半田付け面を示している。   FIG. 5 is a diagram illustrating a conventional die bonding apparatus and a state in which a bonding material protrudes from a portion other than the chip region. FIG. 2A is a view showing a die bonding apparatus for a semiconductor device. FIGS. 2B and 2C show soldered surfaces of the lead frame 1 after supplying solder and after mounting the chip, respectively. Show.

ここでは、図１のダイボンディング装置のように、供給された半田１２ａをリードフレーム１の上方から押圧整形する押圧手段１４を備えていない。そのため、マウント工程ではコレット１６で保持されたパワートランジスタ２によって半田１２ａが直接に押し広げられ、溶融半田がリードフレーム１の素子以外の領域にも大きく広がっている。また、接合材（半田層３）の厚みも不均一になりやすく、その厚み自体を正確にコントロールすることができない。そのために、図５（ａ）に示すようにパワートランジスタ２は傾斜した状態でリードフレーム１上にマウントされてしまうことがある。   Here, unlike the die bonding apparatus of FIG. 1, the pressing means 14 for pressing and shaping the supplied solder 12a from above the lead frame 1 is not provided. Therefore, in the mounting process, the solder 12 a is directly spread by the power transistor 2 held by the collet 16, and the molten solder is greatly spread to the region other than the elements of the lead frame 1. Moreover, the thickness of the bonding material (solder layer 3) is also likely to be non-uniform, and the thickness itself cannot be controlled accurately. Therefore, the power transistor 2 may be mounted on the lead frame 1 in an inclined state as shown in FIG.

図６は、本発明の半田接合方法によりリードフレーム上にマウントされたパワートランジスタの顕微鏡写真を示す図である。
この顕微鏡写真に示すように、リードフレーム１上に配置された矩形のパワートランジスタ２の周囲には、ほぼ均等に半田フィレット３ａが生じている。したがって、リードフレーム１上に均一な半田厚の接合材が形成され、安定した状態でパワートランジスタ２をマウントすることができる。 FIG. 6 is a view showing a photomicrograph of a power transistor mounted on a lead frame by the solder bonding method of the present invention.
As shown in this micrograph, the solder fillets 3a are generated almost uniformly around the rectangular power transistor 2 arranged on the lead frame 1. Therefore, a bonding material having a uniform solder thickness is formed on the lead frame 1, and the power transistor 2 can be mounted in a stable state.

以上、本発明の半田接合方法では、マウント前に所定の叩き工具で半田を押し広げているので、マウントされるパワートランジスタ２の高さを制御して、スクラブすることによって安定したマウント状態を確保できる。すなわち、所定量の半田をリードフレーム１に供給した後、叩き工具１４ｂをリードフレーム１まで下降させて、その開口部面積まで半田層を押し広げるように半田形状を整形してから、パワートランジスタ２をマウントするようにしたために、半田フィレットを均一に形成して、半田はみ出しを防止して、均一な半田厚を確保することができる。   As described above, in the solder joining method of the present invention, the solder is spread with a predetermined hitting tool before mounting. Therefore, a stable mounting state is ensured by controlling the height of the mounted power transistor 2 and scrubbing. it can. That is, after supplying a predetermined amount of solder to the lead frame 1, the striking tool 14 b is lowered to the lead frame 1, and after shaping the solder shape so as to spread the solder layer to the opening area, the power transistor 2. Therefore, the solder fillet can be formed uniformly to prevent the solder from protruding, and a uniform solder thickness can be ensured.

（２）接着剤によるＩＣチップの接合方法
つぎに、ＩＣチップを接着剤フィルムによってパワートランジスタチップの上に積層して接合するＩＣチップの接合方法について説明する。ここでは、接着剤フィルムの一例として、エポキシ樹脂を含有した熱硬化型ポリイミドフィルムが使用される。この接着剤フィルムは絶縁性フィルムであるが、導電性フィルムにも適用できる。 (2) IC chip bonding method using adhesive Next, an IC chip bonding method in which an IC chip is laminated on a power transistor chip using an adhesive film and bonded will be described. Here, as an example of the adhesive film, a thermosetting polyimide film containing an epoxy resin is used. This adhesive film is an insulating film, but can also be applied to a conductive film.

図７は、半導体ウェハーの裏面に接着剤フィルムを貼り付けてマウントする工程を示す図である。
同図（ａ）には、フィルム貼り付け工程を示す。円形の半導体ウェハー２１には、多数のＩＣチップが作成されている。この半導体ウェハー２１をそのままの状態で、その裏面全体に矩形のポリイミドフィルム２２を貼り付ける。こうして、ポリイミドフィルム２２はその硬化反応が開始する温度より約１０〜３０℃低い温度で、半導体ウェハー２１に対して仮接着される。 FIG. 7 is a diagram showing a process of attaching and mounting an adhesive film on the back surface of the semiconductor wafer.
FIG. 4A shows a film attaching process. A large number of IC chips are formed on the circular semiconductor wafer 21. With this semiconductor wafer 21 as it is, a rectangular polyimide film 22 is attached to the entire back surface thereof. Thus, the polyimide film 22 is temporarily bonded to the semiconductor wafer 21 at a temperature about 10 to 30 ° C. lower than the temperature at which the curing reaction starts.

図７（ｂ）にはダイカット（ＤＣ）工程を示す。ここでは、半導体ウェハー２１の外周部の余分なポリイミドフィルム２２を除去してから、ダイシングテープに半導体ウェハー２１を貼り付け、ダイサーによりフルカットを施すことにより、多数のＩＣチップ（ダイス）として切り出される。これらの一連の作業は、通常のチップ作成工程と同一工程である。通常の作業と異なっているのは、このようにして切り出されたＩＣチップ４の裏面には、チップサイズと同等であって、均一な膜厚の接着剤フィルム層５ａが形成されていることである。   FIG. 7B shows a die cutting (DC) process. Here, the excess polyimide film 22 on the outer peripheral portion of the semiconductor wafer 21 is removed, and then the semiconductor wafer 21 is attached to a dicing tape, and a full cut is performed by a dicer to cut out a large number of IC chips (dies). . These series of operations are the same as the normal chip manufacturing process. The difference from the normal operation is that an adhesive film layer 5a having a uniform film thickness is formed on the back surface of the IC chip 4 cut out in this way, which is equivalent to the chip size. is there.

図８は、熱硬化型ポリイミドフィルムの吸発熱曲線の一例を示す図である。このチャートの横軸には温度（℃）、縦軸にはＤＳＣ（示差走査熱量計）によって測定される熱量（ｍＷ）を示す。この吸発熱曲線によれば、ポリイミドフィルム２２の硬化開始温度は約１８０℃付近である。   FIG. 8 is a diagram showing an example of an endothermic curve of a thermosetting polyimide film. The horizontal axis of this chart indicates temperature (° C.), and the vertical axis indicates the amount of heat (mW) measured by DSC (differential scanning calorimeter). According to this endothermic curve, the curing start temperature of the polyimide film 22 is about 180 ° C.

つぎに、図７（ｃ）に示すダイ加熱（ＤＢ）工程に進んで、パワートランジスタ２上へのマウントが実施される。ここでは、リードフレーム１のマウント手段１５（図１）を用いて、コレット２３でＩＣチップ４を真空吸着して、恒温槽内で加熱されたパワートランジスタ２の表面所定位置に接着させる。   Next, the process proceeds to a die heating (DB) process shown in FIG. 7C, and mounting on the power transistor 2 is performed. Here, the IC chip 4 is vacuum-sucked by the collet 23 using the mounting means 15 (FIG. 1) of the lead frame 1 and adhered to a predetermined position on the surface of the power transistor 2 heated in the thermostat.

このとき恒温槽内のマウント温度は、半導体ウェハー２１に貼り付けられた接着剤フィルム（ポリイミドフィルム２２）の仕様に応じて最適化を図る必要がある。ここでは、ＩＣマウント温度と接着状態との関連について説明する。   At this time, it is necessary to optimize the mount temperature in the thermostat according to the specifications of the adhesive film (polyimide film 22) attached to the semiconductor wafer 21. Here, the relationship between the IC mount temperature and the adhesion state will be described.

図９（ａ）〜（ｃ）は、加熱温度がそれぞれ異なるパワートランジスタにポリイミドフィルムを接着したときの、接着部の顕微鏡写真を示す図である。
図９（ａ）に示すように、マウント時の加熱温度が１７０℃であれば、ＩＣチップ４の全面が均一に接着されることになる。しかし、図９（ｂ）および（ｃ）に示すように、ポリイミドフィルム２２の硬化開始温度である１８０℃以上の、１９０℃や２１０℃の高温でマウントを行ったときには、パワートランジスタ２上でＩＣチップ４の一部分しか接着されない不具合が生じる。これは、パワートランジスタ２が傾いていた場合に、マウント温度が硬化開始温度より高い状態であれば、接着剤フィルム層５ａとパワートランジスタ２との接触箇所のみが接着され、剥離部２２ａを残してポリイミドフィルム２２が硬化してしまうことに起因している。そして、このような剥離現象は、つぎに説明するワイヤボンディング時のワイヤ結線にも悪影響を及ぼす。 FIG. 9A to FIG. 9C are micrographs of bonded portions when polyimide films are bonded to power transistors having different heating temperatures.
As shown in FIG. 9A, if the heating temperature at the time of mounting is 170 ° C., the entire surface of the IC chip 4 is uniformly bonded. However, as shown in FIGS. 9B and 9C, when mounting is performed at a high temperature of 190 ° C. or 210 ° C., which is 180 ° C. or higher, which is the curing start temperature of the polyimide film 22, an IC is formed on the power transistor 2. There arises a problem that only a part of the chip 4 is bonded. If the power transistor 2 is tilted and the mount temperature is higher than the curing start temperature, only the contact portion between the adhesive film layer 5a and the power transistor 2 is bonded, leaving the peeling portion 22a. This is because the polyimide film 22 is cured. And such a peeling phenomenon has a bad influence also on the wire connection at the time of the wire bonding demonstrated below.

こうした不具合を解消するために、本発明のＩＣチップの接合方法では、マウント時の恒温槽内の温度を、当初は硬化開始温度より１０から２０℃低い温度、一例として約１０℃低い１７０℃でＩＣチップ４を仮接着するようにしている（第１のキュア工程）。仮接着では、ポリイミドフィルム２２が硬化を開始する直前の状態に留めておいて、その後に恒温槽内の温度を硬化開始温度以上に高くして、接着剤フィルム層５ａの硬化反応を完了させるためのキュアが施される（第２のキュア工程）。   In order to eliminate such problems, in the IC chip bonding method of the present invention, the temperature in the thermostatic chamber at the time of mounting is initially 10 to 20 ° C. lower than the curing start temperature, for example, 170 ° C. lower by about 10 ° C. The IC chip 4 is temporarily bonded (first curing step). In the temporary bonding, the polyimide film 22 is kept in a state immediately before the curing is started, and then the temperature in the thermostatic bath is set higher than the curing start temperature to complete the curing reaction of the adhesive film layer 5a. (The second curing step).

一般に、こうした２段階に温度を変化させるステップキュアの条件としては、まずマウント温度と同一温度（硬化開始温度より低い）状態でキュアをかけて、ポリイミドフィルム２２の粘弾性によりＩＣチップ４の全面での接着を図り、その後に温度を上げてポリイミドフィルム２２を完全硬化させることが必要である。接着剤フィルム層５ａの完全硬化は、ポリイミドフィルム２２が熱分解を開始する温度以下であって、かつエンドユーザーでの実装条件を含む温度プロファイルの最高温度で実施することが望ましい。具体的には、エンドユーザーの基板実装時の加熱温度である２６０℃（Ｐｂフリー半田の実装温度）で完全硬化させている。   In general, as a condition for the step cure in which the temperature is changed in two stages, first, curing is performed at the same temperature as the mount temperature (lower than the curing start temperature), and the entire surface of the IC chip 4 is applied due to the viscoelasticity of the polyimide film 22. It is necessary that the polyimide film 22 be completely cured by raising the temperature after that. The complete curing of the adhesive film layer 5a is preferably performed at a temperature not higher than the temperature at which the polyimide film 22 starts thermal decomposition and at the maximum temperature of the temperature profile including the mounting conditions of the end user. Specifically, it is completely cured at 260 ° C. (Pb-free solder mounting temperature), which is the heating temperature when the end user mounts the board.

以上に説明した接着剤フィルムによるＩＣチップ４の接合方法では、ＣＯＣの半導体装置にポリイミドフィルム２２のようなフィルム系接着剤を導入して、半導体ウェハー２１をウェハー状態のままで、まずフィルム系接着剤がウェハー裏面に貼り付けられ、その後に従来通りのダイシングカットをするようにしたので、アウトガス量を低減させて、接着剤内のボイドをなくすとともに、その厚みを均一化できる。また、チップサイズ同等の接着剤をＩＣチップ４のチップ裏面に設けてから、パワートランジスタ２のような半導体チップ上にマウントするようにしたので、接着剤の位置ずれや染み出しなどの不具合を解消できる。さらに、ＩＣチップ４のマウント装置には、パワートランジスタ２の接合工程で使用したコレット２３をそのまま流用でき、設備投資を大幅に抑制することができる。   In the bonding method of the IC chip 4 using the adhesive film described above, a film adhesive such as the polyimide film 22 is introduced into the COC semiconductor device, and the semiconductor wafer 21 is left in the wafer state, and the film adhesive is first performed. Since the agent is affixed to the back surface of the wafer, and then the conventional dicing cut is performed, the amount of outgas can be reduced, voids in the adhesive can be eliminated, and the thickness thereof can be made uniform. In addition, since the adhesive equivalent to the chip size is provided on the back surface of the IC chip 4 and mounted on the semiconductor chip such as the power transistor 2, problems such as misalignment and bleeding of the adhesive are eliminated. it can. Further, the collet 23 used in the joining process of the power transistor 2 can be used as it is for the mounting device of the IC chip 4, and the capital investment can be greatly suppressed.

なお、フィルム系接着剤を用いるときには、その硬化特性を把握して最適キュア（ステップキュア）の条件を容易に確立できるとともに、ＩＣチップ４の裏面全面の接着剤を確実に硬化させておくことによって、結線時のワイヤボンディング性が損なわれないという利点もある。   When using a film-based adhesive, it is possible to easily establish the conditions for optimal cure (step cure) by grasping its curing characteristics and to ensure that the adhesive on the entire back surface of the IC chip 4 is cured. There is also an advantage that the wire bonding property at the time of connection is not impaired.

（３）ワイヤボンディングによる結線方法
ＣＯＣの半導体装置におけるワイヤボンディングによる結線方法では、短ループ／低ループでワイヤボンディングをいかに安定して完成させるかが最大の課題となる。上述した半導体チップの半田接合方法、および接着剤によるＩＣチップの接合方法を適用した半導体装置においても、ボンディングツールの移動軌跡に合わせて、そこから引き出されるワイヤの長さを一定にして、かつそのワイヤ形状を安定してワイヤ結線することが必要不可欠である。 (3) Connection Method by Wire Bonding In the connection method by wire bonding in a COC semiconductor device, the biggest issue is how to complete wire bonding stably in a short loop / low loop. Even in a semiconductor device to which the above-described semiconductor chip soldering method and IC chip bonding method using an adhesive are applied, the length of the wire drawn from the bonding tool is adjusted in accordance with the movement trajectory of the bonding tool. It is indispensable to stably wire the wire shape.

図１０は、本発明のワイヤボンディングによる結線方法を示す説明図である。ボンディングツール３１は、アルミワイヤなどの金属細線９を保持するワイヤガイド３２と、ボンディング後にワイヤをカットするカッター３３とクランプ機構３４とを備えたウェッジボンダー３０として構成されている。   FIG. 10 is an explanatory view showing a connection method by wire bonding according to the present invention. The bonding tool 31 is configured as a wedge bonder 30 including a wire guide 32 that holds a thin metal wire 9 such as an aluminum wire, a cutter 33 that cuts the wire after bonding, and a clamp mechanism 34.

同図（ａ）では、ウェッジボンダー３０によりＩＣチップ４のボンディング位置に配線用の金属細線９が超音波接合される（第１のボンディング工程）。同図（ｂ）には、ワイヤガイド３２から引き出された金属細線９によりツール軌跡を示す。このとき、金属細線９はワイヤガイド３２から所定長さだけ引き出された後、クランプ機構３４によってクランプされる（ワイヤ引き出し工程）。   In FIG. 2A, the fine metal wires 9 are ultrasonically bonded to the bonding position of the IC chip 4 by the wedge bonder 30 (first bonding step). In FIG. 4B, the tool trajectory is shown by the fine metal wire 9 drawn out from the wire guide 32. At this time, the thin metal wire 9 is pulled out by a predetermined length from the wire guide 32 and then clamped by the clamp mechanism 34 (wire drawing process).

同図（ｃ）では、ウェッジボンダー３０はワイヤガイド３２のクランプ機構３４によってワイヤクランプ状態が保持され、リードフレーム１（図１）と一体構成のアウタリード７のボンディング位置まで移動する。そして、金属細線９の他端をウェッジボンダー３０によりアウタリード７上に超音波接合している（第２のボンディング工程）。   In FIG. 6C, the wedge bonder 30 is held in the wire clamp state by the clamp mechanism 34 of the wire guide 32, and moves to the bonding position of the outer lead 7 integrated with the lead frame 1 (FIG. 1). The other end of the fine metal wire 9 is ultrasonically bonded onto the outer lead 7 by the wedge bonder 30 (second bonding step).

このように第１のボンディング工程が終了した後のワイヤ引き出し時に、結線用ワイヤのループ形状を安定化させるために、ウェッジボンダー３０の付加機能であるアクティブクランプ機能を活用して、金属細線９の引き出し量を安定化させている。すなわち、第１のボンディング工程の後、第２のボンディング工程に進む前に、金属細線９をクランプ機構３４によってクランプしながら一定のワイヤ長で結線するようにしたので、金属細線９が形成するループ形状の安定性を図ることができる。なお、金線ワイヤをボンディングする場合でも、同様の動作によって同等の効果を達成できる。   In order to stabilize the loop shape of the wire for connection when the wire is pulled out after the first bonding process is completed in this way, the active clamp function which is an additional function of the wedge bonder 30 is utilized to The amount of drawer is stabilized. That is, after the first bonding step and before proceeding to the second bonding step, the metal thin wire 9 is clamped by the clamp mechanism 34 and connected with a fixed wire length, so that the loop formed by the metal thin wire 9 is formed. Shape stability can be achieved. Even when a gold wire is bonded, the same effect can be achieved by the same operation.

以上、この発明の実施形態について説明したが、この発明は上述した実施形態のものに限られるわけではない。たとえばパワートランジスタの接合半田としては、Ｓｎ−Ｐｂ系に限らずＳｎ−Ａｇ、Ｓｎ−Ｓｂ系半田にも適用可能である。   As mentioned above, although embodiment of this invention was described, this invention is not necessarily restricted to the thing of embodiment mentioned above. For example, the junction solder of the power transistor is not limited to Sn—Pb, but can be applied to Sn—Ag and Sn—Sb solder.

またＩＣチップの接着剤についても、ポリイミドフィルム以外の熱硬化性フィルム接着剤を利用することも可能である。   Moreover, it is also possible to utilize thermosetting film adhesives other than a polyimide film also about the adhesive agent of an IC chip.

１ リードフレーム
２ パワートランジスタ
３ 半田層
４ 制御用のＩＣチップ
５ 絶縁性接着剤
５ａ 接着剤フィルム層
６，８，９ 金属細線
７ アウタリード
１１ ヒータレール
１２，１２ａ 半田
１３ 半田供給手段
１３ａ 供給部
１４ 押圧手段
１４ａ 加圧工具
１４ｂ 叩き工具
１５ マウント手段
１６，２３ コレット
２１ 半導体ウェハー
２２ ポリイミドフィルム
３０ ウェッジボンダー
３１ ボンディングツール
３２ ワイヤガイド
３３ カッター
３４ クランプ機構 DESCRIPTION OF SYMBOLS 1 Lead frame 2 Power transistor 3 Solder layer 4 IC chip for control 5 Insulating adhesive 5a Adhesive film layer 6, 8, 9 Metal thin wire 7 Outer lead 11 Heater rail 12, 12a Solder 13 Solder supply means 13a Supply part 14 Press Means 14a Pressure tool 14b Tapping tool 15 Mounting means 16, 23 Collet 21 Semiconductor wafer 22 Polyimide film 30 Wedge bonder 31 Bonding tool 32 Wire guide 33 Cutter 34 Clamp mechanism

Claims (2)

半導体チップを半田接合によって金属製のリードフレームの所定位置にマウントし、前記半導体チップにＩＣチップをさらに積層して配置し、前記リードフレーム、前記半導体チップ、または前記ＩＣチップの間を電気的に接続する半導体装置の製造方法において、
前記リードフレーム、前記半導体チップ、または前記ＩＣチップのボンディング位置に配線用ワイヤを超音波接合する第１のボンディング工程と、
前記配線用ワイヤをキャピラリから所定長さだけ引き出した後に、前記キャピラリをワイヤクランプ状態にして前記リードフレーム、前記半導体チップ、または前記ＩＣチップの別のボンディング位置に移動するワイヤ引き出し工程と、
前記別のボンディング位置で前記配線用ワイヤの他端を超音波接合する第２のボンディング工程と、
を含むことを特徴とする半導体装置の製造方法。 A semiconductor chip is mounted at a predetermined position on a metal lead frame by solder bonding, an IC chip is further stacked on the semiconductor chip, and the lead frame, the semiconductor chip, or the IC chip is electrically connected. In the manufacturing method of the semiconductor device to be connected,
A first bonding step of ultrasonically bonding a wire for wiring to a bonding position of the lead frame, the semiconductor chip, or the IC chip;
A wire drawing step of drawing the wiring wire from the capillary by a predetermined length and then moving the capillary to a wire clamping state and moving to another bonding position of the lead frame, the semiconductor chip, or the IC chip;
A second bonding step of ultrasonically bonding the other end of the wiring wire at the other bonding position;
A method for manufacturing a semiconductor device, comprising: 前記配線用ワイヤがアルミワイヤもしくは金線ワイヤであることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring wire is an aluminum wire or a gold wire.
JP2010248251A 2010-11-05 2010-11-05 Method of manufacturing semiconductor device Pending JP2011023768A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162217A (en) * 1995-12-08 1997-06-20 Sony Corp Semiconductor device
JP2001007143A (en) * 1999-06-22 2001-01-12 Kaijo Corp Wire bonding device
JP2004031451A (en) * 2002-06-21 2004-01-29 Mitsubishi Electric Corp Semiconductor device and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162217A (en) * 1995-12-08 1997-06-20 Sony Corp Semiconductor device
JP2001007143A (en) * 1999-06-22 2001-01-12 Kaijo Corp Wire bonding device
JP2004031451A (en) * 2002-06-21 2004-01-29 Mitsubishi Electric Corp Semiconductor device and its manufacturing method

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