JP3920994B2 - プロセッサをコプロセッサにインタフェースするための方法および装置 - Google Patents

プロセッサをコプロセッサにインタフェースするための方法および装置 Download PDF

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Publication number
JP3920994B2
JP3920994B2 JP25936498A JP25936498A JP3920994B2 JP 3920994 B2 JP3920994 B2 JP 3920994B2 JP 25936498 A JP25936498 A JP 25936498A JP 25936498 A JP25936498 A JP 25936498A JP 3920994 B2 JP3920994 B2 JP 3920994B2
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coprocessor
processor
instruction
bus
control signal
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JP25936498A
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Japanese (ja)
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JPH11154144A5 (enExample
JPH11154144A (ja
Inventor
ウィリアム・シー・モイヤー
ジョン・アレンズ
ジェフリー・ダブリュ・スコット
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NXP USA Inc
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NXP USA Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30116—Shadow registers, e.g. coupled registers, not forming part of the register space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G06F9/3881—Arrangements for communication of instructions and data

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
JP25936498A 1997-09-05 1998-08-28 プロセッサをコプロセッサにインタフェースするための方法および装置 Expired - Fee Related JP3920994B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/924,518 US6505290B1 (en) 1997-09-05 1997-09-05 Method and apparatus for interfacing a processor to a coprocessor
US08/924,518 1997-09-05

Publications (3)

Publication Number Publication Date
JPH11154144A JPH11154144A (ja) 1999-06-08
JPH11154144A5 JPH11154144A5 (enExample) 2005-10-27
JP3920994B2 true JP3920994B2 (ja) 2007-05-30

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JP25936498A Expired - Fee Related JP3920994B2 (ja) 1997-09-05 1998-08-28 プロセッサをコプロセッサにインタフェースするための方法および装置

Country Status (8)

Country Link
US (3) US6505290B1 (enExample)
EP (2) EP0901071B1 (enExample)
JP (1) JP3920994B2 (enExample)
KR (1) KR100563012B1 (enExample)
CN (3) CN1299218C (enExample)
DE (1) DE69814268T2 (enExample)
SG (2) SG102528A1 (enExample)
TW (1) TW385410B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002169724A (ja) * 2000-12-01 2002-06-14 Oki Electric Ind Co Ltd キャッシュメモリにおける部分無効化装置

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001092663A (ja) * 1999-09-17 2001-04-06 Sanyo Electric Co Ltd データ処理装置
US6829697B1 (en) * 2000-09-06 2004-12-07 International Business Machines Corporation Multiple logical interfaces to a shared coprocessor resource
EP2804106A1 (en) * 2000-09-06 2014-11-19 Ericsson Modems SA Inter-processor communication system
JP2002149402A (ja) * 2000-11-14 2002-05-24 Pacific Design Kk データ処理装置およびその制御方法
US7237090B1 (en) 2000-12-29 2007-06-26 Mips Technologies, Inc. Configurable out-of-order data transfer in a coprocessor interface
US7287147B1 (en) 2000-12-29 2007-10-23 Mips Technologies, Inc. Configurable co-processor interface
US6754804B1 (en) * 2000-12-29 2004-06-22 Mips Technologies, Inc. Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions
US7168066B1 (en) 2001-04-30 2007-01-23 Mips Technologies, Inc. Tracing out-of order load data
US7240203B2 (en) * 2001-07-24 2007-07-03 Cavium Networks, Inc. Method and apparatus for establishing secure sessions
GB2378271B (en) * 2001-07-30 2004-12-29 Advanced Risc Mach Ltd Handling of coprocessor instructions in a data processing apparatus
US7228401B2 (en) 2001-11-13 2007-06-05 Freescale Semiconductor, Inc. Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor
US6886092B1 (en) * 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US6795877B2 (en) * 2001-11-29 2004-09-21 Intel Corporation Configurable serial bus to couple baseband and application processors
FR2834154B1 (fr) * 2001-12-21 2005-03-11 Oberthur Card Syst Sa Unite electronique incluant des moyens de cryptographie capables de traiter des informations a haut debit
US7305567B1 (en) 2002-03-01 2007-12-04 Cavium Networks, In. Decoupled architecture for data ciphering operations
US7154941B2 (en) * 2002-06-28 2006-12-26 Nokia Corporation Modem having a vector-architecture processor, and associated methodology therefor
EP1387259B1 (en) * 2002-07-31 2017-09-20 Texas Instruments Incorporated Inter-processor control
JP4182801B2 (ja) * 2003-04-24 2008-11-19 日本電気株式会社 マルチプロセサシステム
KR100849296B1 (ko) * 2003-06-13 2008-07-29 삼성전자주식회사 주제어부와 보조제어부를 구비하는 시스템에서의보조제어부의 초기화 장치 및 방법
JP4224430B2 (ja) * 2003-07-07 2009-02-12 株式会社ルネサステクノロジ 情報処理装置
US7441106B2 (en) 2004-07-02 2008-10-21 Seagate Technology Llc Distributed processing in a multiple processing unit environment
DE602004026431D1 (de) * 2004-07-09 2010-05-20 Michael Colin George Chapman Hochleistungsfähiger benutzer-konfigurierbarer Prozessor
JP3768516B1 (ja) 2004-12-03 2006-04-19 株式会社ソニー・コンピュータエンタテインメント マルチプロセッサシステムとそのシステムにおけるプログラム実行方法
US20060155974A1 (en) * 2005-01-07 2006-07-13 Moyer William C Data processing system having flexible instruction capability and selection mechanism
JP3867804B2 (ja) * 2005-03-22 2007-01-17 セイコーエプソン株式会社 集積回路装置
US7472261B2 (en) * 2005-11-08 2008-12-30 International Business Machines Corporation Method for performing externally assisted calls in a heterogeneous processing complex
KR100781340B1 (ko) * 2006-09-18 2007-11-30 삼성전자주식회사 사용자 정의 확장 연산을 처리하는 연산 시스템 및 방법
US8095699B2 (en) * 2006-09-29 2012-01-10 Mediatek Inc. Methods and apparatus for interfacing between a host processor and a coprocessor
US8006069B2 (en) * 2006-10-05 2011-08-23 Synopsys, Inc. Inter-processor communication method
US20080147357A1 (en) * 2006-12-15 2008-06-19 Iintrinisyc Software International System and method of assessing performance of a processor
FR2942556B1 (fr) * 2009-02-24 2011-03-25 Commissariat Energie Atomique Unite d'allocation et de controle
WO2010150474A1 (ja) 2009-06-23 2010-12-29 セイコーエプソン株式会社 サブプロセッサー、集積回路装置及び電子機器
EP2278452A1 (en) * 2009-07-15 2011-01-26 Nxp B.V. Coprocessor programming
JP5632651B2 (ja) * 2010-05-19 2014-11-26 スパンション エルエルシー 半導体回路及び設計装置
JP5739055B2 (ja) * 2011-04-01 2015-06-24 インテル コーポレイション ベクトルフレンドリ命令フォーマット及びその実行
CN102736895B (zh) * 2011-04-07 2015-06-10 中兴通讯股份有限公司 一种实现寄存器文件间的数据传输方法及装置
EP2525286A1 (en) * 2011-05-17 2012-11-21 Nxp B.V. Co-processor interface
JP2012252374A (ja) * 2011-05-31 2012-12-20 Renesas Electronics Corp 情報処理装置
JP5653865B2 (ja) * 2011-08-23 2015-01-14 日本電信電話株式会社 データ処理システム
CN104011670B (zh) 2011-12-22 2016-12-28 英特尔公司 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令
US9329870B2 (en) 2013-02-13 2016-05-03 International Business Machines Corporation Extensible execution unit interface architecture with multiple decode logic and multiple execution units
US9203835B2 (en) 2013-03-01 2015-12-01 Paypal, Inc. Systems and methods for authenticating a user based on a biometric model associated with the user
US20150261535A1 (en) * 2014-03-11 2015-09-17 Cavium, Inc. Method and apparatus for low latency exchange of data between a processor and coprocessor
CN105988773B (zh) 2015-02-10 2021-03-09 恩智浦美国有限公司 硬件接口组件和用于硬件接口组件的方法
CN106648400B (zh) * 2015-11-03 2020-04-03 华为终端有限公司 一种触摸数据上报的方法及电子设备
CN108076476B (zh) * 2016-11-18 2020-11-06 华为技术有限公司 用于传输数据的方法和装置
US11263014B2 (en) * 2019-08-05 2022-03-01 Arm Limited Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry
CN110532040A (zh) * 2019-08-29 2019-12-03 北京地平线机器人技术研发有限公司 固件程序的加载方法及装置、存储介质和电子设备
CN111917471B (zh) * 2020-09-09 2021-09-28 西安工程大学 一种自由空间可见光通信系统及其通信性能优化算法

Family Cites Families (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4270167A (en) 1978-06-30 1981-05-26 Intel Corporation Apparatus and method for cooperative and concurrent coprocessing of digital information
US4547849A (en) 1981-12-09 1985-10-15 Glenn Louie Interface between a microprocessor and a coprocessor
US4509116A (en) 1982-04-21 1985-04-02 Digital Equipment Corporation Special instruction processing unit for data processing system
US4715013A (en) 1983-04-18 1987-12-22 Motorola, Inc. Coprocessor instruction format
US4729094A (en) 1983-04-18 1988-03-01 Motorola, Inc. Method and apparatus for coordinating execution of an instruction by a coprocessor
US4731736A (en) 1983-04-18 1988-03-15 Motorola, Inc. Method and apparatus for coordinating execution of an instruction by a selected coprocessor
US4763242A (en) * 1985-10-23 1988-08-09 Hewlett-Packard Company Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility
JPH079643B2 (ja) 1986-09-24 1995-02-01 株式会社日立マイコンシステム コプロセツサデ−タ転送制御方式
US5001624A (en) 1987-02-13 1991-03-19 Harrell Hoffman Processor controlled DMA controller for transferring instruction and data from memory to coprocessor
US5091845A (en) * 1987-02-24 1992-02-25 Digital Equipment Corporation System for controlling the storage of information in a cache memory
US5226170A (en) * 1987-02-24 1993-07-06 Digital Equipment Corporation Interface between processor and special instruction processor in digital data processing system
IN171198B (enExample) * 1987-02-24 1992-08-15 Digital Equipment Corp
US5341482A (en) * 1987-03-20 1994-08-23 Digital Equipment Corporation Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions
JPS63259727A (ja) 1987-04-17 1988-10-26 Hitachi Ltd コプロセツサのインタ−フエイス方式
US4991078A (en) 1987-09-29 1991-02-05 Digital Equipment Corporation Apparatus and method for a pipelined central processing unit in a data processing system
JPH0679307B2 (ja) 1987-10-22 1994-10-05 日本電気株式会社 コプロセッサの並行動作制御方式
JPH01147656A (ja) 1987-12-03 1989-06-09 Nec Corp マイクロプロセッサ
JPH01277934A (ja) * 1988-04-29 1989-11-08 Nec Corp パラメータリスト参照方法の切換え方式
JP2741867B2 (ja) * 1988-05-27 1998-04-22 株式会社日立製作所 情報処理システムおよびプロセツサ
US5109514A (en) * 1988-07-28 1992-04-28 Sun Microsystems, Inc. Method and apparatus for executing concurrent CO processor operations and precisely handling related exceptions
JP2754825B2 (ja) 1989-02-03 1998-05-20 日本電気株式会社 マイクロプロセッサ
US5093908A (en) 1989-04-17 1992-03-03 International Business Machines Corporation Method and apparatus for executing instructions in a single sequential instruction stream in a main processor and a coprocessor
US5218711A (en) 1989-05-15 1993-06-08 Mitsubishi Denki Kabushiki Kaisha Microprocessor having program counter registers for its coprocessors
US5247650A (en) * 1989-08-30 1993-09-21 Industrial Technology Institute System for combining originally software incompatible control, kinematic, and discrete event simulation systems into a single integrated simulation system
WO1991011765A1 (en) 1990-01-29 1991-08-08 Teraplex, Inc. Architecture for minimal instruction set computing system
EP0468831B1 (en) 1990-06-29 1997-10-15 Digital Equipment Corporation Bus protocol for write-back cache processor
US5305446A (en) 1990-09-28 1994-04-19 Texas Instruments Incorporated Processing devices with improved addressing capabilities, systems and methods
US5826101A (en) 1990-09-28 1998-10-20 Texas Instruments Incorporated Data processing device having split-mode DMA channel
US5283881A (en) * 1991-01-22 1994-02-01 Westinghouse Electric Corp. Microcoprocessor, memory management unit interface to support one or more coprocessors
JP3206006B2 (ja) * 1991-01-25 2001-09-04 株式会社日立製作所 二重化バス制御方法及び装置
US5488729A (en) 1991-05-15 1996-01-30 Ross Technology, Inc. Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
US5430850A (en) 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads
US5767939A (en) 1991-10-09 1998-06-16 Seiko Epson Corporation Eyeglass lens
US5708784A (en) * 1991-11-27 1998-01-13 Emc Corporation Dual bus computer architecture utilizing distributed arbitrators and method of using same
JPH07504054A (ja) 1992-02-18 1995-04-27 アプル・コンピュータ・インコーポレーテッド コンピュータシステムにおけるコプロセッサのプログラミングモデル
US5481743A (en) 1993-09-30 1996-01-02 Apple Computer, Inc. Minimal instruction set computer architecture and multiple instruction issue method
US5706478A (en) * 1994-05-23 1998-01-06 Cirrus Logic, Inc. Display list processor for operating in processor and coprocessor modes
JP2987308B2 (ja) * 1995-04-28 1999-12-06 松下電器産業株式会社 情報処理装置
US5603047A (en) 1995-10-06 1997-02-11 Lsi Logic Corporation Superscalar microprocessor architecture
US5898897A (en) * 1996-10-18 1999-04-27 Samsung Electronics Company, Ltd. Bit stream signal feature detection in a signal processing system
US5953741A (en) * 1996-11-27 1999-09-14 Vlsi Technology, Inc. Stack cache for stack-based processor and method thereof
US5715439A (en) * 1996-12-09 1998-02-03 Allen-Bradley Company, Inc. Bi-directional co-processor interface
GB2326253A (en) 1997-06-10 1998-12-16 Advanced Risc Mach Ltd Coprocessor data access control
US6226738B1 (en) 1997-08-01 2001-05-01 Micron Technology, Inc. Split embedded DRAM processor
US6163836A (en) 1997-08-01 2000-12-19 Micron Technology, Inc. Processor with programmable addressing modes
US6760833B1 (en) 1997-08-01 2004-07-06 Micron Technology, Inc. Split embedded DRAM processor
US6216222B1 (en) 1998-05-14 2001-04-10 Arm Limited Handling exceptions in a pipelined data processing apparatus
US6247113B1 (en) 1998-05-27 2001-06-12 Arm Limited Coprocessor opcode division by data type
US6434689B2 (en) 1998-11-09 2002-08-13 Infineon Technologies North America Corp. Data processing unit with interface for sharing registers by a processor and a coprocessor
KR100308618B1 (ko) 1999-02-27 2001-09-26 윤종용 단일 칩 상의 마이크로프로세서-코프로세서 시스템을 구비한 파이프라인 데이터 처리 시스템 및 호스트 마이크로프로세서와 코프로세서 사이의 인터페이스 방법
US6446221B1 (en) 1999-05-19 2002-09-03 Arm Limited Debug mechanism for data processing systems
US6557069B1 (en) 1999-11-12 2003-04-29 International Business Machines Corporation Processor-memory bus architecture for supporting multiple processors
US6526469B1 (en) 1999-11-12 2003-02-25 International Business Machines Corporation Bus architecture employing varying width uni-directional command bus
US6513091B1 (en) 1999-11-12 2003-01-28 International Business Machines Corporation Data routing using status-response signals
US6658545B1 (en) 2000-02-16 2003-12-02 Lucent Technologies Inc. Passing internal bus data external to a completed system
US6626489B2 (en) * 2001-07-18 2003-09-30 Evenflo Company, Inc. Infant seat providing a cushioned carry

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002169724A (ja) * 2000-12-01 2002-06-14 Oki Electric Ind Co Ltd キャッシュメモリにおける部分無効化装置

Also Published As

Publication number Publication date
CN1560729A (zh) 2005-01-05
US6327647B1 (en) 2001-12-04
TW385410B (en) 2000-03-21
DE69814268T2 (de) 2004-01-22
CN1307536C (zh) 2007-03-28
US6505290B1 (en) 2003-01-07
EP1282035A1 (en) 2003-02-05
CN1299218C (zh) 2007-02-07
SG102528A1 (en) 2004-03-26
CN1211012A (zh) 1999-03-17
EP0901071A3 (en) 1999-10-13
CN1983167A (zh) 2007-06-20
SG103282A1 (en) 2004-04-29
KR19990029361A (ko) 1999-04-26
JPH11154144A (ja) 1999-06-08
DE69814268D1 (de) 2003-06-12
US7007154B2 (en) 2006-02-28
EP0901071A2 (en) 1999-03-10
KR100563012B1 (ko) 2007-04-10
CN100573445C (zh) 2009-12-23
EP0901071B1 (en) 2003-05-07
US20020049894A1 (en) 2002-04-25

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