JP3915317B2 - Electronic component mounting method - Google Patents

Electronic component mounting method Download PDF

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Publication number
JP3915317B2
JP3915317B2 JP12960699A JP12960699A JP3915317B2 JP 3915317 B2 JP3915317 B2 JP 3915317B2 JP 12960699 A JP12960699 A JP 12960699A JP 12960699 A JP12960699 A JP 12960699A JP 3915317 B2 JP3915317 B2 JP 3915317B2
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Japan
Prior art keywords
bond
substrate
electronic component
chip
curing
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP12960699A
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Japanese (ja)
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JP2000323348A (en
Inventor
秀喜 永福
忠彦 境
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP12960699A priority Critical patent/JP3915317B2/en
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Publication of JP3915317B2 publication Critical patent/JP3915317B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、電子部品をボンドによって基板に接着して実装する電子部品の実装方法に関するものである。
【０００２】
【従来の技術】
半導体チップなどの電子部品を基板に実装する方法として、ボンドによってチップを接着する方法が用いられている。ボンドは熱硬化性の樹脂接着剤であり、基板上に供給されたボンドの上にチップを搭載した状態で、所定の温度条件を所定時間保持することによりボンドが硬化し、これによりチップは所定強度で基板に固着される。そして実装後にはチップが基板に接続された状態での動作状態を検査する機能検査が行われる。この機能検査で不良と判定されたもののうち、再利用可能と判断された部品は取り外して再利用することが望ましい。
【０００３】
【発明が解決しようとする課題】
ところが、ボンドが完全に硬化した後のチップと基板との接合部は、介在するボンドが強固に固着しているためボンドと基板あるいはボンドとチップの界面を良好な状態を保ちながら剥離させることが難しい。このため、従来は機能的には再利用が可能な部品であるにも拘わらず、良好な状態で取り外すことが困難であるために廃棄処分される場合が大半で、資源の有効利用が図られていないという問題点があった。
【０００４】
そこで本発明は、実装後の部品の取り外しが容易に行え、部品の有効利用を図ることができる電子部品の実装方法を提供することを目的とする。
【０００５】
【課題を解決するための手段】
請求項１記載の電子部品の実装方法は、基板に電子部品接着用の熱硬化性のボンドを供給するボンド供給工程と、ボンドが供給された実装部位に熱圧着ヘッドの下面に保持された電子部品を搭載する搭載工程と、前記ボンドを仮硬化させる仮硬化工程と、ボンドが仮硬化した状態で前記基板の機能検査を行う検査工程と、機能検査によって合格判定された基板について前記ボンドを本硬化させる本硬化工程とを含み、前記仮硬化工程において、前記熱圧着ヘッドにより電子部品を上面から加熱してボンドを上方側をより速く硬化進行させることにより、前記基板とボンドとの接合強度よりも電子部品とボンドとの接合強度の方が大きくなるようにボンドを硬化させることにより、前記機能検査において不合格判定された基板について、ボンドが仮硬化の状態で、前記基板とボンドが固着した前記電子部品を分離させて基板を再利用するようにした。
【０００７】
本発明によれば、機能検査に先立って行われ電子部品接着用のボンドを仮硬化させる仮硬化工程において、基板とボンドとの接合強度よりも電子部品とボンドとの接合強度が大きくなるようにボンドを硬化させることにより、機能検査によって不合格判定された基板についてはボンドを本硬化させることなくリペア作業を行え、再利用可能な基板を良好な状態でボンドから剥離させることができる。
【０００８】
【発明の実施の形態】
次に本発明の実施の形態を図面を参照して説明する。図１（ａ），（ｂ），（ｃ）、図２（ａ），（ｂ），（ｃ）は本発明の一実施の形態の電子部品の実装方法の工程説明図である。図１（ａ），（ｂ），（ｃ）、図２（ａ），（ｂ），（ｃ）は実装方法を工程順に示したものである。
【０００９】
まず図１（ａ）において、基板１には電極２、２ａが形成されている。電極２は電子部品である半導体チップ（以下単に「チップ」と略称）との接続用に設けられたものであり、電極２ａはチップ搭載後に行われる機能検査時に検査用プローブを接触させて基板１の回路を検査装置と導通させるためのものである。基板１の電極２の周囲には、熱硬化性の樹脂接着剤であるボンド３が供給される。ボンド３の供給方法としては、ディスペンサによって塗布する方法、スクリーン印刷によって供給部位にボンドを印刷する方法などが用いられる。
【００１０】
次に図１（ｂ）に示すように、ボンド３が供給された電極２の周囲、すなわちチップが実装される実装部位には、熱圧着ヘッド５の下面に保持されたチップ４が搭載される。チップ４の下面には金属バンプ４ａが形成されており、金属バンプ４ａを電極２に押圧することにより、チップ４は基板１に設けられた回路と電気的に接続される。
【００１１】
この後、図１（ｃ）に示すように、熱圧着ヘッド５に備えられた加熱手段を駆動してチップ４を上面から加熱するとともに、熱圧着ヘッド５によってチップ４を所定荷重で押圧する。これにより、金属バンプ４ａは電極２の表面に押し付けられ良好な導通が得られる。そして加熱を継続することによりボンド３の硬化が進行する。ここで行われる加熱はボンド３を完全に硬化させるような条件では行われず、ボンド３の硬化が不完全なまま一旦中断するような方法で行われる。例えば１７０℃の加熱温度を６０秒継続することが完全硬化の加熱条件がであれば、この温度での加熱を約１０秒程度行った後に加熱を停止する。すなわち、この加熱工程はボンド３の仮硬化工程である。
【００１２】
このとき、チップ４と基板１の間に存在するボンド３に対しては、チップ４を介して上方から熱が伝達されるためボンド３の硬化状態は一様ではなく、熱が伝達される上方側のほうがより速く硬化が進行する（図１（ｃ）に示す破線部参照）。したがって仮硬化工程においては、チップ４とボンド３との接合強度の方が基板１とボンド３との接合強度よりも大きくなるようにボンド３が硬化する。
【００１３】
この仮硬化工程後、チップ４が搭載された基板１は検査工程に送られ、ここで機能検査が行われる。機能検査はチップ４が基板１に接続された状態でチップ４と基板１より構成される電子回路の動作が正常か否かを検査するものであり、図２（ａ）に示すように検査装置（図示せず）のプローブ６を基板１の電極２ａに接触させることにより、所定の検査が行われる。
【００１４】
この機能検査の結果、異常が検出されず合格判定されたものは本硬化工程に送られる。ここでは、所定温度での加熱を所定時間継続することにより、図２（ｂ）に示すように仮硬化状態にあるボンド３の硬化反応をさらに進行させて完全硬化させる。そしてこれによりチップ４の基板１への実装が完了する。
【００１５】
これに対し、機能検査において異常が検出された基板１は本硬化工程には送られず、部品再利用可否が判断される。そしてここでチップ４の再利用が可能であると判断された基板１はリペア工程に送られ、リペア工程ではチップ４と基板１を分離する作業が行われる。この分離作業では、図２（ｃ）に示すようにボンド３が仮硬化した状態で、チップ４をツール７によって上方に引き剥がす操作を行う。
【００１６】
このとき、前述のように仮硬化工程においてはチップ４とボンド３との接合強度の方が基板１とボンド３との接合強度よりも大きくなるような硬化過程が採られているため、ボンド３の剥離面は基板１とボンド３との界面に生じる。したがって基板１は、良好な状態でボンド３が固着したチップ４から分離される。すなわち、この基板１の実装面にはチップ４の実装を妨げるボンド３の付着がないため、新たなチップの実装用に再利用することが可能な状態にある。
【００１７】
上記説明したように、ボンド３を仮硬化させる際に、チップ４とボンド３との接合強度の方が基板１とボンド３との接合強度よりも大きくなるような硬化過程を採用することにより、機能検査後のリペアにおいて基板を良好な状態で取り外すことができる。すなわち、本実施の形態を単価の高い種類の基板を用いた実装に対して適用することにより、機能検査で異常が検出された場合においても基板そのものに不良が無ければその基板を再利用することができ、資源の有効利用が促進される。
【００１８】
【発明の効果】
本発明によれば、機能検査に先立って行われ電子部品接着用のボンドを仮硬化させる仮硬化工程において、基板とボンドとの接合強度よりも電子部品とボンドとの接合強度が大きくなるようにボンドを硬化させることにより、機能検査によって不合格判定された基板についてはボンドを本硬化させることなくリペア作業を行え、再利用可能な基板を良好な状態でボンドから剥離させることができる。
【図面の簡単な説明】
【図１】（ａ）本発明の一実施の形態の電子部品の実装方法の工程説明図
（ｂ）本発明の一実施の形態の電子部品の実装方法の工程説明図
（ｃ）本発明の一実施の形態の電子部品の実装方法の工程説明図
【図２】（ａ）本発明の一実施の形態の電子部品の実装方法の工程説明図
（ｂ）本発明の一実施の形態の電子部品の実装方法の工程説明図
（ｃ）本発明の一実施の形態の電子部品の実装方法の工程説明図
【符号の説明】
１ 基板
２ 電極
３ ボンド
４ チップ
４ａ 金属バンプ
５ 熱圧着ヘッド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component mounting method in which an electronic component is mounted on a substrate by bonding.
[0002]
[Prior art]
As a method of mounting an electronic component such as a semiconductor chip on a substrate, a method of bonding the chip by bonding is used. The bond is a thermosetting resin adhesive, and the bond is cured by holding a predetermined temperature condition for a predetermined time in a state where the chip is mounted on the bond supplied onto the substrate. Fixed to the substrate with strength. Then, after mounting, a function test is performed to test the operation state with the chip connected to the substrate. Of those determined to be defective in this functional inspection, it is desirable to remove and reuse the parts determined to be reusable.
[0003]
[Problems to be solved by the invention]
However, the bond between the chip and the substrate after the bond is completely cured can be peeled off while maintaining a good interface between the bond and the substrate or the bond and the chip because the intervening bond is firmly fixed. difficult. For this reason, even though it is a functionally reusable part in the past, it is difficult to remove it in a good state, and in most cases it is disposed of, and effective use of resources is achieved. There was a problem that not.
[0004]
SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic component mounting method in which components after mounting can be easily removed and components can be effectively used.
[0005]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a method for mounting an electronic component comprising: a bond supplying step of supplying a thermosetting bond for bonding an electronic component to a substrate; and an electron held on a lower surface of a thermocompression head at a mounting portion to which the bond is supplied. A mounting process for mounting components, a temporary curing process for temporarily curing the bond, an inspection process for performing a functional test on the substrate in a state where the bond is temporarily cured, and a board that has been determined to pass by the functional test. A main curing step of curing, and in the temporary curing step, the electronic component is heated from the upper surface by the thermocompression bonding head, and the bond is cured more rapidly on the upper side, whereby the bonding strength between the substrate and the bond is more than In addition, by curing the bond so that the bonding strength between the electronic component and the bond is greater, the bond that has been determined to be rejected in the functional inspection is In the temporarily cured state, and to reuse the substrate by separating the electronic component, wherein the substrate and the bond is stuck.
[0007]
According to the present invention, the bonding strength between the electronic component and the bond is larger than the bonding strength between the substrate and the bond in the temporary curing process that is performed prior to the function inspection and temporarily bonds the bond for bonding the electronic component. By curing the bond, a repair operation can be performed on the substrate that has been determined to be rejected by the functional inspection without being fully cured, and the reusable substrate can be peeled from the bond in a good state.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. 1A, 1B, 1C, 2A, 2B, and 2C are explanatory diagrams of processes of the electronic component mounting method according to the embodiment of the present invention. 1A, 1B, 1C, 2A, 2B, and 2C show the mounting method in the order of steps.
[0009]
First, in FIG. 1A, electrodes 2 and 2a are formed on a substrate 1. The electrode 2 is provided for connection to a semiconductor chip which is an electronic component (hereinafter simply referred to as “chip”), and the electrode 2a is brought into contact with an inspection probe at the time of function inspection performed after mounting the chip. This circuit is for conducting the circuit with the inspection device. A bond 3 that is a thermosetting resin adhesive is supplied around the electrode 2 of the substrate 1. As a supply method of the bond 3, a method of applying by a dispenser, a method of printing a bond on a supply site by screen printing, or the like is used.
[0010]
Next, as shown in FIG. 1B, the chip 4 held on the lower surface of the thermocompression bonding head 5 is mounted around the electrode 2 to which the bond 3 is supplied, that is, on the mounting portion where the chip is mounted. . Metal bumps 4 a are formed on the lower surface of the chip 4, and the chip 4 is electrically connected to a circuit provided on the substrate 1 by pressing the metal bump 4 a against the electrode 2.
[0011]
Thereafter, as shown in FIG. 1C, the heating means provided in the thermocompression bonding head 5 is driven to heat the chip 4 from the upper surface, and the thermocompression bonding head 5 presses the chip 4 with a predetermined load. Thereby, the metal bumps 4a are pressed against the surface of the electrode 2 and good conduction is obtained. And the hardening of the bond 3 proceeds by continuing the heating. The heating performed here is not performed under the condition that the bond 3 is completely cured, but is performed in such a manner that the curing of the bond 3 is temporarily interrupted while being incomplete. For example, if the heating temperature of 170 ° C. is continued for 60 seconds and the heating condition for complete curing is, heating at this temperature is performed for about 10 seconds and then the heating is stopped. That is, this heating process is a temporary curing process for the bond 3.
[0012]
At this time, with respect to the bond 3 existing between the chip 4 and the substrate 1, heat is transmitted from above through the chip 4, so that the cured state of the bond 3 is not uniform and the heat is transmitted upward. Curing proceeds faster on the side (see the broken line portion shown in FIG. 1 (c)). Therefore, in the temporary curing step, the bond 3 is cured so that the bonding strength between the chip 4 and the bond 3 is larger than the bonding strength between the substrate 1 and the bond 3.
[0013]
After this temporary curing step, the substrate 1 on which the chip 4 is mounted is sent to an inspection step, where a functional inspection is performed. The function inspection is to inspect whether or not the operation of the electronic circuit composed of the chip 4 and the substrate 1 is normal in a state where the chip 4 is connected to the substrate 1, and as shown in FIG. A predetermined inspection is performed by bringing the probe 6 (not shown) into contact with the electrode 2 a of the substrate 1.
[0014]
As a result of this functional inspection, those that are judged to be acceptable without being detected are sent to the main curing process. Here, by continuing heating at a predetermined temperature for a predetermined time, as shown in FIG. 2B, the curing reaction of the bond 3 in the temporarily cured state is further advanced to be completely cured. Thereby, the mounting of the chip 4 on the substrate 1 is completed.
[0015]
On the other hand, the substrate 1 in which an abnormality is detected in the function inspection is not sent to the main curing process, and it is determined whether or not the component can be reused. And the board | substrate 1 judged that the chip | tip 4 can be reused here is sent to a repair process, and the operation | work which isolate | separates the chip | tip 4 and the board | substrate 1 is performed in a repair process. In this separation operation, as shown in FIG. 2C, an operation of peeling the chip 4 upward with the tool 7 is performed in a state where the bond 3 is temporarily cured.
[0016]
At this time, as described above, in the temporary curing step, a curing process is employed in which the bonding strength between the chip 4 and the bond 3 is larger than the bonding strength between the substrate 1 and the bond 3. The peeling surface is formed at the interface between the substrate 1 and the bond 3. Accordingly, the substrate 1 is separated from the chip 4 to which the bond 3 is fixed in a good state. That is, since there is no adhesion of the bond 3 hindering the mounting of the chip 4 on the mounting surface of the substrate 1, it can be reused for mounting a new chip.
[0017]
As described above, when the bond 3 is temporarily cured, by adopting a curing process in which the bonding strength between the chip 4 and the bond 3 is larger than the bonding strength between the substrate 1 and the bond 3, The substrate can be removed in a good state in the repair after the function test. In other words, by applying this embodiment to mounting using a type of substrate with a high unit price, even if an abnormality is detected in the function inspection, the substrate can be reused if there is no defect. And effective use of resources is promoted.
[0018]
【The invention's effect】
According to the present invention, the bonding strength between the electronic component and the bond is larger than the bonding strength between the substrate and the bond in the temporary curing process that is performed prior to the function inspection and temporarily bonds the bond for bonding the electronic component. By curing the bond, a repair operation can be performed on the substrate that has been determined to be rejected by the functional inspection without being fully cured, and the reusable substrate can be peeled from the bond in a good state.
[Brief description of the drawings]
FIG. 1A is a process explanatory diagram of an electronic component mounting method according to an embodiment of the present invention. FIG. 1B is a process explanatory diagram of an electronic component mounting method according to an embodiment of the present invention. FIG. 2A is a process explanatory diagram of an electronic component mounting method according to an embodiment of the present invention. FIG. 2B is a process explanatory diagram of an electronic component mounting method according to an embodiment of the present invention. Process explanatory diagram of component mounting method (c) Process explanatory diagram of electronic component mounting method according to an embodiment of the present invention
1 Substrate 2 Electrode 3 Bond 4 Chip 4a Metal bump 5 Thermocompression head

Claims (1)

基板に電子部品接着用の熱硬化性のボンドを供給するボンド供給工程と、ボンドが供給された実装部位に熱圧着ヘッドの下面に保持された電子部品を搭載する搭載工程と、前記ボンドを仮硬化させる仮硬化工程と、ボンドが仮硬化した状態で前記基板の機能検査を行う検査工程と、機能検査によって合格判定された基板について前記ボンドを本硬化させる本硬化工程とを含み、前記仮硬化工程において、前記熱圧着ヘッドにより電子部品を上面から加熱してボンドを上方側をより速く硬化進行させることにより、前記基板とボンドとの接合強度よりも電子部品とボンドとの接合強度の方が大きくなるようにボンドを硬化させることにより、前記機能検査において不合格判定された基板について、ボンドが仮硬化の状態で、前記基板とボンドが固着した前記電子部品を分離させて基板を再利用することを特徴とする電子部品の実装方法。A bond supplying step of supplying a thermosetting bond for bonding the electronic component to the substrate; a mounting step of mounting the electronic component held on the lower surface of the thermocompression bonding head on the mounting portion to which the bond is supplied; A temporary curing step for curing, an inspection step for performing a functional inspection of the substrate in a state where the bond is temporarily cured, and a main curing step for main curing the bond with respect to a substrate that has been determined to be acceptable by the functional inspection. In the process, the bonding strength between the electronic component and the bond is higher than the bonding strength between the substrate and the bond by heating the electronic component from the upper surface by the thermocompression bonding head and causing the bond to cure faster at the upper side. by curing the bond so as to increase, for a substrate that has been rejected determined in the function test, the bond is in the temporarily cured state, the substrate and the bond is Mounting method of electronic components to wear the electronic components to separate, characterized in reusing the substrate.
JP12960699A 1999-05-11 1999-05-11 Electronic component mounting method Expired - Lifetime JP3915317B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022099744A1 (en) * 2020-11-11 2022-05-19 联合微电子中心有限责任公司 Method for temporarily bonding and de-bonding semiconductor device, and semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3402267B2 (en) * 1999-06-23 2003-05-06 ソニーケミカル株式会社 Electronic element mounting method
JP6019983B2 (en) * 2012-09-18 2016-11-02 日本電気株式会社 Semiconductor package inspection method and mounting method and mounting structure using the same
CN112385025B (en) * 2018-11-21 2024-01-30 东北微科技株式会社 Stacked semiconductor device and multiple chips used therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022099744A1 (en) * 2020-11-11 2022-05-19 联合微电子中心有限责任公司 Method for temporarily bonding and de-bonding semiconductor device, and semiconductor device

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