WO2022099744A1

WO2022099744A1 - Method for temporarily bonding and de-bonding semiconductor device, and semiconductor device

Info

Publication number: WO2022099744A1
Application number: PCT/CN2020/129749
Authority: WO
Inventors: 王淼; 曾怀望; 焦文龙; 杨睿峰; 李嗣晗
Original assignee: 联合微电子中心有限责任公司
Priority date: 2020-11-11
Filing date: 2020-11-18
Publication date: 2022-05-19
Also published as: CN112382599B; CN112382599A

Abstract

Disclosed are a method for temporarily bonding and de-bonding a semiconductor device, and a semiconductor device. The method for temporarily bonding and de-bonding the semiconductor device comprises: forming a first metal layer on a first wafer, the first wafer being internally provided with a device structure, and the first metal layer being formed on one side of the first wafer close to the device structure (110); forming a second metal layer corresponding to the first metal layer on a second wafer (120); bonding the second metal layer to the first metal layer, such that a second wafer is bonded to the first wafer (130); performing a backside process on one side of the first wafer away from the device structure (140); and performing de-bonding by means of electrochemical anodic metal dissolution, so as to separate the first wafer from the second wafer (150).

Description

Method for temporary bonding and debonding of semiconductor device and semiconductor device

technical field

The present disclosure relates to semiconductor technology, and in particular, to a method for temporary bonding and debonding of semiconductor devices and semiconductor devices.

Background technique

In the semiconductor integration process, after the device layer processing is performed on the front side of the wafer, it is sometimes necessary to perform related processes on the back side of the wafer. In order to avoid the occurrence of chipping or bending deformation of the wafer in the backside process, the wafer can be temporarily bonded to another wafer or carrier with a similar diameter before the backside process of the wafer, so as to realize the support. After backside processing of the wafer, the wafer is debonded from another wafer or slide to achieve separation of the two.

Temporary bonding of a wafer to another wafer or slide can be achieved using a temporary bonding material, for example, an organic material such as a temporary bonding paste or photoresist can be used. However, such temporary bonding materials have poor high temperature resistance and poor compatibility with backside processes after bonding. In order to achieve debonding, mechanical debonding or solvent dissolution debonding can be used. However, shear forces during mechanical debonding tend to damage wafers, resulting in lower yields. In the process of solvent dissolving and debonding, since the dissolving agent slowly dissolves the temporary bonding glue from the edge of the wafer, it takes a long time for the dissolving agent to reach the center of the wafer, and the debonding efficiency is low.

SUMMARY OF THE INVENTION

It would be advantageous to provide a mechanism that alleviates, alleviates or even eliminates one or more of the above problems.

According to some embodiments of the present disclosure, there is provided a method for temporary bonding and debonding of a semiconductor device, comprising: forming a first metal layer on a first wafer in which a device structure is formed and the first metal layer is formed layer is formed on a side of the first wafer close to the device structure; a second metal layer is formed on the second wafer corresponding to the first metal layer; the second metal layer is bonded to the first metal layer such that the first metal layer is The two wafers are bonded to the first wafer; the backside process is performed on the side of the first wafer away from the device structure; and the debonding is performed by electrochemical anodic metal dissolution, so that the first wafer and the second wafer are separated.

According to some embodiments of the present disclosure, there is provided a semiconductor device fabricated by the above-described method.

These and other aspects of the present disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.

Description of drawings

Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

1 is a flowchart of a method for temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure;

2A-2F are schematic diagrams of example structures of semiconductor devices formed in various steps of a method for temporary bonding and debonding of semiconductor devices according to example embodiments of the present disclosure; and

3A-3C are schematic diagrams of debonding by electrochemical anodic metal dissolution according to an exemplary embodiment of the present disclosure.

Detailed ways

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections It should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatially relative terms such as "below", "below", "lower", "below", "above", "above", etc. may be used herein for convenience Description is used to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "beneath" other elements or features would then be oriented "under the other elements or features" above the characteristics". Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. Terms such as "before" or "before" and "after" or "followed by" may similarly be used, for example, to indicate the order in which light travels through elements. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprising" and/or "comprising" when used in this specification designate the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more The presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof of other features, integers, steps, operations, elements, components and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" means A only, B only, or both A and B.

It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to another element or layer" When present, it may be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," "directly adjacent to" another element or layer , with no intervening elements or layers present. However, in no case should "on" or "directly on" be interpreted as requiring a layer to completely cover the layer below.

Embodiments of the disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the disclosure. As such, variations to the shapes of the illustrations are to be expected, eg, as a result of manufacturing techniques and/or tolerances. Accordingly, embodiments of the present disclosure should not be construed as limited to the particular shapes of the regions illustrated herein, but are to include deviations in shapes due, for example, to manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the relevant art and/or the context of this specification, and will not be idealized or overly interpreted in a formal sense, unless expressly defined as such herein.

Exemplary embodiments of the present disclosure provide a method of temporary bonding and debonding of semiconductor devices. In this method, temporary bonding between wafers can be achieved by metal-metal bonding and debonding by electrochemical anodic metal dissolution. Thereby, not only the bond strength of the temporary bond is high, and the high temperature resistance is improved, but also the debonding efficiency can be improved.

As used herein, the term "substrate" may refer to the substrate of a diced wafer, or may refer to the substrate of an un-diced wafer. Similarly, the terms chip and die are used interchangeably, unless such interchange would create a conflict. It should be understood that the term "layer" includes films and should not be construed to indicate vertical or horizontal thickness unless otherwise specified.

FIG. 1 is a flowchart of a method 100 for temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure, and FIGS. 2A-2F are diagrams of temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure. Schematic diagrams of example structures of semiconductor devices formed in various steps of the method. Methods of temporary bonding and debonding of semiconductor devices according to exemplary embodiments of the present disclosure are described below with reference to FIGS. 1 and 2A-2F.

As shown in FIGS. 1 and 2A , in step 110 , a first metal layer 214 is formed on the first wafer 210 . The first wafer 210 has device structures 211 formed therein and a first metal layer 214 is formed on a side of the first wafer 210 close to the device structures 211 .

The first wafer 210 may be any type of wafer. For example, the first wafer 210 may include a substrate and device structures 211 formed on the substrate. The substrate may be made of any suitable material, for example, may be made of at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S- SiGeOI) and silicon germanium on insulator (SiGeOI), etc. Further, the substrate may also be an N-type substrate or a P-type substrate. As used herein, the term "wafer" may refer to a diced wafer, or may refer to a non-diced wafer. The device structure 211 may be any semiconductor device structure formed by a semiconductor process. For example, the device structure 211 may be a passive device, an active device, a MEMS (Micro Electro Mechanical Systems, micro-electromechanical systems) device, an interconnect structure, or the like.

According to some embodiments, the method according to an exemplary embodiment of the present disclosure may further include forming a passivation layer 212 on the first wafer 210 before forming the first metal layer 214 on the first wafer 210 . Forming the passivation layer 212 and the first metal layer 214 on the first wafer 210 may include: forming a passivation material layer on the side of the first wafer 210 close to the device structure 211 ; forming a passivation material layer on the passivation material layer a first metal material layer; and sequentially patterning the first metal material layer and the passivation material layer to form the passivation layer 212 and the first metal layer 214 . For example, the first metal material layer and the passivation material layer may be patterned through photolithography and etching processes, but the present disclosure is not limited thereto. Any suitable process capable of patterning the first layer of metallic material and the layer of passivation material may be selected depending on the specific application and/or requirements.

The passivation layer 212 may be formed of a passivation material, such as oxide, nitride, or oxynitride. By forming the passivation layer 212, it is possible to prevent the direct contact between the metal wiring electrically connected to the device structure 211 and the first metal layer 214, thereby preventing the occurrence of a short circuit. According to some embodiments, the passivation layer 212 may also be formed of a polymer with good temperature resistance, such as polyimide. By selecting a polymer with good temperature resistance to form the passivation layer, damage to the passivation layer during the formation of the first metal layer and during the bonding process of the first metal layer and the second metal layer can be avoided.

The passivation layer may be formed through a deposition process. It should be understood that other processes are possible and are not limited here.

In some examples, the first metal layer may be formed on the passivation layer by any suitable process. For example, vapor deposition, sputtering, or the like.

It should be understood that the passivation layer may also be omitted in other possible embodiments, which is not limited herein. For the convenience of description, the method for temporarily bonding and debonding a semiconductor device according to an exemplary embodiment of the present disclosure will be described below with reference to FIGS.

As shown in FIG. 2A , in some embodiments, the passivation layer 212 and the first metal layer 214 expose the pad region 213 formed on the first wafer 210 . This helps the device structure 211 formed in the first wafer 210 to be easily electrically connected with other structures after debonding.

As shown in FIGS. 1 and 2B , in step 120 , a second metal layer 218 corresponding to the first metal layer 214 is formed on the second wafer 216

In some examples, the second metal layer 218 may be formed on the second wafer 216 by any suitable process. For example, vapor deposition, sputtering, or the like.

The location of the second metal layer 218 formed on the second wafer 216 may correspond to the location of the first metal layer 214 . For example, the second metal layer 218 may be formed by forming a second metal material layer on the second wafer 216 and patterning the second metal material layer. In some examples, the second metal material layer formed on the second wafer 216 may not be patterned, and the second metal material layer formed is directly used as the second metal layer 218, thereby saving process flow. The second wafer 216 can be used as a support wafer to support the first wafer 210 .

According to some embodiments, the material of the second metal layer 218 may be the same as the material of the first metal layer 214 , for example, the material forming the first metal layer 214 and the second metal layer 218 may be aluminum. The compatibility between aluminum metal and semiconductor technology is good, and the bonding strength of aluminum-aluminum metal bonding is high and high temperature resistance is good. advantageous. Although aluminum may be selected as the material for forming the first metal layer 214 and the second metal layer 218, the present disclosure is not limited thereto. Depending on the specific application and/or requirements, any metal material that can achieve metal-metal bonding and can be debonded by electrochemical anodic metal dissolution can be selected.

In some embodiments, the material of the second metal layer 218 may also be different from the material of the first metal layer 214. For example, the material of the first metal layer 214 may be aluminum, and the material of the second metal layer 218 may be aluminum-copper alloy, Aluminum-silicon-copper alloys, etc., are not limited here.

The second wafer 216 may be formed of a conductive material or a non-conductive material. For example, the second wafer 216 may be formed of silicon, glass or ceramic material. According to some embodiments, the second wafer 216 may be formed of low resistance silicon doped to provide electrical conductivity.

In the case where the second wafer 216 is formed of a non-conductive material, as shown in FIG. 2B ′, the method for temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure may further include: on the second wafer 216 A third metal layer 217 is formed on the second wafer 216 before the second metal layer 218 corresponding to the first metal layer 214 is formed thereon. The corrosion potential of the material forming the third metal layer 217 is higher than the corrosion potential of the material forming the first and second metal layers, so that the third metal layer is less prone to electrochemical dissolution than the first and second metal layers.

When the materials of the first and second metal layers are aluminum, the material of the third metal layer may be a metal with a higher corrosion potential than aluminum, such as chromium or copper. In some examples, the material of the third metal layer may also be an alloy, such as an alloy in which two or more metal crystals form a mechanical mixture or other forms of alloys.

In the following description, the second wafer structure shown in FIG. 2B is mainly described, but it should be understood that the second wafer structure shown in FIG. 2B' may also be used.

As shown in FIGS. 1 and 2C , in step 130 , the second metal layer 218 is bonded to the first metal layer 214 such that the second wafer 216 is bonded to the first wafer 210 .

Step 130 may be implemented through a bonding process. In the example shown in FIG. 2C , the structure shown in FIG. 2B is now flipped so that the second metal layer 218 formed on the second wafer 216 in FIG. 2B can interact with the first metal layer 218 formed on the first wafer 210 in FIG. The metal layer 214 is bonded. For example, the second metal layer 218 may be bonded to the first metal layer 214 by thermocompression. FIG. 2C shows a schematic diagram after bonding the second metal layer 218 and the first metal layer 214 , wherein the metal layers 214 / 218 are the state after the first metal layer 214 and the second metal layer 218 are bonded.

According to some embodiments, the thickness of each of the first metal layer 214 and the second metal layer 218 may be 0.1 μm˜50 μm.

According to some embodiments, the bonding temperature for bonding the second metal layer 218 to the first metal layer 214 may be 25°C to 500°C. This temperature range generally does not affect the device structure 211 of the first wafer 210, and can well bond the first metal layer 214 and the second metal layer 218 together.

As shown in FIG. 1 and FIGS. 2D and 2E , in step 140 , a backside process is performed on a side of the first wafer 210 away from the device structure 211 .

In this disclosure, any process performed on the side of the first wafer away from the device structure may be referred to as a backside process.

In some embodiments, after bonding the second metal layer 218 to the first metal layer 214, the temperature of the backside process performed on the side of the first wafer 210 remote from the device structures 211 does not exceed the temperature for forming the first metal layer The temperature tolerance of the material of layer 214 and second metal layer 218 . Metals have a higher temperature tolerance, so wafers with metal-to-metal bonding are more adaptable to backside processes in many forms and conditions.

According to some exemplary embodiments, after the bonding is completed, the first wafer may be thinned, or other backside processes may be performed according to specific applications and/or requirements, which are not limited herein.

For example, as shown in FIG. 2D , the backside process may include thinning the first wafer 210 on a side of the first wafer 210 remote from the device structures 211 . The thinned first wafer can exhibit flexible features such as bendability and extensibility, thereby helping to form flexible semiconductor devices.

As shown in FIG. 2E , according to some embodiments, the backside process may further include forming a protective layer 220 on a side of the first wafer 210 away from the device structure 211 after thinning the first wafer 210 .

According to some embodiments, forming the protective layer 220 on the side of the first wafer 210 away from the device structure 211 may include: forming a protective material layer on the side of the first wafer 210 away from the device structure 211 , and forming the protective material layer on the side of the first wafer 210 away from the device structure 211 Curing is performed to form the protective layer 220 . By forming the protective layer, a protective effect can be formed on the thinned first wafer, and further contribute to realizing a bendable or foldable flexible semiconductor device after debonding.

According to some embodiments, the protective material layer may include polyimide (PI). For example, polyimide may be formed on a side of the first wafer 210 away from the device structure 211 by a spin coating process. The polyimide is then cured at a temperature of about 350°C to form a protective layer.

Although the schematic diagram shown in FIG. 2E shows that the protective layer 220 is further formed after the first wafer 210 is thinned, it should be understood that in the case where the first wafer 210 does not need to be thinned, the first wafer 210 can also be The protective layer 220 is directly formed on the un-thinned first wafer 210 .

According to some embodiments, the backside process may include forming another device structure on a side of the first wafer 210 remote from the device structure 211 . The other device structure may be a device structure formed by any suitable semiconductor process, which is not limited herein. For example, another device structure may be a passive device, an active device, a MEMS device, an interconnect structure, or the like, according to specific applications and/or requirements.

As shown in FIGS. 1 and 2F , in step 150 , debonding is performed by electrochemical anodic metal dissolution to separate the first wafer 210 from the second wafer 216 . Figure 2F shows the first wafer after debonding.

It should be understood that FIGS. 2A to 2F are merely schematic diagrams of example structures formed in various steps of a method for temporary bonding and debonding of semiconductor devices according to example embodiments of the present disclosure, and the thicknesses and sizes shown in the figures are not Not necessarily indicative of actual thickness and size.

As shown in FIG. 3A, according to some embodiments, the positive electrode of the voltage source for electrochemical anodic metal dissolution is connected to the second wafer 216, and the negative electrode of the voltage source is connected to the cathode 312, which is immersed in the electrode for electrochemical anodic metal dissolution. The anode metal is dissolved in solution 310 .

According to some embodiments, the second wafer 216 may be formed of a conductive material, and the anode of the voltage source is connected to a predetermined location of the second wafer 216, eg, as shown in FIG. 3A. In this case, the second wafer 216 connected to the positive electrode of the voltage source can be used as the anode during the electrochemical anodic metal dissolution process.

According to some embodiments, as shown in FIG. 2B ′ above, the second wafer 216 may also be formed of a non-conductive material, and before the second metal layer 218 corresponding to the first metal layer 214 is formed on the second wafer 216 , A third metal layer 217 is formed on the second wafer 216 , and the corrosion potential of the material forming the third metal layer 217 is higher than the corrosion potential of the material forming the first metal layer 214 and the second metal layer 218 . In the case where the third metal layer 217 is formed on the second wafer 216 , the positive electrode of the voltage source for electrochemical anodic metal dissolution may be connected to the third metal layer 217 . In this case, the third metal layer 217 connected to the positive electrode of the voltage source can function as the anode during the electrochemical anodic metal dissolution process.

According to some embodiments, the material forming the cathode 312 is an inert material. For example, cathode 312 may be formed of materials such as platinum, gold, lead, or graphite, or mixtures thereof.

According to some embodiments, the solution 310 for electrochemical anode metal dissolution may be an aqueous neutral electrolyte solution. For example, the neutral electrolyte aqueous solution may be one of the group consisting _of : _NaCl solution, _Na2SO4 solution, _MgCl2 solution, _KCl solution, _K2SO4 solution, _K2NO3 solution, and _Na2NO ₃ solutions. The neutral solution has less pollution to the environment, which is in line with the current industrial environmental protection trend.

According to some embodiments, the solution for dissolving the metal in the electrochemical anode may also be a weakly acidic solution or a weakly basic solution, such as MgSO ₄ , etc., which is not limited herein.

Figure 3B schematically shows the reaction process of electrochemical anode metal dissolution. As shown in FIG. 3B, the first and second metal layers 214/218, which have been bonded together, can be dissolved by utilizing electrochemical anodic metal dissolution.

For example, when the material of the first metal layer and the second metal layer is aluminum, in the process of electrochemical anode metal dissolution, the anode reaction can generate aluminum ions: Al→Al ³⁺ +3e ^- , and the cathode reaction can generate hydrogen gas: 2H ⁺ +2e ^- →H ₂ .

Different from the conventional solvent dissolution debonding method, during the electrochemical anodic metal dissolution process, although the metal regions such as the pads exposed by the passivation layer 212 and the first metal layer 214 may also be immersed in the solution, due to these metals The region does not participate in the anodic reaction, so dissolution does not occur. This, to a certain extent, increases the degree of freedom of material selection for the metal regions, such as pads, formed on the first wafer.

According to some embodiments, as shown in FIG. 2B' described above, in the case where the third metal layer 217 is formed on the second wafer 216, the voltage applied by the voltage source may be within a predetermined range such that at least the first metal layer is 214 can dissolve but the third metal layer 217 does not dissolve. For example, when the material of the first and second metal layers is aluminum and the material of the third metal is chromium, the voltage of the voltage source is adjusted so that the aluminum can be dissolved without the chromium being dissolved during the electrochemical anodic metal dissolution process.

Figure 3C schematically shows the state after the electrochemical anode metal dissolution process has ended. As shown in FIG. 3C , the first metal layer 214 and the second metal layer 218 have been dissolved, so that the first wafer 210 and the second wafer 216 are debonded and separated.

During the electrochemical anode metal dissolution process as shown in FIGS. 3A to 3C , the debonding speed of the first wafer 210 and the second wafer 216 can be controlled by appropriately adjusting the voltage value of the voltage source until the first wafer 210 completely separated from the second wafer 216 .

By performing metal-metal bonding and using electrochemical anodic metal dissolution for debonding, the removal rate of the bonded metal layer can be high, thereby improving the efficiency of debonding. In addition, the speed of debonding can be controlled by selecting the corresponding materials and adjusting the voltage value of the voltage source used for electrochemical anode metal dissolution, which contributes to better controllability. Compared with mechanical debonding, debonding by electrochemical anodic metal dissolution also avoids damage to wafers due to shear forces, thereby improving yield.

Methods of temporary bonding and debonding of semiconductor devices according to exemplary embodiments of the present disclosure and various variations thereof are described above with respect to FIGS. 1 , 2A-2F, and 3A-3C. It will be understood that there is no requirement that the steps or operations described must be performed in the particular order described, nor that all steps or operations described must be performed to achieve desired results. For example, the step of forming the second metal layer on the second wafer may be performed before the step of forming the first metal layer on the first wafer.

According to an embodiment of the present disclosure, there is also provided a semiconductor device, which can be manufactured by the above-described method. Embodiments of methods of temporary bonding and debonding of semiconductor devices have been described so that the structure of the resulting semiconductor device will be clear. Embodiments of semiconductor devices can provide the same or corresponding advantages as method embodiments, a detailed description of which is omitted for brevity.

While the present disclosure has been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustration and description are to be considered illustrative and schematic and not restrictive; example. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "a plurality" means two or more . The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

A method for temporary bonding and debonding of semiconductor devices, comprising:

forming a first metal layer on a first wafer in which device structures are formed and the first metal layer is formed on a side of the first wafer close to the device structures;

forming a second metal layer corresponding to the first metal layer on the second wafer;

bonding the second metal layer to the first metal layer such that the second wafer is bonded to the first wafer;

performing a backside process on a side of the first wafer remote from the device structures; and

Debonding is performed by electrochemical anodic metal dissolution to separate the first wafer from the second wafer.
The method of claim 1, wherein the material for forming the first metal layer is aluminum.
The method of claim 2, wherein the material of the second metal layer is one selected from the group consisting of aluminum, aluminum copper, and aluminum silicon copper.
The method of claim 1, wherein the temperature of the backside process does not exceed a tolerance temperature of a material forming the first metal layer and the second metal layer.
The method of claim 1, wherein a positive electrode of a voltage source for the electrochemical anode metal dissolution is connected to the second wafer, and,

Therein, the negative electrode of the voltage source is connected to a cathode which is immersed in a solution for metal dissolution of the electrochemical anode.
6. The method of claim 5, wherein the material from which the cathode is formed is an inert material.
7. The method of claim 6, wherein the inert material is one of the group consisting of platinum, gold, graphite.
6. The method of claim 5, wherein the second wafer is formed of a conductive material, and the positive electrode of the voltage source is connected to a predetermined location on the second wafer.
The method of claim 5, wherein the second wafer is formed of a non-conductive material, and the method further comprises:

forming a third metal layer on the second wafer before forming the second metal layer corresponding to the first metal layer on the second wafer,

Wherein, the corrosion potential of the material forming the third metal layer is higher than the corrosion potential of the material forming the first and second metal layers, and the positive electrode of the voltage source is connected to the third metal layer.
9. The method of claim 9, wherein the voltage applied by the voltage source is within a predetermined range such that the first metal layer can dissolve but the third metal layer does not dissolve.
The method of claim 1, wherein the solution used for the electrochemical anode metal dissolution is a neutral electrolyte aqueous solution.
The method of claim 11, wherein the neutral electrolyte aqueous solution is one or more of the group consisting of: NaCl solution, Na 2 SO 4 solution, MgCl 2 solution, KCl solution, K 2 SO4 solution, K2NO3 solution and Na2NO3 solution .
The method of claim 1, further comprising forming a passivation layer on the first wafer before forming a first metal layer on the first wafer, and

Wherein, forming the passivation layer and the first metal layer on the first wafer includes:

forming a passivation material layer on the side of the first wafer close to the device structure;

On the passivation material layer, a first metal material layer is formed; and

The first metal material layer and the passivation material layer are sequentially patterned to form the passivation layer and the first metal layer.
14. The method of claim 13, wherein the passivation layer and the first metal layer expose pad regions formed on the first wafer.
The method of claim 1, wherein the backside process comprises thinning the first wafer on a side of the first wafer remote from the device structure.
16. The method of claim 15, wherein the backside process further comprises: after thinning the first wafer, forming a protective layer on a side of the first wafer away from the device structure .
17. The method of claim 16, wherein forming a protective layer on a side of the first wafer remote from the device structure comprises:

forming a protective material layer on a side of the first wafer away from the device structure; and

The protective material layer is cured to form the protective layer.
18. The method of claim 17, wherein the protective material layer comprises polyimide.
The method of claim 1, wherein the backside process comprises forming another device structure on a side of the first wafer remote from the device structure.
A semiconductor device, wherein the semiconductor device is manufactured by the method of any one of claims 1-19.