WO2022099744A1 - Procédé de liaison et de dissociation temporaires de dispositif à semi-conducteur et dispositif à semi-conducteur - Google Patents

Procédé de liaison et de dissociation temporaires de dispositif à semi-conducteur et dispositif à semi-conducteur Download PDF

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Publication number
WO2022099744A1
WO2022099744A1 PCT/CN2020/129749 CN2020129749W WO2022099744A1 WO 2022099744 A1 WO2022099744 A1 WO 2022099744A1 CN 2020129749 W CN2020129749 W CN 2020129749W WO 2022099744 A1 WO2022099744 A1 WO 2022099744A1
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wafer
metal layer
layer
metal
forming
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PCT/CN2020/129749
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English (en)
Chinese (zh)
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王淼
曾怀望
焦文龙
杨睿峰
李嗣晗
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联合微电子中心有限责任公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8334—Bonding interfaces of the layer connector
    • H01L2224/83359—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/98—Methods for disconnecting semiconductor or solid-state bodies

Definitions

  • the present disclosure relates to semiconductor technology, and in particular, to a method for temporary bonding and debonding of semiconductor devices and semiconductor devices.
  • the wafer can be temporarily bonded to another wafer or carrier with a similar diameter before the backside process of the wafer, so as to realize the support. After backside processing of the wafer, the wafer is debonded from another wafer or slide to achieve separation of the two.
  • Temporary bonding of a wafer to another wafer or slide can be achieved using a temporary bonding material, for example, an organic material such as a temporary bonding paste or photoresist can be used.
  • a temporary bonding material for example, an organic material such as a temporary bonding paste or photoresist can be used.
  • such temporary bonding materials have poor high temperature resistance and poor compatibility with backside processes after bonding.
  • mechanical debonding or solvent dissolution debonding can be used.
  • shear forces during mechanical debonding tend to damage wafers, resulting in lower yields.
  • solvent dissolving and debonding since the dissolving agent slowly dissolves the temporary bonding glue from the edge of the wafer, it takes a long time for the dissolving agent to reach the center of the wafer, and the debonding efficiency is low.
  • a method for temporary bonding and debonding of a semiconductor device comprising: forming a first metal layer on a first wafer in which a device structure is formed and the first metal layer is formed layer is formed on a side of the first wafer close to the device structure; a second metal layer is formed on the second wafer corresponding to the first metal layer; the second metal layer is bonded to the first metal layer such that the first metal layer is The two wafers are bonded to the first wafer; the backside process is performed on the side of the first wafer away from the device structure; and the debonding is performed by electrochemical anodic metal dissolution, so that the first wafer and the second wafer are separated.
  • FIG. 1 is a flowchart of a method for temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure
  • 2A-2F are schematic diagrams of example structures of semiconductor devices formed in various steps of a method for temporary bonding and debonding of semiconductor devices according to example embodiments of the present disclosure.
  • 3A-3C are schematic diagrams of debonding by electrochemical anodic metal dissolution according to an exemplary embodiment of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections It should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
  • Terms such as “before” or “before” and “after” or “followed by” may similarly be used, for example, to indicate the order in which light travels through elements.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • Embodiments of the disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the disclosure. As such, variations to the shapes of the illustrations are to be expected, eg, as a result of manufacturing techniques and/or tolerances. Accordingly, embodiments of the present disclosure should not be construed as limited to the particular shapes of the regions illustrated herein, but are to include deviations in shapes due, for example, to manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
  • Exemplary embodiments of the present disclosure provide a method of temporary bonding and debonding of semiconductor devices.
  • temporary bonding between wafers can be achieved by metal-metal bonding and debonding by electrochemical anodic metal dissolution.
  • the bond strength of the temporary bond is high, and the high temperature resistance is improved, but also the debonding efficiency can be improved.
  • the term “substrate” may refer to the substrate of a diced wafer, or may refer to the substrate of an un-diced wafer.
  • the terms chip and die are used interchangeably, unless such interchange would create a conflict.
  • the term “layer” includes films and should not be construed to indicate vertical or horizontal thickness unless otherwise specified.
  • FIG. 1 is a flowchart of a method 100 for temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIGS. 2A-2F are diagrams of temporary bonding and debonding of a semiconductor device according to an exemplary embodiment of the present disclosure. Schematic diagrams of example structures of semiconductor devices formed in various steps of the method. Methods of temporary bonding and debonding of semiconductor devices according to exemplary embodiments of the present disclosure are described below with reference to FIGS. 1 and 2A-2F.
  • a first metal layer 214 is formed on the first wafer 210 .
  • the first wafer 210 has device structures 211 formed therein and a first metal layer 214 is formed on a side of the first wafer 210 close to the device structures 211 .
  • the first wafer 210 may be any type of wafer.
  • the first wafer 210 may include a substrate and device structures 211 formed on the substrate.
  • the substrate may be made of any suitable material, for example, may be made of at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S- SiGeOI) and silicon germanium on insulator (SiGeOI), etc.
  • the substrate may also be an N-type substrate or a P-type substrate.
  • the term "wafer” may refer to a diced wafer, or may refer to a non-diced wafer.
  • the device structure 211 may be any semiconductor device structure formed by a semiconductor process.
  • the device structure 211 may be a passive device, an active device, a MEMS (Micro Electro Mechanical Systems, micro-electromechanical systems) device, an interconnect structure, or the like.
  • MEMS Micro Electro Mechanical Systems, micro-electromechanical systems
  • the method according to an exemplary embodiment of the present disclosure may further include forming a passivation layer 212 on the first wafer 210 before forming the first metal layer 214 on the first wafer 210 .
  • Forming the passivation layer 212 and the first metal layer 214 on the first wafer 210 may include: forming a passivation material layer on the side of the first wafer 210 close to the device structure 211 ; forming a passivation material layer on the passivation material layer a first metal material layer; and sequentially patterning the first metal material layer and the passivation material layer to form the passivation layer 212 and the first metal layer 214 .
  • the first metal material layer and the passivation material layer may be patterned through photolithography and etching processes, but the present disclosure is not limited thereto. Any suitable process capable of patterning the first layer of metallic material and the layer of passivation material may be selected depending on the specific application and/or requirements.
  • the passivation layer 212 may be formed of a passivation material, such as oxide, nitride, or oxynitride. By forming the passivation layer 212, it is possible to prevent the direct contact between the metal wiring electrically connected to the device structure 211 and the first metal layer 214, thereby preventing the occurrence of a short circuit. According to some embodiments, the passivation layer 212 may also be formed of a polymer with good temperature resistance, such as polyimide. By selecting a polymer with good temperature resistance to form the passivation layer, damage to the passivation layer during the formation of the first metal layer and during the bonding process of the first metal layer and the second metal layer can be avoided.
  • a passivation material such as oxide, nitride, or oxynitride.
  • the passivation layer may be formed through a deposition process. It should be understood that other processes are possible and are not limited here.
  • the first metal layer may be formed on the passivation layer by any suitable process. For example, vapor deposition, sputtering, or the like.
  • the passivation layer may also be omitted in other possible embodiments, which is not limited herein.
  • the method for temporarily bonding and debonding a semiconductor device according to an exemplary embodiment of the present disclosure will be described below with reference to FIGS.
  • the passivation layer 212 and the first metal layer 214 expose the pad region 213 formed on the first wafer 210 . This helps the device structure 211 formed in the first wafer 210 to be easily electrically connected with other structures after debonding.
  • a second metal layer 218 corresponding to the first metal layer 214 is formed on the second wafer 216
  • the second metal layer 218 may be formed on the second wafer 216 by any suitable process. For example, vapor deposition, sputtering, or the like.
  • the location of the second metal layer 218 formed on the second wafer 216 may correspond to the location of the first metal layer 214 .
  • the second metal layer 218 may be formed by forming a second metal material layer on the second wafer 216 and patterning the second metal material layer.
  • the second metal material layer formed on the second wafer 216 may not be patterned, and the second metal material layer formed is directly used as the second metal layer 218, thereby saving process flow.
  • the second wafer 216 can be used as a support wafer to support the first wafer 210 .
  • the material of the second metal layer 218 may be the same as the material of the first metal layer 214 , for example, the material forming the first metal layer 214 and the second metal layer 218 may be aluminum.
  • the compatibility between aluminum metal and semiconductor technology is good, and the bonding strength of aluminum-aluminum metal bonding is high and high temperature resistance is good.
  • aluminum may be selected as the material for forming the first metal layer 214 and the second metal layer 218, the present disclosure is not limited thereto. Depending on the specific application and/or requirements, any metal material that can achieve metal-metal bonding and can be debonded by electrochemical anodic metal dissolution can be selected.
  • the material of the second metal layer 218 may also be different from the material of the first metal layer 214.
  • the material of the first metal layer 214 may be aluminum
  • the material of the second metal layer 218 may be aluminum-copper alloy, Aluminum-silicon-copper alloys, etc., are not limited here.
  • the second wafer 216 may be formed of a conductive material or a non-conductive material.
  • the second wafer 216 may be formed of silicon, glass or ceramic material.
  • the second wafer 216 may be formed of low resistance silicon doped to provide electrical conductivity.
  • the method for temporary bonding and debonding of a semiconductor device may further include: on the second wafer 216 A third metal layer 217 is formed on the second wafer 216 before the second metal layer 218 corresponding to the first metal layer 214 is formed thereon.
  • the corrosion potential of the material forming the third metal layer 217 is higher than the corrosion potential of the material forming the first and second metal layers, so that the third metal layer is less prone to electrochemical dissolution than the first and second metal layers.
  • the material of the third metal layer may be a metal with a higher corrosion potential than aluminum, such as chromium or copper.
  • the material of the third metal layer may also be an alloy, such as an alloy in which two or more metal crystals form a mechanical mixture or other forms of alloys.
  • the second wafer structure shown in FIG. 2B is mainly described, but it should be understood that the second wafer structure shown in FIG. 2B' may also be used.
  • step 130 the second metal layer 218 is bonded to the first metal layer 214 such that the second wafer 216 is bonded to the first wafer 210 .
  • Step 130 may be implemented through a bonding process.
  • the structure shown in FIG. 2B is now flipped so that the second metal layer 218 formed on the second wafer 216 in FIG. 2B can interact with the first metal layer 218 formed on the first wafer 210 in FIG.
  • the metal layer 214 is bonded.
  • the second metal layer 218 may be bonded to the first metal layer 214 by thermocompression.
  • FIG. 2C shows a schematic diagram after bonding the second metal layer 218 and the first metal layer 214 , wherein the metal layers 214 / 218 are the state after the first metal layer 214 and the second metal layer 218 are bonded.
  • the thickness of each of the first metal layer 214 and the second metal layer 218 may be 0.1 ⁇ m ⁇ 50 ⁇ m.
  • the bonding temperature for bonding the second metal layer 218 to the first metal layer 214 may be 25°C to 500°C. This temperature range generally does not affect the device structure 211 of the first wafer 210, and can well bond the first metal layer 214 and the second metal layer 218 together.
  • step 140 a backside process is performed on a side of the first wafer 210 away from the device structure 211 .
  • any process performed on the side of the first wafer away from the device structure may be referred to as a backside process.
  • the temperature of the backside process performed on the side of the first wafer 210 remote from the device structures 211 does not exceed the temperature for forming the first metal layer
  • Metals have a higher temperature tolerance, so wafers with metal-to-metal bonding are more adaptable to backside processes in many forms and conditions.
  • the first wafer may be thinned, or other backside processes may be performed according to specific applications and/or requirements, which are not limited herein.
  • the backside process may include thinning the first wafer 210 on a side of the first wafer 210 remote from the device structures 211 .
  • the thinned first wafer can exhibit flexible features such as bendability and extensibility, thereby helping to form flexible semiconductor devices.
  • the backside process may further include forming a protective layer 220 on a side of the first wafer 210 away from the device structure 211 after thinning the first wafer 210 .
  • forming the protective layer 220 on the side of the first wafer 210 away from the device structure 211 may include: forming a protective material layer on the side of the first wafer 210 away from the device structure 211 , and forming the protective material layer on the side of the first wafer 210 away from the device structure 211 Curing is performed to form the protective layer 220 .
  • a protective effect can be formed on the thinned first wafer, and further contribute to realizing a bendable or foldable flexible semiconductor device after debonding.
  • the protective material layer may include polyimide (PI).
  • PI polyimide
  • polyimide may be formed on a side of the first wafer 210 away from the device structure 211 by a spin coating process. The polyimide is then cured at a temperature of about 350°C to form a protective layer.
  • the protective layer 220 is further formed after the first wafer 210 is thinned, it should be understood that in the case where the first wafer 210 does not need to be thinned, the first wafer 210 can also be The protective layer 220 is directly formed on the un-thinned first wafer 210 .
  • the backside process may include forming another device structure on a side of the first wafer 210 remote from the device structure 211 .
  • the other device structure may be a device structure formed by any suitable semiconductor process, which is not limited herein.
  • another device structure may be a passive device, an active device, a MEMS device, an interconnect structure, or the like, according to specific applications and/or requirements.
  • step 150 debonding is performed by electrochemical anodic metal dissolution to separate the first wafer 210 from the second wafer 216 .
  • Figure 2F shows the first wafer after debonding.
  • FIGS. 2A to 2F are merely schematic diagrams of example structures formed in various steps of a method for temporary bonding and debonding of semiconductor devices according to example embodiments of the present disclosure, and the thicknesses and sizes shown in the figures are not Not necessarily indicative of actual thickness and size.
  • 3A-3C are schematic diagrams of debonding by electrochemical anodic metal dissolution according to an exemplary embodiment of the present disclosure.
  • the positive electrode of the voltage source for electrochemical anodic metal dissolution is connected to the second wafer 216, and the negative electrode of the voltage source is connected to the cathode 312, which is immersed in the electrode for electrochemical anodic metal dissolution.
  • the anode metal is dissolved in solution 310 .
  • the second wafer 216 may be formed of a conductive material, and the anode of the voltage source is connected to a predetermined location of the second wafer 216, eg, as shown in FIG. 3A.
  • the second wafer 216 connected to the positive electrode of the voltage source can be used as the anode during the electrochemical anodic metal dissolution process.
  • the second wafer 216 may also be formed of a non-conductive material, and before the second metal layer 218 corresponding to the first metal layer 214 is formed on the second wafer 216 , A third metal layer 217 is formed on the second wafer 216 , and the corrosion potential of the material forming the third metal layer 217 is higher than the corrosion potential of the material forming the first metal layer 214 and the second metal layer 218 .
  • the positive electrode of the voltage source for electrochemical anodic metal dissolution may be connected to the third metal layer 217 .
  • the third metal layer 217 connected to the positive electrode of the voltage source can function as the anode during the electrochemical anodic metal dissolution process.
  • the material forming the cathode 312 is an inert material.
  • cathode 312 may be formed of materials such as platinum, gold, lead, or graphite, or mixtures thereof.
  • the solution 310 for electrochemical anode metal dissolution may be an aqueous neutral electrolyte solution.
  • the neutral electrolyte aqueous solution may be one of the group consisting of : NaCl solution, Na2SO4 solution, MgCl2 solution, KCl solution, K2SO4 solution, K2NO3 solution, and Na2NO 3 solutions.
  • the neutral solution has less pollution to the environment, which is in line with the current industrial environmental protection trend.
  • the solution for dissolving the metal in the electrochemical anode may also be a weakly acidic solution or a weakly basic solution, such as MgSO 4 , etc., which is not limited herein.
  • Figure 3B schematically shows the reaction process of electrochemical anode metal dissolution.
  • the first and second metal layers 214/218 which have been bonded together, can be dissolved by utilizing electrochemical anodic metal dissolution.
  • the anode reaction can generate aluminum ions: Al ⁇ Al 3+ +3e -
  • the cathode reaction can generate hydrogen gas: 2H + +2e - ⁇ H 2 .
  • the metal regions such as the pads exposed by the passivation layer 212 and the first metal layer 214 may also be immersed in the solution, due to these metals
  • the region does not participate in the anodic reaction, so dissolution does not occur. This, to a certain extent, increases the degree of freedom of material selection for the metal regions, such as pads, formed on the first wafer.
  • the voltage applied by the voltage source may be within a predetermined range such that at least the first metal layer is 214 can dissolve but the third metal layer 217 does not dissolve.
  • the voltage of the voltage source is adjusted so that the aluminum can be dissolved without the chromium being dissolved during the electrochemical anodic metal dissolution process.
  • Figure 3C schematically shows the state after the electrochemical anode metal dissolution process has ended. As shown in FIG. 3C , the first metal layer 214 and the second metal layer 218 have been dissolved, so that the first wafer 210 and the second wafer 216 are debonded and separated.
  • the debonding speed of the first wafer 210 and the second wafer 216 can be controlled by appropriately adjusting the voltage value of the voltage source until the first wafer 210 completely separated from the second wafer 216 .
  • the removal rate of the bonded metal layer can be high, thereby improving the efficiency of debonding.
  • the speed of debonding can be controlled by selecting the corresponding materials and adjusting the voltage value of the voltage source used for electrochemical anode metal dissolution, which contributes to better controllability.
  • debonding by electrochemical anodic metal dissolution also avoids damage to wafers due to shear forces, thereby improving yield.
  • FIGS. 1 , 2A-2F, and 3A-3C Methods of temporary bonding and debonding of semiconductor devices according to exemplary embodiments of the present disclosure and various variations thereof are described above with respect to FIGS. 1 , 2A-2F, and 3A-3C. It will be understood that there is no requirement that the steps or operations described must be performed in the particular order described, nor that all steps or operations described must be performed to achieve desired results. For example, the step of forming the second metal layer on the second wafer may be performed before the step of forming the first metal layer on the first wafer.
  • a semiconductor device which can be manufactured by the above-described method.
  • Embodiments of methods of temporary bonding and debonding of semiconductor devices have been described so that the structure of the resulting semiconductor device will be clear.
  • Embodiments of semiconductor devices can provide the same or corresponding advantages as method embodiments, a detailed description of which is omitted for brevity.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur un procédé pour lier et dissocier temporairement un dispositif à semi-conducteur, et sur un dispositif à semi-conducteur. Le procédé de liaison et de dissociation temporaires du dispositif à semi-conducteur consiste à : former une première couche métallique sur une première tranche, la première tranche étant intérieurement pourvue d'une structure de dispositif, et la première couche métallique étant formée sur un côté de la première tranche à proximité de la structure de dispositif (110) ; former une seconde couche métallique correspondant à la première couche métallique sur une seconde tranche (120) ; lier la seconde couche métallique à la première couche métallique, de telle sorte qu'une seconde tranche est liée à la première tranche (130) ; réaliser un processus arrière sur un côté de la première tranche éloignée de la structure de dispositif (140) ; et réaliser un dissociation au moyen d'une dissolution de métal anodique électrochimique, de manière à séparer la première tranche de la seconde tranche (150).
PCT/CN2020/129749 2020-11-11 2020-11-18 Procédé de liaison et de dissociation temporaires de dispositif à semi-conducteur et dispositif à semi-conducteur WO2022099744A1 (fr)

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