JP3914431B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP3914431B2
JP3914431B2 JP2001392970A JP2001392970A JP3914431B2 JP 3914431 B2 JP3914431 B2 JP 3914431B2 JP 2001392970 A JP2001392970 A JP 2001392970A JP 2001392970 A JP2001392970 A JP 2001392970A JP 3914431 B2 JP3914431 B2 JP 3914431B2
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JP
Japan
Prior art keywords
bump
circuit board
adhesive
bare chip
semiconductor bare
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001392970A
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English (en)
Japanese (ja)
Other versions
JP2003197853A5 (enExample
JP2003197853A (ja
Inventor
浩二郎 中村
能彦 八木
道朗 吉野
一人 西田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2001392970A priority Critical patent/JP3914431B2/ja
Priority to US10/328,189 priority patent/US6966964B2/en
Publication of JP2003197853A publication Critical patent/JP2003197853A/ja
Publication of JP2003197853A5 publication Critical patent/JP2003197853A5/ja
Application granted granted Critical
Publication of JP3914431B2 publication Critical patent/JP3914431B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H10W74/012—
    • H10W72/00—
    • H10W74/15—
    • H10W90/00—
    • H10W72/01225—
    • H10W72/0711—
    • H10W72/07178—
    • H10W72/073—
    • H10W72/07331—
    • H10W72/07338—
    • H10W72/251—
    • H10W72/354—
    • H10W72/856—
    • H10W72/90—
    • H10W72/9415—
    • H10W90/724—
    • H10W90/734—

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  • Wire Bonding (AREA)
JP2001392970A 2001-12-26 2001-12-26 半導体装置の製造方法 Expired - Fee Related JP3914431B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001392970A JP3914431B2 (ja) 2001-12-26 2001-12-26 半導体装置の製造方法
US10/328,189 US6966964B2 (en) 2001-12-26 2002-12-26 Method and apparatus for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001392970A JP3914431B2 (ja) 2001-12-26 2001-12-26 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2003197853A JP2003197853A (ja) 2003-07-11
JP2003197853A5 JP2003197853A5 (enExample) 2005-07-28
JP3914431B2 true JP3914431B2 (ja) 2007-05-16

Family

ID=19188732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001392970A Expired - Fee Related JP3914431B2 (ja) 2001-12-26 2001-12-26 半導体装置の製造方法

Country Status (2)

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US (1) US6966964B2 (enExample)
JP (1) JP3914431B2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006154655A (ja) * 2004-12-01 2006-06-15 Bridgestone Corp 情報表示用パネルの製造方法および情報表示装置
KR100598459B1 (ko) 2004-12-10 2006-07-11 주식회사 쎄크 칩 본딩장치
CN100552948C (zh) * 2004-12-28 2009-10-21 松下电器产业株式会社 半导体芯片的安装结构体和其制造方法
JP2006210566A (ja) * 2005-01-27 2006-08-10 Akita Denshi Systems:Kk 半導体装置
US7170183B1 (en) * 2005-05-13 2007-01-30 Amkor Technology, Inc. Wafer level stacked package
DE102007010731A1 (de) * 2007-02-26 2008-08-28 Würth Elektronik GmbH & Co. KG Verfahren zum Einbetten von Chips und Leiterplatte
JP4952353B2 (ja) * 2007-04-18 2012-06-13 パナソニック株式会社 チップモジュールおよびメモリカード
JP5179787B2 (ja) * 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
JP2009049051A (ja) * 2007-08-14 2009-03-05 Elpida Memory Inc 半導体基板の接合方法及びそれにより製造された積層体
JP2010062365A (ja) * 2008-09-04 2010-03-18 Hitachi Ltd 半導体装置およびその製造方法
US8710654B2 (en) 2011-05-26 2014-04-29 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US9252130B2 (en) * 2013-03-29 2016-02-02 Stats Chippac, Ltd. Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bonding
FR3011679B1 (fr) * 2013-10-03 2017-01-27 Commissariat Energie Atomique Procede ameliore d'assemblage par collage direct entre deux elements, chaque element comprenant des portions de metal et de materiaux dielectriques
JP6189181B2 (ja) 2013-11-06 2017-08-30 東芝メモリ株式会社 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5366933A (en) * 1993-10-13 1994-11-22 Intel Corporation Method for constructing a dual sided, wire bonded integrated circuit chip package
JP3266815B2 (ja) * 1996-11-26 2002-03-18 シャープ株式会社 半導体集積回路装置の製造方法
US6071371A (en) * 1998-02-02 2000-06-06 Delco Electronics Corporation Method of simultaneously attaching surface-mount and chip-on-board dies to a circuit board
JP2002198395A (ja) * 2000-12-26 2002-07-12 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器

Also Published As

Publication number Publication date
US6966964B2 (en) 2005-11-22
JP2003197853A (ja) 2003-07-11
US20030138993A1 (en) 2003-07-24

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