JP3908175B2 - Semiconductor integrated circuit and evaluation circuit thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit including a test circuit for easily performing a shipping test and an evaluation circuit thereof.
[0002]
[Prior art]
As a shipment test of a semiconductor integrated circuit, for example, the phase of a data signal with respect to a clock signal output from the semiconductor integrated circuit or the phase difference between data signals is measured, and whether these measured values satisfy a specification. A test is performed. Further, in another device using the clock signal and data signal output from the semiconductor integrated circuit, an output timing test is performed to determine whether the data signal can be correctly taken in synchronization with the clock signal.
[0003]
For example, when a plurality of bits of data signals change simultaneously as in a data bus, if there is a phase shift between these data signals, a device that uses these data signals may malfunction. In addition, if the output timing of these data signals is shifted with respect to the clock signal and the setup time and hold time are insufficient, there is a problem that these data signals cannot be correctly captured in a device using these data signals. appear.
[0004]
Therefore, a test circuit is provided inside the semiconductor integrated circuit, or a test pattern for actually operating the semiconductor integrated circuit is created to perform the above test.
[0005]
For example, in Patent Document 1, when an original function is performed, an internal signal output from an internal circuit is selected by a selection unit, output from an output terminal via a final stage sequential circuit, and AC characteristics are evaluated. In this case, a semiconductor integrated circuit device is proposed in which a test signal generated by a test signal generator controlled by a controller is selected by a selector and output from an output terminal via a final stage sequential circuit. Has been.
[0006]
However, the conventional technique has a problem that the test circuit becomes too complicated, or the circuit scale of the test circuit itself increases significantly in proportion to the increase in the number of pins to be measured. Also, when it is difficult to actually change the data signal output from the semiconductor integrated circuit by operating the internal circuit, for example, when the circuit configuration is such that the data signal output from the semiconductor integrated circuit changes only rarely There is also a problem that the test pattern may become extremely long.
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-237445
[Problems to be solved by the invention]
An object of the present invention is to solve the problems based on the above prior art and easily measure the phase of a data signal relative to a clock signal and the phase difference between data signals, and test the output timing of the data signal relative to the clock signal. An object of the present invention is to provide a semiconductor integrated circuit and an evaluation circuit thereof.
[0009]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a semiconductor integrated circuit in which a clock signal and at least one data signal are output from first and at least one second output terminals, respectively.
A test flip-flop for outputting the data signal is provided, and the test flip-flop holds an output signal of an internal circuit in synchronization with a clock signal supplied from a clock tree shared with the clock signal during normal operation. The semiconductor integrated circuit is characterized in that the output signal of the test flip-flop is inverted and output in synchronization with the clock signal during the test operation.
[0010]
The present invention also provides an evaluation circuit for a semiconductor integrated circuit as described above,
A flip-flop that holds a data signal output from the second output terminal of the semiconductor integrated circuit in synchronization with a clock signal output from the first output terminal of the semiconductor integrated circuit;
An evaluation circuit is provided that evaluates an output timing of the data signal with respect to the clock signal based on an output signal of the flip-flop.
[0011]
The present invention also provides an evaluation circuit for a semiconductor integrated circuit as described above,
A logic circuit that determines and outputs whether the logics of the data signals output from the plurality of second output terminals of the semiconductor integrated circuit all match or are different, and
A flip-flop that holds the output of the logic circuit in synchronization with a clock signal output from the first output terminal of the semiconductor integrated circuit;
An evaluation circuit is provided that evaluates an output timing of the data signal with respect to the clock signal based on an output signal of the flip-flop.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor integrated circuit and its evaluation circuit of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.
[0013]
FIG. 1 is a schematic configuration diagram of an embodiment of a semiconductor integrated circuit and an evaluation circuit thereof according to the present invention. In the figure, an external clock signal is input from the clock input terminal CLKIN to the semiconductor integrated circuit 10, and the external clock signal is input to the clock tree 16 via the input buffer 14. The clock tree 16 generates a plurality of internal clock signals having substantially the same phase.
[0014]
In the present embodiment, the plurality of internal clock signals are respectively input to the clock input terminals of the two flip-flops 18a and 18b, and also output from the clock output terminal CLKOUT of the semiconductor integrated circuit 10 via the output buffer 20. Yes.
[0015]
A signal output from the data output terminal Q of the flip-flop 18a is output from the data output terminal DATA1 of the semiconductor integrated circuit 10 via the output timing adjustment buffer chain 22a and the output buffer 24a. The phase relationship between the clock signal output from the clock output terminal CLKOUT and the data signal output from the data output terminal DATA1 is adjusted by the buffer chain 22a for output timing adjustment.
[0016]
The output signal of the multiplexer 26a is input to the data input terminal D of the flip-flop 18a. The multiplexer 26a receives the output signal of the internal circuit 28a at its input terminal 0, the signal output from the inverted data output terminal Q 出力 of the flip-flop 18a at the input terminal 1, and the test signal ACtest at the selected input terminal. Is entered. In this embodiment, the normal operation mode is set when the test signal ACtest is at a low level, and the test mode is set when the test signal ACtest is at a high level.
[0017]
The flip-flop 18b, the output timing adjustment buffer chain 22b, the output buffer 24b, the multiplexer 26b, and the internal circuit 28b have the same configuration.
[0018]
In the semiconductor integrated circuit 10, when the test signal ACtest is at a low level, that is, in the normal operation mode, for example, the output signal of the internal circuit 28a is output from the multiplexer 26a. The output signal of the multiplexer 26a is held in the flip-flop 18a in synchronism with the rising edge of the internal clock signal. After the output timing is adjusted by the buffer chain for adjusting the output timing, the output signal is output from the data output terminal DATA1 via the output buffer 24a. Is output.
[0019]
When the test signal ACtest is at a high level, that is, in the test mode, the multiplexer 26a0 outputs a signal output from the inverted data output terminal Q￣ of the flip-flop 18a. That is, each time the clock signal rises, as shown in the timing chart of FIG. 2, the signal output from the data output terminal Q of the flip-flop 18a is inverted and output in the same manner, and the output timing is adjusted and the data output terminal DATA1 is Is output.
[0020]
Thus, in the semiconductor integrated circuit 10, in the test mode, the data output from the data output terminal DATA1 is inverted and output in synchronization with the rising edge of the clock signal. Therefore, the phase of the data output from the data output terminal DATA1 with respect to the clock signal output from the clock output terminal CLKOUT can be changed by simply inputting an external clock signal from the clock input terminal CLKIN without creating a dedicated test pattern. It can be measured easily.
[0021]
Although the data output from the data output terminal DATA1 has been described, the same applies to the data output from the data output terminal DATA2.
[0022]
Next, in FIG. 1, the evaluation circuit 12 includes an EOR circuit 30 and a flip-flop 32. Data signals output from the data output terminals DATA 1 and DATA 2 of the semiconductor integrated circuit 10 are input to the EOR circuit 30, and an output signal of the EOR circuit 30 is input to the data input terminal D of the flip-flop 32. A clock signal output from the clock output terminal CLKOUT of the semiconductor integrated circuit 10 is input to the clock input terminal of the flip-flop 32.
[0023]
In the evaluation circuit 12, an exclusive OR of the data signals output from the data output terminals DATA 1 and DATA 2 of the semiconductor integrated circuit 10 is calculated by the EOR circuit 30. The output signal of the EOR circuit 30 as a result of the operation is held in the flip-flop 32 at the rising edge of the clock signal output from the clock output terminal CLKOUT of the semiconductor integrated circuit 10 and output from the data output terminal Q of the flip-flop 32. Is done.
[0024]
As shown in the timing chart of FIG. 2, when there is a shift in the phase between the data signals output from the data output terminals DATA1 and DATA2 of the semiconductor integrated circuit 10, the shift in the phase between the two is detected by the EOR circuit 30, The EOR circuit 30 outputs a high level during a period in which the phases of both are shifted.
[0025]
Therefore, if the signal output from the data output terminal Q of the flip-flop 32 is at a high level, the data output terminal DATA1 or DATA2 is used for the rising edge of the clock signal output from the clock output terminal CLKOUT of the semiconductor integrated circuit 10. It can be determined that the setup time (or hold time) of the output data is insufficient.
[0026]
On the other hand, if the signal output from the data output terminal Q of the flip-flop 32 is at a low level, the data output from the data output terminals DATA1 and DATA2 of the semiconductor integrated circuit 10 is output from the clock output terminal CLKOUT. It can be determined that the setup time (or hold time) is satisfied with respect to the rising edge of the clock signal.
[0027]
As described above, the evaluation circuit 12 evaluates the output timing of the data signal with respect to the clock signal output from the semiconductor integrated circuit 10 only by monitoring the state of the signal output from the data output terminal Q of the flip-flop 32. be able to. That is, it can be confirmed that in the circuit using the clock signal and data output from the semiconductor integrated circuit 10, the data can be correctly held in the flip-flop at the rising edge of the clock signal.
[0028]
In the embodiment of FIG. 1, the evaluation circuit 12 is described as being provided outside the semiconductor integrated circuit 10. However, the evaluation circuit 12 of the present invention may be provided inside the semiconductor integrated circuit 10. Good. For example, a wiring connected to the first and second output terminals or an internal wiring branched from the input wiring of the buffers 20, 24a, 24b in the preceding stage is taken out, and the EOR circuit 30 and the flip-flop 32 are taken in and connected to the flip-flop. 32 outputs can be taken out as output terminals of the semiconductor integrated circuit 10.
[0029]
By doing so, the output timing of the data signal can be evaluated by monitoring the state of the output terminal.
[0030]
The present invention is particularly suitable for a semiconductor integrated circuit that requires a plurality of output signals to be changed in substantially the same phase, such as a data bus. The plurality of output signals are held in the flip-flop in synchronization with the clock signal and then output from the output terminal. When the present invention is applied to such a semiconductor integrated circuit, a test circuit can be configured with a very simple configuration in which only a multiplexer is added.
[0031]
Further, a flip-flop having a reset input terminal or the like may be used to set its initial state. In the illustrated example, only two data output terminals are shown, but the number of data output terminals is not limited at all. Further, although the data bus is illustrated as a preferred application example, this is not limited, and the present invention can be applied to any signal output from the semiconductor integrated circuit.
[0032]
The evaluation circuit of the present invention verifies that the output signal output from the semiconductor integrated circuit of the present invention can be held in the flip-flop in synchronization with the clock signal output from the semiconductor integrated circuit of the present invention. Anything is possible. Therefore, in the evaluation circuit of the present invention, the EOR circuit is not an essential element, and the EOR circuit may not be used, or the evaluation circuit may be configured using another gate circuit that is not the EOR circuit. .
[0033]
In the evaluation circuit, the wiring length of the clock signal and the data signal is determined in accordance with the device that actually uses the clock signal and the data signal of the semiconductor integrated circuit, and the same as the actual device as much as possible. It is preferable to perform the evaluation under conditions.
[0034]
Further, it is preferable to prepare a test flip-flop including the multiplexer and the flip-flop as a primitive cell in advance. For example, by designing a semiconductor integrated circuit using normal flip-flops and replacing the normal flip-flops with test flip-flops immediately before layout, it is not necessary to create a test pattern. The number of man-hours for performing can be greatly reduced.
[0035]
The present invention is basically as described above.
The semiconductor integrated circuit and its evaluation circuit of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.
[0036]
【The invention's effect】
As described above in detail, according to the present invention, the phase of a signal output from a semiconductor integrated circuit and the output timing test can be performed without adding a complicated circuit such as a timing generation circuit. . In addition, a test pattern for performing a test is not necessary, and therefore the man-hour required for creating the test pattern can be greatly reduced. Therefore, a shipment test of the semiconductor integrated circuit can be easily performed.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of an embodiment of a semiconductor integrated circuit and an evaluation circuit thereof according to the present invention.
2 is a timing chart of an embodiment illustrating operations of the semiconductor integrated circuit and the evaluation circuit shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 12 Evaluation circuit 14 Input buffer 16 Clock tree 18a, 18b Flip-flop 20 Output buffer 22a, 22b Buffer chain 24a, 24b Output buffer 26a, 26b Multiplexer 28a, 28b Internal circuit 30 EOR circuit 32 Flip-flop

Claims (3)

A semiconductor integrated circuit in which a clock signal and at least one data signal are respectively output from a first and at least one second output terminal;
A test flip-flop for outputting the data signal is provided, and the test flip-flop holds an output signal of an internal circuit in synchronization with a clock signal supplied from a clock tree shared with the clock signal during normal operation. A semiconductor integrated circuit, wherein the output signal of the test flip-flop is inverted and output in synchronization with the clock signal during a test operation. An evaluation circuit for a semiconductor integrated circuit according to claim 1,
A flip-flop that holds a data signal output from the second output terminal of the semiconductor integrated circuit in synchronization with a clock signal output from the first output terminal of the semiconductor integrated circuit;
An evaluation circuit for evaluating an output timing of the data signal with respect to the clock signal based on an output signal of the flip-flop. An evaluation circuit for a semiconductor integrated circuit according to claim 1,
A logic circuit that determines and outputs whether or not all the logics of data signals output from the plurality of second output terminals of the semiconductor integrated circuit are identical or different, and
A flip-flop that holds the output of the logic circuit in synchronization with a clock signal output from the first output terminal of the semiconductor integrated circuit;
An evaluation circuit for evaluating an output timing of the data signal with respect to the clock signal based on an output signal of the flip-flop.

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